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-rw-r--r--tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt1595
1 files changed, 797 insertions, 798 deletions
diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
index 7cef0aacd..c93b4b47a 100644
--- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
@@ -1,120 +1,120 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.233283 # Number of seconds simulated
-sim_ticks 233282768000 # Number of ticks simulated
-final_tick 233282768000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.233332 # Number of seconds simulated
+sim_ticks 233331881000 # Number of ticks simulated
+final_tick 233331881000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 136250 # Simulator instruction rate (inst/s)
-host_op_rate 147606 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 62910352 # Simulator tick rate (ticks/s)
-host_mem_usage 320784 # Number of bytes of host memory used
-host_seconds 3708.18 # Real time elapsed on the host
+host_inst_rate 137799 # Simulator instruction rate (inst/s)
+host_op_rate 149285 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 63638999 # Simulator tick rate (ticks/s)
+host_mem_usage 320760 # Number of bytes of host memory used
+host_seconds 3666.49 # Real time elapsed on the host
sim_insts 505237724 # Number of instructions simulated
sim_ops 547350945 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 683136 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 9221056 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.l2cache.prefetcher 16463744 # Number of bytes read from this memory
-system.physmem.bytes_read::total 26367936 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 683136 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 683136 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 18705728 # Number of bytes written to this memory
-system.physmem.bytes_written::total 18705728 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 10674 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 144079 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.l2cache.prefetcher 257246 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 411999 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 292277 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 292277 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 2928360 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 39527377 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.l2cache.prefetcher 70574197 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 113029935 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 2928360 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 2928360 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 80184782 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 80184782 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 80184782 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 2928360 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 39527377 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.l2cache.prefetcher 70574197 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 193214717 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 411999 # Number of read requests accepted
-system.physmem.writeReqs 292277 # Number of write requests accepted
-system.physmem.readBursts 411999 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 292277 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 26229824 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 138112 # Total number of bytes read from write queue
-system.physmem.bytesWritten 18703872 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 26367936 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 18705728 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 2158 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 4 # Number of DRAM write bursts merged with an existing one
+system.physmem.bytes_read::cpu.inst 689792 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 9194752 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.l2cache.prefetcher 16497856 # Number of bytes read from this memory
+system.physmem.bytes_read::total 26382400 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 689792 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 689792 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 18714240 # Number of bytes written to this memory
+system.physmem.bytes_written::total 18714240 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 10778 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 143668 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.l2cache.prefetcher 257779 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 412225 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 292410 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 292410 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 2956270 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 39406325 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.l2cache.prefetcher 70705537 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 113068132 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 2956270 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 2956270 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 80204385 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 80204385 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 80204385 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 2956270 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 39406325 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.l2cache.prefetcher 70705537 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 193272517 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 412225 # Number of read requests accepted
+system.physmem.writeReqs 292410 # Number of write requests accepted
+system.physmem.readBursts 412225 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 292410 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 26244608 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 137792 # Total number of bytes read from write queue
+system.physmem.bytesWritten 18711808 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 26382400 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 18714240 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 2153 # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts 7 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 3 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 26728 # Per bank write bursts
-system.physmem.perBankRdBursts::1 25477 # Per bank write bursts
-system.physmem.perBankRdBursts::2 25253 # Per bank write bursts
-system.physmem.perBankRdBursts::3 24678 # Per bank write bursts
-system.physmem.perBankRdBursts::4 27151 # Per bank write bursts
-system.physmem.perBankRdBursts::5 26546 # Per bank write bursts
-system.physmem.perBankRdBursts::6 25195 # Per bank write bursts
-system.physmem.perBankRdBursts::7 24195 # Per bank write bursts
-system.physmem.perBankRdBursts::8 25840 # Per bank write bursts
-system.physmem.perBankRdBursts::9 24882 # Per bank write bursts
-system.physmem.perBankRdBursts::10 24886 # Per bank write bursts
-system.physmem.perBankRdBursts::11 26093 # Per bank write bursts
-system.physmem.perBankRdBursts::12 26302 # Per bank write bursts
-system.physmem.perBankRdBursts::13 26067 # Per bank write bursts
-system.physmem.perBankRdBursts::14 24895 # Per bank write bursts
-system.physmem.perBankRdBursts::15 25653 # Per bank write bursts
-system.physmem.perBankWrBursts::0 18973 # Per bank write bursts
-system.physmem.perBankWrBursts::1 18287 # Per bank write bursts
-system.physmem.perBankWrBursts::2 17868 # Per bank write bursts
-system.physmem.perBankWrBursts::3 17935 # Per bank write bursts
-system.physmem.perBankWrBursts::4 18795 # Per bank write bursts
-system.physmem.perBankWrBursts::5 18319 # Per bank write bursts
-system.physmem.perBankWrBursts::6 17931 # Per bank write bursts
-system.physmem.perBankWrBursts::7 17655 # Per bank write bursts
-system.physmem.perBankWrBursts::8 18179 # Per bank write bursts
-system.physmem.perBankWrBursts::9 17927 # Per bank write bursts
-system.physmem.perBankWrBursts::10 17987 # Per bank write bursts
-system.physmem.perBankWrBursts::11 18662 # Per bank write bursts
-system.physmem.perBankWrBursts::12 18697 # Per bank write bursts
-system.physmem.perBankWrBursts::13 18344 # Per bank write bursts
-system.physmem.perBankWrBursts::14 18231 # Per bank write bursts
-system.physmem.perBankWrBursts::15 18458 # Per bank write bursts
+system.physmem.perBankRdBursts::0 26528 # Per bank write bursts
+system.physmem.perBankRdBursts::1 25539 # Per bank write bursts
+system.physmem.perBankRdBursts::2 25303 # Per bank write bursts
+system.physmem.perBankRdBursts::3 24713 # Per bank write bursts
+system.physmem.perBankRdBursts::4 27194 # Per bank write bursts
+system.physmem.perBankRdBursts::5 26607 # Per bank write bursts
+system.physmem.perBankRdBursts::6 24941 # Per bank write bursts
+system.physmem.perBankRdBursts::7 24442 # Per bank write bursts
+system.physmem.perBankRdBursts::8 25767 # Per bank write bursts
+system.physmem.perBankRdBursts::9 24723 # Per bank write bursts
+system.physmem.perBankRdBursts::10 25091 # Per bank write bursts
+system.physmem.perBankRdBursts::11 26187 # Per bank write bursts
+system.physmem.perBankRdBursts::12 26462 # Per bank write bursts
+system.physmem.perBankRdBursts::13 26013 # Per bank write bursts
+system.physmem.perBankRdBursts::14 25052 # Per bank write bursts
+system.physmem.perBankRdBursts::15 25510 # Per bank write bursts
+system.physmem.perBankWrBursts::0 18779 # Per bank write bursts
+system.physmem.perBankWrBursts::1 18326 # Per bank write bursts
+system.physmem.perBankWrBursts::2 18027 # Per bank write bursts
+system.physmem.perBankWrBursts::3 17939 # Per bank write bursts
+system.physmem.perBankWrBursts::4 18703 # Per bank write bursts
+system.physmem.perBankWrBursts::5 18353 # Per bank write bursts
+system.physmem.perBankWrBursts::6 17755 # Per bank write bursts
+system.physmem.perBankWrBursts::7 17808 # Per bank write bursts
+system.physmem.perBankWrBursts::8 18074 # Per bank write bursts
+system.physmem.perBankWrBursts::9 17824 # Per bank write bursts
+system.physmem.perBankWrBursts::10 18093 # Per bank write bursts
+system.physmem.perBankWrBursts::11 18724 # Per bank write bursts
+system.physmem.perBankWrBursts::12 18814 # Per bank write bursts
+system.physmem.perBankWrBursts::13 18339 # Per bank write bursts
+system.physmem.perBankWrBursts::14 18411 # Per bank write bursts
+system.physmem.perBankWrBursts::15 18403 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 233282750000 # Total gap between requests
+system.physmem.totGap 233331863000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 411999 # Read request sizes (log2)
+system.physmem.readPktSize::6 412225 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 292277 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 312898 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 47873 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 13110 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 9133 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 7330 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 6176 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 5273 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 4418 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 3450 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 96 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 40 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 27 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 11 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 6 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 292410 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 311682 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 49314 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 13194 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 9237 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 7343 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 6192 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 5234 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 4415 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 3338 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 64 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 32 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 14 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 10 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
@@ -148,31 +148,31 @@ system.physmem.wrQLenPdf::11 1 # Wh
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 6395 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 6689 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 13204 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 15353 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 16370 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 16918 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 17192 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 17443 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 17610 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 17839 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 18048 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 18366 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 18616 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 18818 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 19964 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 18185 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 17613 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 17459 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 108 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 40 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 19 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 6 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37 3 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 6393 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 6662 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 13233 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 15393 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 16401 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 16959 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 17206 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 17395 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 17650 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 17892 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 17983 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 18388 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 18586 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 18721 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 19985 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 18227 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 17652 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 17464 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33 97 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34 47 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35 29 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36 9 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37 6 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38 9 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
@@ -197,102 +197,102 @@ system.physmem.wrQLenPdf::60 0 # Wh
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 306889 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 146.413224 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 102.997180 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 182.093051 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 184151 60.01% 60.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 82036 26.73% 86.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 16582 5.40% 92.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 7394 2.41% 94.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 4756 1.55% 96.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 2254 0.73% 96.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 1661 0.54% 97.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 1625 0.53% 97.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 6430 2.10% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 306889 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 17312 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 23.673001 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 116.829793 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-511 17311 99.99% 99.99% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples 307255 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 146.312346 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 102.902161 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 182.114345 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 184693 60.11% 60.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 81851 26.64% 86.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 16642 5.42% 92.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 7320 2.38% 94.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 4729 1.54% 96.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 2259 0.74% 96.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 1737 0.57% 97.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 1607 0.52% 97.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 6417 2.09% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 307255 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 17328 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 23.664070 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 116.589701 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-511 17327 99.99% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::14848-15359 1 0.01% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 17312 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 17312 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 16.881238 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 16.838780 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 1.240848 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16 10485 60.56% 60.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17 306 1.77% 62.33% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18 5502 31.78% 94.11% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19 671 3.88% 97.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20 134 0.77% 98.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21 74 0.43% 99.19% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22 42 0.24% 99.43% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23 45 0.26% 99.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24 29 0.17% 99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25 14 0.08% 99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26 9 0.05% 99.99% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total 17328 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 17328 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 16.872807 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 16.831610 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 1.219578 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16 10506 60.63% 60.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17 279 1.61% 62.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18 5596 32.29% 94.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19 616 3.55% 98.09% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20 141 0.81% 98.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21 60 0.35% 99.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22 44 0.25% 99.50% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23 41 0.24% 99.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24 25 0.14% 99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25 12 0.07% 99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26 7 0.04% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28 1 0.01% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 17312 # Writes before turning the bus around for reads
-system.physmem.totQLat 9036310212 # Total ticks spent queuing
-system.physmem.totMemAccLat 16720828962 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 2049205000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 22048.33 # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::total 17328 # Writes before turning the bus around for reads
+system.physmem.totQLat 9022211140 # Total ticks spent queuing
+system.physmem.totMemAccLat 16711061140 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 2050360000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 22001.53 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 40798.33 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 112.44 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 80.18 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 113.03 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 80.18 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 40751.53 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 112.48 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 80.19 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 113.07 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 80.20 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 1.50 # Data bus utilization in percentage
+system.physmem.busUtil 1.51 # Data bus utilization in percentage
system.physmem.busUtilRead 0.88 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.63 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.15 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 21.78 # Average write queue length when enqueuing
-system.physmem.readRowHits 299552 # Number of row buffer hits during reads
-system.physmem.writeRowHits 95641 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 73.09 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 32.72 # Row buffer hit rate for writes
-system.physmem.avgGap 331237.68 # Average gap between requests
-system.physmem.pageHitRate 56.29 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 1156763160 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 631170375 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 1600435200 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 944401680 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 15236457600 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 74473770375 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 74637909000 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 168680907390 # Total energy per rank (pJ)
-system.physmem_0.averagePower 723.094931 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 123643637069 # Time in different power states
-system.physmem_0.memoryStateTime::REF 7789600000 # Time in different power states
+system.physmem.avgRdQLen 1.17 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 21.59 # Average write queue length when enqueuing
+system.physmem.readRowHits 299444 # Number of row buffer hits during reads
+system.physmem.writeRowHits 95740 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 73.02 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 32.74 # Row buffer hit rate for writes
+system.physmem.avgGap 331138.62 # Average gap between requests
+system.physmem.pageHitRate 56.26 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 1156823640 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 631203375 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 1601035800 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 944071200 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 15240017520 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 75187551735 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 74044498500 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 168805201770 # Total energy per rank (pJ)
+system.physmem_0.averagePower 723.458661 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 122654182736 # Time in different power states
+system.physmem_0.memoryStateTime::REF 7791420000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 101845250931 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 102885452264 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 1163007720 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 634577625 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 1595802000 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 949158000 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 15236457600 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 74040443550 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 75018020250 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 168637466745 # Total energy per rank (pJ)
-system.physmem_1.averagePower 722.908711 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 124281047938 # Time in different power states
-system.physmem_1.memoryStateTime::REF 7789600000 # Time in different power states
+system.physmem_1.actEnergy 1166024160 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 636223500 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 1597377600 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 950499360 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 15240017520 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 74554879950 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 74599507500 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 168744529590 # Total energy per rank (pJ)
+system.physmem_1.averagePower 723.198461 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 123580654566 # Time in different power states
+system.physmem_1.memoryStateTime::REF 7791420000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 101208398062 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 101958813184 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.cpu.branchPred.lookups 175089811 # Number of BP lookups
-system.cpu.branchPred.condPredicted 131337021 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 7444155 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 90376647 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 83876100 # Number of BTB hits
+system.cpu.branchPred.lookups 175090137 # Number of BP lookups
+system.cpu.branchPred.condPredicted 131338905 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 7443529 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 90540858 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 83879425 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 92.807271 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 12110019 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 104160 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 92.642622 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 12110692 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 104166 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
@@ -411,129 +411,129 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 548 # Number of system calls
-system.cpu.numCycles 466565537 # number of cpu cycles simulated
+system.cpu.numCycles 466663763 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 7838065 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 731795546 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 175089811 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 95986119 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 450385778 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 14940817 # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles 5837 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 243 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 14677 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 236716672 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 34578 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 465715008 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.701748 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 1.179403 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 7839248 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 731808788 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 175090137 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 95990117 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 450472274 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 14939659 # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles 5656 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 157 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 14269 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 236720425 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 34587 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 465801433 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.701462 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 1.179511 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 93791115 20.14% 20.14% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 132693411 28.49% 48.63% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 57855471 12.42% 61.05% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 181375011 38.95% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 93869731 20.15% 20.15% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 132699774 28.49% 48.64% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 57852108 12.42% 61.06% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 181379820 38.94% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 465715008 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.375274 # Number of branch fetches per cycle
-system.cpu.fetch.rate 1.568473 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 32367511 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 117249871 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 287084329 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 22031549 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 6981748 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 24050134 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 496459 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 715800999 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 30008433 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 6981748 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 63425626 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 54212557 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 40336788 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 276681526 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 24076763 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 686589929 # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts 13340569 # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents 9410638 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 2384158 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents 1669115 # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents 1841927 # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands 831018421 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 3019159141 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 723918647 # Number of integer rename lookups
+system.cpu.fetch.rateDist::total 465801433 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.375195 # Number of branch fetches per cycle
+system.cpu.fetch.rate 1.568171 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 32373679 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 117343382 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 287062106 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 22041011 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 6981255 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 24049971 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 496386 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 715809364 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 30003912 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 6981255 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 63434666 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 54211510 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 40338612 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 276664591 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 24170799 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 686600417 # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts 13340367 # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents 9416739 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 2386420 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents 1670076 # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents 1927738 # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands 831025477 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 3019202538 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 723925996 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 416 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 654123751 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 176894670 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 1544698 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 1534992 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 42289780 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 143526215 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 67981217 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 12855514 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 11197113 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 668159255 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 2978326 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 610231748 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 5860169 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 123786636 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 319274742 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 694 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 465715008 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.310312 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.101358 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 176901726 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 1544701 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 1534906 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 42308307 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 143530339 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 67981565 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 12860716 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 11266999 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 668170903 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 2978331 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 610248763 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 5854866 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 123798289 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 319264737 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 699 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 465801433 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 1.310105 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.101429 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 148574576 31.90% 31.90% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 101171602 21.72% 53.63% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 145766544 31.30% 84.93% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 63282576 13.59% 98.51% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 6919220 1.49% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 490 0.00% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 148653685 31.91% 31.91% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 101184506 21.72% 53.64% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 145749505 31.29% 84.93% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 63290175 13.59% 98.51% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 6923088 1.49% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 474 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 465715008 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 465801433 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 71921517 52.96% 52.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 30 0.00% 52.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 52.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 52.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 52.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 52.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 52.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 52.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 52.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 52.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 52.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 52.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 52.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 52.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 44556516 32.81% 85.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 19328890 14.23% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 71924616 52.97% 52.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 30 0.00% 52.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 52.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 52.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 52.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 52.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 52.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 52.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 52.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 52.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 52.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 52.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 52.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 52.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 44553347 32.81% 85.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 19296722 14.21% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 413144323 67.70% 67.70% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 351745 0.06% 67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 413148587 67.70% 67.70% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 351752 0.06% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.76% # Type of FU issued
@@ -561,84 +561,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.76% # Ty
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 134209580 21.99% 89.75% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 62526097 10.25% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 134215566 21.99% 89.75% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 62532855 10.25% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 610231748 # Type of FU issued
-system.cpu.iq.rate 1.307923 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 135806953 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.222550 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 1827845333 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 794952356 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 594966802 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total 610248763 # Type of FU issued
+system.cpu.iq.rate 1.307684 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 135774715 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.222491 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 1827928247 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 794975703 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 594980555 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 293 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 316 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 746038524 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 746023301 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 177 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 7273046 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads 7276983 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 27641459 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 25471 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 28891 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 11120740 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 27645583 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 25497 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 28922 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 11121088 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 225190 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 22470 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 225125 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 22421 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 6981748 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 23001930 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 919984 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 672625014 # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles 6981255 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 22978687 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 924846 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 672636723 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 143526215 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 67981217 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 1489784 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 258650 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 525178 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 28891 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 3821630 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 3731398 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 7553028 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 599382547 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 129570228 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 10849201 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewDispLoadInsts 143530339 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 67981565 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 1489789 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 258799 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 529739 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 28922 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 3821583 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 3731049 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 7552632 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 599397786 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 129576337 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 10850977 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 1487433 # number of nop insts executed
-system.cpu.iew.exec_refs 190523509 # number of memory reference insts executed
-system.cpu.iew.exec_branches 131370037 # Number of branches executed
-system.cpu.iew.exec_stores 60953281 # Number of stores executed
-system.cpu.iew.exec_rate 1.284670 # Inst execution rate
-system.cpu.iew.wb_sent 596261681 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 594966818 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 349901968 # num instructions producing a value
-system.cpu.iew.wb_consumers 570648646 # num instructions consuming a value
+system.cpu.iew.exec_nop 1487489 # number of nop insts executed
+system.cpu.iew.exec_refs 190533026 # number of memory reference insts executed
+system.cpu.iew.exec_branches 131372234 # Number of branches executed
+system.cpu.iew.exec_stores 60956689 # Number of stores executed
+system.cpu.iew.exec_rate 1.284432 # Inst execution rate
+system.cpu.iew.wb_sent 596275489 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 594980571 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 349907425 # num instructions producing a value
+system.cpu.iew.wb_consumers 570632122 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.275205 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.613165 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.274966 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.613193 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 110016162 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 110027797 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 6955495 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 448601420 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.223123 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.887905 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 6954955 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 448686365 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.222892 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.888131 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 219539851 48.94% 48.94% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 116349885 25.94% 74.87% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 43748468 9.75% 84.63% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 23302371 5.19% 89.82% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 11552802 2.58% 92.40% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 7777273 1.73% 94.13% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 8275373 1.84% 95.98% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 4252092 0.95% 96.92% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 13803305 3.08% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 219669318 48.96% 48.96% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 116312485 25.92% 74.88% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 43742979 9.75% 84.63% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 23278779 5.19% 89.82% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 11577691 2.58% 92.40% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 7777719 1.73% 94.13% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 8261206 1.84% 95.97% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 4236050 0.94% 96.92% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 13830138 3.08% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 448601420 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 448686365 # Number of insts commited each cycle
system.cpu.commit.committedInsts 506581608 # Number of instructions committed
system.cpu.commit.committedOps 548694829 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
@@ -684,182 +684,182 @@ system.cpu.commit.op_class_0::MemWrite 56860477 10.36% 100.00% # Cl
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 548694829 # Class of committed instruction
-system.cpu.commit.bw_lim_events 13803305 # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads 1093501968 # The number of ROB reads
-system.cpu.rob.rob_writes 1334565325 # The number of ROB writes
-system.cpu.timesIdled 13884 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 850529 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events 13830138 # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads 1093571715 # The number of ROB reads
+system.cpu.rob.rob_writes 1334590067 # The number of ROB writes
+system.cpu.timesIdled 13966 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 862330 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 505237724 # Number of Instructions Simulated
system.cpu.committedOps 547350945 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 0.923457 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.923457 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.082887 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.082887 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 611072880 # number of integer regfile reads
-system.cpu.int_regfile_writes 328111730 # number of integer regfile writes
+system.cpu.cpi 0.923652 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.923652 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.082659 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.082659 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 611088796 # number of integer regfile reads
+system.cpu.int_regfile_writes 328119086 # number of integer regfile writes
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
-system.cpu.cc_regfile_reads 2170116632 # number of cc regfile reads
-system.cpu.cc_regfile_writes 376537008 # number of cc regfile writes
-system.cpu.misc_regfile_reads 217962216 # number of misc regfile reads
+system.cpu.cc_regfile_reads 2170176811 # number of cc regfile reads
+system.cpu.cc_regfile_writes 376539852 # number of cc regfile writes
+system.cpu.misc_regfile_reads 217970841 # number of misc regfile reads
system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes
-system.cpu.dcache.tags.replacements 2820796 # number of replacements
-system.cpu.dcache.tags.tagsinuse 511.631791 # Cycle average of tags in use
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+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 344223500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 727200000 # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 727200000 # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 9979336000 # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 9979336000 # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 727200000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10323559500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 11050759500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 727200000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10323559500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 19018555494 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 30069314994 # number of overall MSHR miss cycles
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.074074 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.074074 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.007043 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.007043 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.144288 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.144288 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.061063 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.061063 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.144288 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.051069 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.053451 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.144288 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.051069 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.007131 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.007131 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.145739 # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.145739 # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.060860 # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.060860 # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.145739 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.050920 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.053342 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.145739 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.050920 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.148406 # mshr miss rate for overall accesses
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 69537.256777 # average HardPFReq mshr miss latency
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 69537.256777 # average HardPFReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 16500 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16500 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78794.341676 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78794.341676 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66995.737705 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66995.737705 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71076.233583 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71076.233583 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66995.737705 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71273.150333 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70978.094407 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66995.737705 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71273.150333 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 69537.256777 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70056.196140 # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.148517 # mshr miss rate for overall accesses
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 69015.083205 # average HardPFReq mshr miss latency
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 69015.083205 # average HardPFReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 16750 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16750 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 92483.476625 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 92483.476625 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67464.514333 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67464.514333 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71307.966587 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71307.966587 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67464.514333 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71856.555694 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71550.033021 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67464.514333 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71856.555694 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 69015.083205 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69925.549787 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadResp 2373352 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 2648520 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict 622852 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::HardPFReq 320716 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 2373490 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 2649541 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict 621819 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::HardPFReq 317371 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 27 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 27 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 521972 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 521972 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq 74017 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq 2299336 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 220623 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8440541 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 8661164 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4734912 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 331363264 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 336098176 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 721627 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 6511219 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 1.110823 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.313913 # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadExReq 521960 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 521960 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq 73994 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq 2299497 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 220555 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8440647 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 8661202 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4733440 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 331429632 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 336163072 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 718484 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 6508328 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1.110389 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.313375 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 5789625 88.92% 88.92% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 721594 11.08% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 5789877 88.96% 88.96% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 718451 11.04% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 6511219 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 5251055500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total 6508328 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 5252069500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 2.3 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 111049948 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 111018442 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 4231992466 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 4232215467 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 1.8 # Layer utilization (%)
-system.membus.trans_dist::ReadResp 408324 # Transaction distribution
-system.membus.trans_dist::Writeback 292277 # Transaction distribution
-system.membus.trans_dist::CleanEvict 103036 # Transaction distribution
+system.membus.trans_dist::ReadResp 408504 # Transaction distribution
+system.membus.trans_dist::Writeback 292410 # Transaction distribution
+system.membus.trans_dist::CleanEvict 103085 # Transaction distribution
system.membus.trans_dist::UpgradeReq 3 # Transaction distribution
system.membus.trans_dist::UpgradeResp 3 # Transaction distribution
-system.membus.trans_dist::ReadExReq 3675 # Transaction distribution
-system.membus.trans_dist::ReadExResp 3675 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 408324 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1219317 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 1219317 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 45073664 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 45073664 # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadExReq 3721 # Transaction distribution
+system.membus.trans_dist::ReadExResp 3721 # Transaction distribution
+system.membus.trans_dist::ReadSharedReq 408504 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1219951 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 1219951 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 45096640 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 45096640 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 807315 # Request fanout histogram
+system.membus.snoop_fanout::samples 807723 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 807315 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 807723 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 807315 # Request fanout histogram
-system.membus.reqLayer0.occupancy 2175050688 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 807723 # Request fanout histogram
+system.membus.reqLayer0.occupancy 2173813941 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.9 # Layer utilization (%)
-system.membus.respLayer1.occupancy 2177979128 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 2179181168 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.9 # Layer utilization (%)
---------- End Simulation Statistics ----------