diff options
Diffstat (limited to 'tests/long/se/20.parser/ref')
8 files changed, 140 insertions, 40 deletions
diff --git a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt index d4b67bdd9..aa609094f 100644 --- a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.412080 # Nu sim_ticks 412079966500 # Number of ticks simulated final_tick 412079966500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 240872 # Simulator instruction rate (inst/s) -host_op_rate 240872 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 162212982 # Simulator tick rate (ticks/s) -host_mem_usage 251076 # Number of bytes of host memory used -host_seconds 2540.36 # Real time elapsed on the host +host_inst_rate 523017 # Simulator instruction rate (inst/s) +host_op_rate 523017 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 352221098 # Simulator tick rate (ticks/s) +host_mem_usage 299640 # Number of bytes of host memory used +host_seconds 1169.95 # Real time elapsed on the host sim_insts 611901617 # Number of instructions simulated sim_ops 611901617 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 412079966500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 156608 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 24143296 # Number of bytes read from this memory system.physmem.bytes_read::total 24299904 # Number of bytes read from this memory @@ -282,6 +283,7 @@ system.physmem_1.memoryStateTime::REF 13760240000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 73580458750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 412079966500 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 123917421 # Number of BP lookups system.cpu.branchPred.condPredicted 87658943 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 6214661 # Number of conditional branches incorrect @@ -329,6 +331,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 485 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 412079966500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 824159933 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -375,6 +378,7 @@ system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Cl system.cpu.op_class_0::total 611901617 # Class of committed instruction system.cpu.tickCycles 739333991 # Number of cycles that the object actually ticked system.cpu.idleCycles 84825942 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 412079966500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 2535268 # number of replacements system.cpu.dcache.tags.tagsinuse 4087.644038 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 202570428 # Total number of references to valid blocks. @@ -392,6 +396,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::3 3145 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 414584966 # Number of tag accesses system.cpu.dcache.tags.data_accesses 414584966 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 412079966500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 146904269 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 146904269 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 55666159 # number of WriteReq hits @@ -488,6 +493,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22270.814661 system.cpu.dcache.demand_avg_mshr_miss_latency::total 22270.814661 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22270.814661 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 22270.814661 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 412079966500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 3158 # number of replacements system.cpu.icache.tags.tagsinuse 1117.678366 # Cycle average of tags in use system.cpu.icache.tags.total_refs 226045682 # Total number of references to valid blocks. @@ -506,6 +512,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 1590 system.cpu.icache.tags.occ_task_id_percent::1024 0.892578 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 452106322 # Number of tag accesses system.cpu.icache.tags.data_accesses 452106322 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 412079966500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 226045682 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 226045682 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 226045682 # number of demand (read+write) hits @@ -574,6 +581,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 45856.899318 system.cpu.icache.demand_avg_mshr_miss_latency::total 45856.899318 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 45856.899318 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 45856.899318 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 412079966500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 347705 # number of replacements system.cpu.l2cache.tags.tagsinuse 29504.977164 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3908748 # Total number of references to valid blocks. @@ -596,6 +604,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 18756 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.989685 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 41820503 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 41820503 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 412079966500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 2339413 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 2339413 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 3158 # number of WritebackClean hits @@ -742,6 +751,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 system.cpu.toL2Bus.snoop_filter.tot_snoops 2394 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2394 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 412079966500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 1766190 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 2633020 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 3158 # Transaction distribution @@ -774,6 +784,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 7479000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3809046000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 412079966500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 173378 # Transaction distribution system.membus.trans_dist::WritebackDirty 293607 # Transaction distribution system.membus.trans_dist::CleanEvict 51709 # Transaction distribution diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt index 6ebc4ae73..4d23ca501 100644 --- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.362632 # Nu sim_ticks 362631828500 # Number of ticks simulated final_tick 362631828500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 177215 # Simulator instruction rate (inst/s) -host_op_rate 191948 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 126858592 # Simulator tick rate (ticks/s) -host_mem_usage 271160 # Number of bytes of host memory used -host_seconds 2858.55 # Real time elapsed on the host +host_inst_rate 379372 # Simulator instruction rate (inst/s) +host_op_rate 410911 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 271571493 # Simulator tick rate (ticks/s) +host_mem_usage 317732 # Number of bytes of host memory used +host_seconds 1335.31 # Real time elapsed on the host sim_insts 506579366 # Number of instructions simulated sim_ops 548692589 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 362631828500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 179456 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 9032064 # Number of bytes read from this memory system.physmem.bytes_read::total 9211520 # Number of bytes read from this memory @@ -286,6 +287,7 @@ system.physmem_1.memoryStateTime::REF 12108980000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 57113763250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 362631828500 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 131880511 # Number of BP lookups system.cpu.branchPred.condPredicted 98032974 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 5909980 # Number of conditional branches incorrect @@ -300,6 +302,7 @@ system.cpu.branchPred.indirectHits 3881527 # Nu system.cpu.branchPred.indirectMisses 8121 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 53795 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 362631828500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -329,6 +332,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 362631828500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -358,6 +362,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 362631828500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -387,6 +392,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 362631828500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -417,6 +423,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 362631828500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 725263657 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -463,6 +470,7 @@ system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Cl system.cpu.op_class_0::total 548692589 # Class of committed instruction system.cpu.tickCycles 688919604 # Number of cycles that the object actually ticked system.cpu.idleCycles 36344053 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 362631828500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 1141477 # number of replacements system.cpu.dcache.tags.tagsinuse 4070.722142 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 170992714 # Total number of references to valid blocks. @@ -480,6 +488,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::3 3497 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 346245015 # Number of tag accesses system.cpu.dcache.tags.data_accesses 346245015 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 362631828500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 114475063 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 114475063 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 53537828 # number of WriteReq hits @@ -600,6 +609,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20520.422763 system.cpu.dcache.demand_avg_mshr_miss_latency::total 20520.422763 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20521.099485 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 20521.099485 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 362631828500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 18130 # number of replacements system.cpu.icache.tags.tagsinuse 1186.413401 # Cycle average of tags in use system.cpu.icache.tags.total_refs 198770599 # Total number of references to valid blocks. @@ -618,6 +628,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 1397 system.cpu.icache.tags.occ_task_id_percent::1024 0.913574 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 397601201 # Number of tag accesses system.cpu.icache.tags.data_accesses 397601201 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 362631828500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 198770599 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 198770599 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 198770599 # number of demand (read+write) hits @@ -686,6 +697,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21750.787461 system.cpu.icache.demand_avg_mshr_miss_latency::total 21750.787461 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21750.787461 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 21750.787461 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 362631828500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 112376 # number of replacements system.cpu.l2cache.tags.tagsinuse 27628.930561 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1772118 # Total number of references to valid blocks. @@ -708,6 +720,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 25849 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.952515 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 19061751 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 19061751 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 362631828500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 1069336 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 1069336 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 17893 # number of WritebackClean hits @@ -860,6 +873,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4997 system.cpu.toL2Bus.snoop_filter.tot_snoops 2608 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2605 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 3 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 362631828500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 808883 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 1166546 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 18130 # Transaction distribution @@ -892,6 +906,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 30027947 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 1718367983 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 362631828500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 42981 # Transaction distribution system.membus.trans_dist::WritebackDirty 97210 # Transaction distribution system.membus.trans_dist::CleanEvict 12558 # Transaction distribution diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index b5fc0a42a..b6b8a4259 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.232865 # Nu sim_ticks 232864525000 # Number of ticks simulated final_tick 232864525000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 230904 # Simulator instruction rate (inst/s) -host_op_rate 250150 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 106424359 # Simulator tick rate (ticks/s) -host_mem_usage 342436 # Number of bytes of host memory used -host_seconds 2188.08 # Real time elapsed on the host +host_inst_rate 221507 # Simulator instruction rate (inst/s) +host_op_rate 239970 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 102093126 # Simulator tick rate (ticks/s) +host_mem_usage 343096 # Number of bytes of host memory used +host_seconds 2280.90 # Real time elapsed on the host sim_insts 505234934 # Number of instructions simulated sim_ops 547348155 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 523840 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 10146304 # Number of bytes read from this memory system.physmem.bytes_read::cpu.l2cache.prefetcher 16460800 # Number of bytes read from this memory @@ -293,6 +294,7 @@ system.physmem_1.memoryStateTime::REF 7775820000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 108384997620 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 174583649 # Number of BP lookups system.cpu.branchPred.condPredicted 131051926 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 7234327 # Number of conditional branches incorrect @@ -307,6 +309,7 @@ system.cpu.branchPred.indirectHits 4673781 # Nu system.cpu.branchPred.indirectMisses 14023 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 53864 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -336,6 +339,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -365,6 +369,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -394,6 +399,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -424,6 +430,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 232864525000 # Cumulative time (in ticks) in various power states system.cpu.numCycles 465729051 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -713,6 +720,7 @@ system.cpu.cc_regfile_reads 2166261838 # nu system.cpu.cc_regfile_writes 376539611 # number of cc regfile writes system.cpu.misc_regfile_reads 217603177 # number of misc regfile reads system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 2817145 # number of replacements system.cpu.dcache.tags.tagsinuse 511.627957 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 168870791 # Total number of references to valid blocks. @@ -729,6 +737,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 355267161 # Number of tag accesses system.cpu.dcache.tags.data_accesses 355267161 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 114168570 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 114168570 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 51722271 # number of WriteReq hits @@ -859,6 +868,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12117.964016 system.cpu.dcache.demand_avg_mshr_miss_latency::total 12117.964016 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12118.158615 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 12118.158615 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 76528 # number of replacements system.cpu.icache.tags.tagsinuse 466.435319 # Cycle average of tags in use system.cpu.icache.tags.total_refs 235186472 # Total number of references to valid blocks. @@ -877,6 +887,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 17 system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 470619957 # Number of tag accesses system.cpu.icache.tags.data_accesses 470619957 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 235186472 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 235186472 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 235186472 # number of demand (read+write) hits @@ -951,12 +962,14 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14634.139793 system.cpu.icache.demand_avg_mshr_miss_latency::total 14634.139793 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14634.139793 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 14634.139793 # average overall mshr miss latency +system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.prefetcher.num_hwpf_issued 8513492 # number of hwpf issued system.cpu.l2cache.prefetcher.pfIdentified 8514887 # number of prefetch candidates identified system.cpu.l2cache.prefetcher.pfBufferHit 402 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu.l2cache.prefetcher.pfSpanPage 743841 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 395630 # number of replacements system.cpu.l2cache.tags.tagsinuse 15127.357564 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3184940 # Total number of references to valid blocks. @@ -985,6 +998,7 @@ system.cpu.l2cache.tags.occ_task_id_percent::1022 0.064270 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908081 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 94885258 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 94885258 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 2350571 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 2350571 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 519224 # number of WritebackClean hits @@ -1170,6 +1184,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 23913 system.cpu.toL2Bus.snoop_filter.tot_snoops 261080 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 244791 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 16289 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 2372715 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 2642925 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 543102 # Transaction distribution @@ -1208,6 +1223,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 115689827 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 4226522955 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.8 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 420223 # Transaction distribution system.membus.trans_dist::WritebackDirty 292354 # Transaction distribution system.membus.trans_dist::CleanEvict 98859 # Transaction distribution diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt index cec661f19..826ec1511 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.279361 # Nu sim_ticks 279360903000 # Number of ticks simulated final_tick 279360903000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2212896 # Simulator instruction rate (inst/s) -host_op_rate 2396859 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1220336248 # Simulator tick rate (ticks/s) -host_mem_usage 304900 # Number of bytes of host memory used -host_seconds 228.92 # Real time elapsed on the host +host_inst_rate 2143205 # Simulator instruction rate (inst/s) +host_op_rate 2321375 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1181904303 # Simulator tick rate (ticks/s) +host_mem_usage 305572 # Number of bytes of host memory used +host_seconds 236.37 # Real time elapsed on the host sim_insts 506578818 # Number of instructions simulated sim_ops 548692039 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 279360903000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 2066434344 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 422848347 # Number of bytes read from this memory system.physmem.bytes_read::total 2489282691 # Number of bytes read from this memory @@ -35,7 +36,9 @@ system.physmem.bw_write::total 773431764 # Wr system.physmem.bw_total::cpu.inst 7397006245 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2287059270 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 9684065515 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 279360903000 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 279360903000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -65,6 +68,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 279360903000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -94,6 +98,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 279360903000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -123,6 +128,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 279360903000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -153,6 +159,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 279360903000 # Cumulative time (in ticks) in various power states system.cpu.numCycles 558721807 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -213,6 +220,7 @@ system.cpu.op_class::MemWrite 56860222 10.36% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 548692589 # Class of executed instruction +system.membus.pwrStateResidencyTicks::UNDEFINED 279360903000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 630707528 # Transaction distribution system.membus.trans_dist::ReadResp 632196069 # Transaction distribution system.membus.trans_dist::WriteReq 54239049 # Transaction distribution diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt index 925783e41..59b7a6f8a 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.708539 # Nu sim_ticks 708539449500 # Number of ticks simulated final_tick 708539449500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1440714 # Simulator instruction rate (inst/s) -host_op_rate 1560229 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2021455048 # Simulator tick rate (ticks/s) -host_mem_usage 314896 # Number of bytes of host memory used -host_seconds 350.51 # Real time elapsed on the host +host_inst_rate 1462928 # Simulator instruction rate (inst/s) +host_op_rate 1584286 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2052623495 # Simulator tick rate (ticks/s) +host_mem_usage 315564 # Number of bytes of host memory used +host_seconds 345.19 # Real time elapsed on the host sim_insts 504984064 # Number of instructions simulated sim_ops 546875315 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 147392 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 8963904 # Number of bytes read from this memory system.physmem.bytes_read::total 9111296 # Number of bytes read from this memory @@ -36,7 +37,9 @@ system.physmem.bw_total::writebacks 8701167 # To system.physmem.bw_total::cpu.inst 208022 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 12651242 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 21560431 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -66,6 +69,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -95,6 +99,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -124,6 +129,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -154,6 +160,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 708539449500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 1417078899 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -214,6 +221,7 @@ system.cpu.op_class::MemWrite 56860222 10.36% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 548692589 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 1136276 # number of replacements system.cpu.dcache.tags.tagsinuse 4065.261181 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 170177272 # Total number of references to valid blocks. @@ -232,6 +240,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 165 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 343775660 # Number of tag accesses system.cpu.dcache.tags.data_accesses 343775660 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 113315079 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 113315079 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 53882541 # number of WriteReq hits @@ -344,6 +353,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18027.042954 system.cpu.dcache.demand_avg_mshr_miss_latency::total 18027.042954 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18027.080637 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 18027.080637 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 9788 # number of replacements system.cpu.icache.tags.tagsinuse 983.198764 # Cycle average of tags in use system.cpu.icache.tags.total_refs 516597066 # Total number of references to valid blocks. @@ -362,6 +372,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 1402 system.cpu.icache.tags.occ_task_id_percent::1024 0.846191 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 1033228695 # Number of tag accesses system.cpu.icache.tags.data_accesses 1033228695 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 516597066 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 516597066 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 516597066 # number of demand (read+write) hits @@ -430,6 +441,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21846.193907 system.cpu.icache.demand_avg_mshr_miss_latency::total 21846.193907 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21846.193907 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 21846.193907 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 110394 # number of replacements system.cpu.l2cache.tags.tagsinuse 27252.086651 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1747015 # Total number of references to valid blocks. @@ -451,6 +463,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27176 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.951782 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 18853226 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 18853226 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 1065708 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 1065708 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 9751 # number of WritebackClean hits @@ -597,6 +610,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3565 system.cpu.toL2Bus.snoop_filter.tot_snoops 2146 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2145 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 795385 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 1162038 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 9788 # Transaction distribution @@ -629,6 +643,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 17281500 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 1710558000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 41576 # Transaction distribution system.membus.trans_dist::WritebackDirty 96330 # Transaction distribution system.membus.trans_dist::CleanEvict 11920 # Transaction distribution diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index b6e16dfe3..2ac1aa390 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.481958 # Nu sim_ticks 481957625500 # Number of ticks simulated final_tick 481957625500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 86883 # Simulator instruction rate (inst/s) -host_op_rate 160778 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 50643012 # Simulator tick rate (ticks/s) -host_mem_usage 314272 # Number of bytes of host memory used -host_seconds 9516.76 # Real time elapsed on the host +host_inst_rate 134289 # Simulator instruction rate (inst/s) +host_op_rate 248503 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 78275315 # Simulator tick rate (ticks/s) +host_mem_usage 362988 # Number of bytes of host memory used +host_seconds 6157.21 # Real time elapsed on the host sim_insts 826847303 # Number of instructions simulated sim_ops 1530082520 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 154624 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 24604096 # Number of bytes read from this memory system.physmem.bytes_read::total 24758720 # Number of bytes read from this memory @@ -284,6 +285,7 @@ system.physmem_1.memoryStateTime::REF 16093480000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 84631916750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 297786504 # Number of BP lookups system.cpu.branchPred.condPredicted 297786504 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 23596621 # Number of conditional branches incorrect @@ -298,8 +300,12 @@ system.cpu.branchPred.indirectHits 119907455 # Nu system.cpu.branchPred.indirectMisses 109794733 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 11576014 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 551 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 481957625500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 963915252 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -594,6 +600,7 @@ system.cpu.cc_regfile_reads 617820038 # nu system.cpu.cc_regfile_writes 419954937 # number of cc regfile writes system.cpu.misc_regfile_reads 1064369445 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 2545945 # number of replacements system.cpu.dcache.tags.tagsinuse 4088.303608 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 421067815 # Total number of references to valid blocks. @@ -611,6 +618,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::3 3418 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 851394195 # Number of tag accesses system.cpu.dcache.tags.data_accesses 851394195 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 272697526 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 272697526 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 148366944 # number of WriteReq hits @@ -707,6 +715,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22452.333150 system.cpu.dcache.demand_avg_mshr_miss_latency::total 22452.333150 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22452.333150 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 22452.333150 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 4014 # number of replacements system.cpu.icache.tags.tagsinuse 1083.903563 # Cycle average of tags in use system.cpu.icache.tags.total_refs 216343916 # Total number of references to valid blocks. @@ -725,6 +734,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 1566 system.cpu.icache.tags.occ_task_id_percent::1024 0.841797 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 432715084 # Number of tag accesses system.cpu.icache.tags.data_accesses 432715084 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 216344175 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 216344175 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 216344175 # number of demand (read+write) hits @@ -799,6 +809,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 32980.378890 system.cpu.icache.demand_avg_mshr_miss_latency::total 32980.378890 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 32980.378890 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 32980.378890 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 355161 # number of replacements system.cpu.l2cache.tags.tagsinuse 29604.694298 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3909300 # Total number of references to valid blocks. @@ -821,6 +832,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 20752 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987732 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 41979246 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 41979246 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 2337968 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 2337968 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 3923 # number of WritebackClean hits @@ -987,6 +999,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 8246 system.cpu.toL2Bus.snoop_filter.tot_snoops 2834 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2829 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 5 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 1773348 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 2632888 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 4014 # Transaction distribution @@ -1021,6 +1034,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 11087994 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3825891006 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 180179 # Transaction distribution system.membus.trans_dist::WritebackDirty 294920 # Transaction distribution system.membus.trans_dist::CleanEvict 57436 # Transaction distribution diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt index 74fbe2728..8deb96433 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.885773 # Nu sim_ticks 885772926000 # Number of ticks simulated final_tick 885772926000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 772132 # Simulator instruction rate (inst/s) -host_op_rate 1428832 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 827158459 # Simulator tick rate (ticks/s) -host_mem_usage 268696 # Number of bytes of host memory used -host_seconds 1070.86 # Real time elapsed on the host +host_inst_rate 1531547 # Simulator instruction rate (inst/s) +host_op_rate 2834130 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1640692833 # Simulator tick rate (ticks/s) +host_mem_usage 315956 # Number of bytes of host memory used +host_seconds 539.88 # Real time elapsed on the host sim_insts 826847304 # Number of instructions simulated sim_ops 1530082521 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 885772926000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 8546485088 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 2285527276 # Number of bytes read from this memory system.physmem.bytes_read::total 10832012364 # Number of bytes read from this memory @@ -35,9 +36,14 @@ system.physmem.bw_write::total 1119742368 # Wr system.physmem.bw_total::cpu.inst 9648618554 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3700005559 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 13348624112 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 885772926000 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 885772926000 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 885772926000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 885772926000 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 551 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 885772926000 # Cumulative time (in ticks) in various power states system.cpu.numCycles 1771545853 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -98,6 +104,7 @@ system.cpu.op_class::MemWrite 149158195 9.75% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 1530082521 # Class of executed instruction +system.membus.pwrStateResidencyTicks::UNDEFINED 885772926000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 1452393978 # Transaction distribution system.membus.trans_dist::ReadResp 1452393978 # Transaction distribution system.membus.trans_dist::WriteReq 149158211 # Transaction distribution diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt index 4d088ccd8..38495841e 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 1.650501 # Nu sim_ticks 1650501252500 # Number of ticks simulated final_tick 1650501252500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 482495 # Simulator instruction rate (inst/s) -host_op_rate 892859 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 963127288 # Simulator tick rate (ticks/s) -host_mem_usage 277668 # Number of bytes of host memory used -host_seconds 1713.69 # Real time elapsed on the host +host_inst_rate 943240 # Simulator instruction rate (inst/s) +host_op_rate 1745467 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1882837072 # Simulator tick rate (ticks/s) +host_mem_usage 326104 # Number of bytes of host memory used +host_seconds 876.60 # Real time elapsed on the host sim_insts 826847304 # Number of instructions simulated sim_ops 1530082521 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 115776 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 24258944 # Number of bytes read from this memory system.physmem.bytes_read::total 24374720 # Number of bytes read from this memory @@ -36,9 +37,14 @@ system.physmem.bw_total::writebacks 11369424 # To system.physmem.bw_total::cpu.inst 70146 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 14697925 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 26137495 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 551 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 1650501252500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 3301002505 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -99,6 +105,7 @@ system.cpu.op_class::MemWrite 149158195 9.75% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 1530082521 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 2517016 # number of replacements system.cpu.dcache.tags.tagsinuse 4086.386474 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 530720441 # Total number of references to valid blocks. @@ -117,6 +124,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 1069004218 # Number of tag accesses system.cpu.dcache.tags.data_accesses 1069004218 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 382353600 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 382353600 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 148366841 # number of WriteReq hits @@ -205,6 +213,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19367.106658 system.cpu.dcache.demand_avg_mshr_miss_latency::total 19367.106658 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19367.106658 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 19367.106658 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 1253 # number of replacements system.cpu.icache.tags.tagsinuse 881.361687 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1068307822 # Total number of references to valid blocks. @@ -223,6 +232,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 1507 system.cpu.icache.tags.occ_task_id_percent::1024 0.762207 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 2136624086 # Number of tag accesses system.cpu.icache.tags.data_accesses 2136624086 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 1068307822 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1068307822 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1068307822 # number of demand (read+write) hits @@ -291,6 +301,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 43511.371713 system.cpu.icache.demand_avg_mshr_miss_latency::total 43511.371713 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 43511.371713 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 43511.371713 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 348438 # number of replacements system.cpu.l2cache.tags.tagsinuse 29288.734166 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3851952 # Total number of references to valid blocks. @@ -312,6 +323,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 24060 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987549 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 41509728 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 41509728 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 2325221 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 2325221 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 1253 # number of WritebackClean hits @@ -458,6 +470,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 system.cpu.toL2Bus.snoop_filter.tot_snoops 1729 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1729 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 1732556 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 2618429 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 1253 # Transaction distribution @@ -490,6 +503,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 4221000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3781668000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 174499 # Transaction distribution system.membus.trans_dist::WritebackDirty 293207 # Transaction distribution system.membus.trans_dist::CleanEvict 53507 # Transaction distribution |