diff options
Diffstat (limited to 'tests/long/se/20.parser/ref')
6 files changed, 3041 insertions, 3003 deletions
diff --git a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt index d97d6a9aa..8a81dcd7c 100644 --- a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt @@ -1,100 +1,100 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.409306 # Number of seconds simulated -sim_ticks 409306011500 # Number of ticks simulated -final_tick 409306011500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.409289 # Number of seconds simulated +sim_ticks 409289296500 # Number of ticks simulated +final_tick 409289296500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 215743 # Simulator instruction rate (inst/s) -host_op_rate 215743 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 144312578 # Simulator tick rate (ticks/s) -host_mem_usage 243356 # Number of bytes of host memory used -host_seconds 2836.25 # Real time elapsed on the host +host_inst_rate 309220 # Simulator instruction rate (inst/s) +host_op_rate 309220 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 206831646 # Simulator tick rate (ticks/s) +host_mem_usage 269756 # Number of bytes of host memory used +host_seconds 1978.85 # Real time elapsed on the host sim_insts 611901617 # Number of instructions simulated sim_ops 611901617 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 24320640 # Number of bytes read from this memory -system.physmem.bytes_read::total 24320640 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 170752 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 170752 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18724096 # Number of bytes written to this memory -system.physmem.bytes_written::total 18724096 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 380010 # Number of read requests responded to by this memory -system.physmem.num_reads::total 380010 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 292564 # Number of write requests responded to by this memory -system.physmem.num_writes::total 292564 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 59419210 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 59419210 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 417174 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 417174 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 45745959 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 45745959 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 45745959 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 59419210 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 105165169 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 380010 # Number of read requests accepted -system.physmem.writeReqs 292564 # Number of write requests accepted -system.physmem.readBursts 380010 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 292564 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 24298688 # Total number of bytes read from DRAM +system.physmem.bytes_read::cpu.inst 24320576 # Number of bytes read from this memory +system.physmem.bytes_read::total 24320576 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 171008 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 171008 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18723776 # Number of bytes written to this memory +system.physmem.bytes_written::total 18723776 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 380009 # Number of read requests responded to by this memory +system.physmem.num_reads::total 380009 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 292559 # Number of write requests responded to by this memory +system.physmem.num_writes::total 292559 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 59421481 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 59421481 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 417817 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 417817 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 45747045 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 45747045 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 45747045 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 59421481 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 105168526 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 380009 # Number of read requests accepted +system.physmem.writeReqs 292559 # Number of write requests accepted +system.physmem.readBursts 380009 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 292559 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 24298624 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 21952 # Total number of bytes read from write queue -system.physmem.bytesWritten 18722368 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 24320640 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18724096 # Total written bytes from the system interface side +system.physmem.bytesWritten 18721984 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 24320576 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18723776 # Total written bytes from the system interface side system.physmem.servicedByWrQ 343 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 23736 # Per bank write bursts system.physmem.perBankRdBursts::1 23211 # Per bank write bursts system.physmem.perBankRdBursts::2 23514 # Per bank write bursts -system.physmem.perBankRdBursts::3 24536 # Per bank write bursts +system.physmem.perBankRdBursts::3 24530 # Per bank write bursts system.physmem.perBankRdBursts::4 25475 # Per bank write bursts system.physmem.perBankRdBursts::5 23585 # Per bank write bursts -system.physmem.perBankRdBursts::6 23685 # Per bank write bursts -system.physmem.perBankRdBursts::7 23974 # Per bank write bursts -system.physmem.perBankRdBursts::8 23182 # Per bank write bursts +system.physmem.perBankRdBursts::6 23686 # Per bank write bursts +system.physmem.perBankRdBursts::7 23976 # Per bank write bursts +system.physmem.perBankRdBursts::8 23181 # Per bank write bursts system.physmem.perBankRdBursts::9 23951 # Per bank write bursts -system.physmem.perBankRdBursts::10 24679 # Per bank write bursts -system.physmem.perBankRdBursts::11 22748 # Per bank write bursts -system.physmem.perBankRdBursts::12 23716 # Per bank write bursts -system.physmem.perBankRdBursts::13 24414 # Per bank write bursts -system.physmem.perBankRdBursts::14 22802 # Per bank write bursts -system.physmem.perBankRdBursts::15 22459 # Per bank write bursts +system.physmem.perBankRdBursts::10 24677 # Per bank write bursts +system.physmem.perBankRdBursts::11 22749 # Per bank write bursts +system.physmem.perBankRdBursts::12 23715 # Per bank write bursts +system.physmem.perBankRdBursts::13 24413 # Per bank write bursts +system.physmem.perBankRdBursts::14 22806 # Per bank write bursts +system.physmem.perBankRdBursts::15 22461 # Per bank write bursts system.physmem.perBankWrBursts::0 17754 # Per bank write bursts -system.physmem.perBankWrBursts::1 17435 # Per bank write bursts +system.physmem.perBankWrBursts::1 17434 # Per bank write bursts system.physmem.perBankWrBursts::2 17902 # Per bank write bursts -system.physmem.perBankWrBursts::3 18771 # Per bank write bursts +system.physmem.perBankWrBursts::3 18770 # Per bank write bursts system.physmem.perBankWrBursts::4 19442 # Per bank write bursts system.physmem.perBankWrBursts::5 18539 # Per bank write bursts system.physmem.perBankWrBursts::6 18677 # Per bank write bursts -system.physmem.perBankWrBursts::7 18571 # Per bank write bursts -system.physmem.perBankWrBursts::8 18354 # Per bank write bursts +system.physmem.perBankWrBursts::7 18570 # Per bank write bursts +system.physmem.perBankWrBursts::8 18353 # Per bank write bursts system.physmem.perBankWrBursts::9 18833 # Per bank write bursts system.physmem.perBankWrBursts::10 19131 # Per bank write bursts -system.physmem.perBankWrBursts::11 17964 # Per bank write bursts -system.physmem.perBankWrBursts::12 18221 # Per bank write bursts -system.physmem.perBankWrBursts::13 18695 # Per bank write bursts -system.physmem.perBankWrBursts::14 17147 # Per bank write bursts +system.physmem.perBankWrBursts::11 17963 # Per bank write bursts +system.physmem.perBankWrBursts::12 18220 # Per bank write bursts +system.physmem.perBankWrBursts::13 18694 # Per bank write bursts +system.physmem.perBankWrBursts::14 17148 # Per bank write bursts system.physmem.perBankWrBursts::15 17101 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 409305930000 # Total gap between requests +system.physmem.totGap 409289215500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 380010 # Read request sizes (log2) +system.physmem.readPktSize::6 380009 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 292564 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 378272 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1380 # What read queue length does an incoming req see +system.physmem.writePktSize::6 292559 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 378276 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1375 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 15 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -140,29 +140,29 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6975 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 7537 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 16938 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 17305 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 17384 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 17418 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17392 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17374 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6993 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 7538 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 16933 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 17310 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 17382 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 17417 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17401 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17377 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 17382 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 17390 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 17383 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 17383 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 17565 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 17454 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 17428 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17567 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17327 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17272 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 17387 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 17377 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 17385 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 17562 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 17443 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 17429 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17559 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17324 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17269 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 32 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 13 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 10 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 3 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 3 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see @@ -189,37 +189,37 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 141944 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 303.070281 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 179.645979 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 325.191162 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 50836 35.81% 35.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 38595 27.19% 63.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 13069 9.21% 72.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 8075 5.69% 77.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 5863 4.13% 82.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3755 2.65% 84.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3005 2.12% 86.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2490 1.75% 88.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 16256 11.45% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 141944 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17252 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 22.005912 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 228.974837 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 17241 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 141842 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 303.284612 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 179.855968 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 325.125721 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 50699 35.74% 35.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 38599 27.21% 62.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 13098 9.23% 72.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 8031 5.66% 77.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 5875 4.14% 81.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3794 2.67% 84.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3041 2.14% 86.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2492 1.76% 88.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 16213 11.43% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 141842 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17249 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 22.009624 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 229.029888 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 17238 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 7 0.04% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 3 0.02% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::28672-29695 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17252 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17252 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.956701 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.885973 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.749936 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 17057 98.87% 98.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 150 0.87% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 24 0.14% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 7 0.04% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 1 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 17249 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17249 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.959302 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.888033 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.754923 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 17045 98.82% 98.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 155 0.90% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 27 0.16% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 7 0.04% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 2 0.01% 99.92% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::36-39 1 0.01% 99.93% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::40-43 2 0.01% 99.94% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::44-47 2 0.01% 99.95% # Writes before turning the bus around for reads @@ -230,13 +230,13 @@ system.physmem.wrPerTurnAround::100-103 1 0.01% 99.98% # Wr system.physmem.wrPerTurnAround::120-123 1 0.01% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::208-211 1 0.01% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::216-219 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17252 # Writes before turning the bus around for reads -system.physmem.totQLat 4021715750 # Total ticks spent queuing -system.physmem.totMemAccLat 11140472000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1898335000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10592.75 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 17249 # Writes before turning the bus around for reads +system.physmem.totQLat 4014686000 # Total ticks spent queuing +system.physmem.totMemAccLat 11133423500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1898330000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10574.26 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29342.75 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 29324.26 # Average memory access latency per DRAM burst system.physmem.avgRdBW 59.37 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 45.74 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 59.42 # Average system read bandwidth in MiByte/s @@ -246,64 +246,64 @@ system.physmem.busUtil 0.82 # Da system.physmem.busUtilRead 0.46 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.36 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 20.32 # Average write queue length when enqueuing -system.physmem.readRowHits 314877 # Number of row buffer hits during reads -system.physmem.writeRowHits 215374 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.94 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.62 # Row buffer hit rate for writes -system.physmem.avgGap 608566.39 # Average gap between requests -system.physmem.pageHitRate 78.88 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 274823723500 # Time in different power states -system.physmem.memoryStateTime::REF 13667420000 # Time in different power states +system.physmem.avgWrQLen 20.36 # Average write queue length when enqueuing +system.physmem.readRowHits 314933 # Number of row buffer hits during reads +system.physmem.writeRowHits 215412 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.95 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.63 # Row buffer hit rate for writes +system.physmem.avgGap 608546.97 # Average gap between requests +system.physmem.pageHitRate 78.89 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 275084055500 # Time in different power states +system.physmem.memoryStateTime::REF 13666900000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 120808954500 # Time in different power states +system.physmem.memoryStateTime::ACT 120533549500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 105165169 # Throughput (bytes/s) +system.membus.throughput 105168526 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 173388 # Transaction distribution system.membus.trans_dist::ReadResp 173388 # Transaction distribution -system.membus.trans_dist::Writeback 292564 # Transaction distribution -system.membus.trans_dist::ReadExReq 206622 # Transaction distribution -system.membus.trans_dist::ReadExResp 206622 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1052584 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1052584 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43044736 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 43044736 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 43044736 # Total data (bytes) +system.membus.trans_dist::Writeback 292559 # Transaction distribution +system.membus.trans_dist::ReadExReq 206621 # Transaction distribution +system.membus.trans_dist::ReadExResp 206621 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1052577 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1052577 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43044352 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 43044352 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 43044352 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 3204326000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 3204296000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 3607344750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3607299000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.9 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 123709142 # Number of BP lookups -system.cpu.branchPred.condPredicted 87625206 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6390886 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 71443290 # Number of BTB lookups -system.cpu.branchPred.BTBHits 67227338 # Number of BTB hits +system.cpu.branchPred.lookups 123707695 # Number of BP lookups +system.cpu.branchPred.condPredicted 87624621 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6388553 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 71411167 # Number of BTB lookups +system.cpu.branchPred.BTBHits 67224113 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 94.098883 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 14930671 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1120494 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 94.136696 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 14930801 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1120545 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 149298589 # DTB read hits -system.cpu.dtb.read_misses 537604 # DTB read misses +system.cpu.dtb.read_hits 149298209 # DTB read hits +system.cpu.dtb.read_misses 537277 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 149836193 # DTB read accesses -system.cpu.dtb.write_hits 57313863 # DTB write hits -system.cpu.dtb.write_misses 67044 # DTB write misses +system.cpu.dtb.read_accesses 149835486 # DTB read accesses +system.cpu.dtb.write_hits 57314081 # DTB write hits +system.cpu.dtb.write_misses 66749 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 57380907 # DTB write accesses -system.cpu.dtb.data_hits 206612452 # DTB hits -system.cpu.dtb.data_misses 604648 # DTB misses +system.cpu.dtb.write_accesses 57380830 # DTB write accesses +system.cpu.dtb.data_hits 206612290 # DTB hits +system.cpu.dtb.data_misses 604026 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 207217100 # DTB accesses -system.cpu.itb.fetch_hits 225745608 # ITB hits +system.cpu.dtb.data_accesses 207216316 # DTB accesses +system.cpu.itb.fetch_hits 225738536 # ITB hits system.cpu.itb.fetch_misses 48 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 225745656 # ITB accesses +system.cpu.itb.fetch_accesses 225738584 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -317,71 +317,71 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 485 # Number of system calls -system.cpu.numCycles 818612023 # number of cpu cycles simulated +system.cpu.numCycles 818578593 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 611901617 # Number of instructions committed system.cpu.committedOps 611901617 # Number of ops (including micro ops) committed -system.cpu.discardedOps 13147093 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 13144034 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.337816 # CPI: cycles per instruction -system.cpu.ipc 0.747487 # IPC: instructions per cycle -system.cpu.tickCycles 736852058 # Number of cycles that the object actually ticked -system.cpu.idleCycles 81759965 # Total number of cycles that the object has spent stopped -system.cpu.icache.tags.replacements 3162 # number of replacements -system.cpu.icache.tags.tagsinuse 1116.165991 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 225740617 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 4991 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 45229.536566 # Average number of references to valid blocks. +system.cpu.cpi 1.337762 # CPI: cycles per instruction +system.cpu.ipc 0.747517 # IPC: instructions per cycle +system.cpu.tickCycles 736835501 # Number of cycles that the object actually ticked +system.cpu.idleCycles 81743092 # Total number of cycles that the object has spent stopped +system.cpu.icache.tags.replacements 3168 # number of replacements +system.cpu.icache.tags.tagsinuse 1116.143798 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 225733539 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 4997 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 45173.812087 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1116.165991 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.545003 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.545003 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1116.143798 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.544992 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.544992 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1829 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 72 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 77 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 70 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 77 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1589 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 76 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1590 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.893066 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 451496207 # Number of tag accesses -system.cpu.icache.tags.data_accesses 451496207 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 225740617 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 225740617 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 225740617 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 225740617 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 225740617 # number of overall hits -system.cpu.icache.overall_hits::total 225740617 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 4991 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 4991 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 4991 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 4991 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 4991 # number of overall misses -system.cpu.icache.overall_misses::total 4991 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 227498000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 227498000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 227498000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 227498000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 227498000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 227498000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 225745608 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 225745608 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 225745608 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 225745608 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 225745608 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 225745608 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 451482069 # Number of tag accesses +system.cpu.icache.tags.data_accesses 451482069 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 225733539 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 225733539 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 225733539 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 225733539 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 225733539 # number of overall hits +system.cpu.icache.overall_hits::total 225733539 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 4997 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 4997 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 4997 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 4997 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 4997 # number of overall misses +system.cpu.icache.overall_misses::total 4997 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 227649750 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 227649750 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 227649750 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 227649750 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 227649750 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 227649750 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 225738536 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 225738536 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 225738536 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 225738536 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 225738536 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 225738536 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000022 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 45581.646965 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 45581.646965 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 45581.646965 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 45581.646965 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 45581.646965 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 45581.646965 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 45557.284371 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 45557.284371 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 45557.284371 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 45557.284371 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 45557.284371 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 45557.284371 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -390,123 +390,123 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4991 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 4991 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 4991 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 4991 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 4991 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 4991 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 216413000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 216413000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 216413000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 216413000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 216413000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 216413000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4997 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 4997 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 4997 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 4997 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 4997 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 4997 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 216557250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 216557250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 216557250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 216557250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 216557250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 216557250 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000022 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000022 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 43360.649169 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 43360.649169 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 43360.649169 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 43360.649169 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 43360.649169 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 43360.649169 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 43337.452471 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 43337.452471 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 43337.452471 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 43337.452471 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 43337.452471 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 43337.452471 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 763750366 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 1766329 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1766329 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2340010 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 778155 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 778155 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9982 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7418996 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7428978 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 319424 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312288192 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 312607616 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 312607616 # Total data (bytes) +system.cpu.toL2Bus.throughput 763790001 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 1766353 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1766353 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2340032 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 778163 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 778163 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9994 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7419070 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7429064 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 319808 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312291264 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 312611072 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 312611072 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 4782257000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 4782306000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 8038000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 8044750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3891565250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3891617250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) -system.cpu.l2cache.tags.replacements 347300 # number of replacements -system.cpu.l2cache.tags.tagsinuse 29490.485605 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3710989 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 379724 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 9.772859 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 347298 # number of replacements +system.cpu.l2cache.tags.tagsinuse 29490.431668 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3711042 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 379722 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 9.773050 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 188606170000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 21413.748537 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 8076.737069 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.653496 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.246482 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.899978 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 21413.910714 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 8076.520954 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.653501 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.246476 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.899977 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32424 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 133 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 65 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 226 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13172 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 18828 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 137 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 61 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 224 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13170 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 18832 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.989502 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 40233831 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 40233831 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 1592941 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1592941 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 2340010 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 2340010 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.inst 571533 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 571533 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 2164474 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2164474 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 2164474 # number of overall hits -system.cpu.l2cache.overall_hits::total 2164474 # number of overall hits +system.cpu.l2cache.tags.tag_accesses 40234269 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 40234269 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 1592965 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1592965 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 2340032 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 2340032 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.inst 571542 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 571542 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 2164507 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2164507 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 2164507 # number of overall hits +system.cpu.l2cache.overall_hits::total 2164507 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 173388 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 173388 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.inst 206622 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 206622 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 380010 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 380010 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 380010 # number of overall misses -system.cpu.l2cache.overall_misses::total 380010 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 12655083750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 12655083750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 14728692500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 14728692500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 27383776250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 27383776250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 27383776250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 27383776250 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1766329 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1766329 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 2340010 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 2340010 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 778155 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 778155 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 2544484 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2544484 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 2544484 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2544484 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.098163 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.098163 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.265528 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.265528 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.149347 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.149347 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.149347 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.149347 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72987.079556 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 72987.079556 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 71283.273320 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71283.273320 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72060.672745 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 72060.672745 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72060.672745 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 72060.672745 # average overall miss latency +system.cpu.l2cache.ReadExReq_misses::cpu.inst 206621 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 206621 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 380009 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 380009 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 380009 # number of overall misses +system.cpu.l2cache.overall_misses::total 380009 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 12653023000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 12653023000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 14723654500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 14723654500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 27376677500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 27376677500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 27376677500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 27376677500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 1766353 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1766353 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 2340032 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 2340032 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.inst 778163 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 778163 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 2544516 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2544516 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 2544516 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2544516 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.098162 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.098162 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.265524 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.265524 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.149344 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.149344 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.149344 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.149344 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72975.194362 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 72975.194362 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 71259.235508 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71259.235508 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72042.181896 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 72042.181896 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72042.181896 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 72042.181896 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -515,106 +515,106 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 292564 # number of writebacks -system.cpu.l2cache.writebacks::total 292564 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 292559 # number of writebacks +system.cpu.l2cache.writebacks::total 292559 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 173388 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 173388 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 206622 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 206622 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 380010 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 380010 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 380010 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 380010 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10443247750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 10443247750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 12110276500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12110276500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22553524250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 22553524250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22553524250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 22553524250 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.098163 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.098163 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.265528 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.265528 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.149347 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.149347 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.149347 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.149347 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60230.510474 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60230.510474 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 58610.779588 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58610.779588 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59349.817768 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59349.817768 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59349.817768 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59349.817768 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 206621 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 206621 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 380009 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 380009 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 380009 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 380009 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10441221500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 10441221500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 12105242000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12105242000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22546463500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 22546463500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22546463500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 22546463500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.098162 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.098162 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.265524 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.265524 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.149344 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.149344 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.149344 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.149344 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60218.824255 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60218.824255 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 58586.697383 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58586.697383 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59331.393467 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59331.393467 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59331.393467 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59331.393467 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 2535397 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.756934 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 202541489 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2539493 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 79.756664 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 2535423 # number of replacements +system.cpu.dcache.tags.tagsinuse 4087.756597 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 202541016 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2539519 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 79.755661 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 1608245250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 4087.756934 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.997988 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997988 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.inst 4087.756597 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.997987 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997987 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 70 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 69 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 829 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 3145 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 414526387 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 414526387 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 146875295 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 146875295 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 55666194 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 55666194 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.inst 202541489 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 202541489 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 202541489 # number of overall hits -system.cpu.dcache.overall_hits::total 202541489 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 1908118 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1908118 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 1543840 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1543840 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.inst 3451958 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3451958 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 3451958 # number of overall misses -system.cpu.dcache.overall_misses::total 3451958 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 36372214750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 36372214750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 45066771500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 45066771500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 81438986250 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 81438986250 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 81438986250 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 81438986250 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 148783413 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 148783413 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 414525597 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 414525597 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 146874833 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 146874833 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.inst 55666183 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 55666183 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.inst 202541016 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 202541016 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.inst 202541016 # number of overall hits +system.cpu.dcache.overall_hits::total 202541016 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.inst 1908172 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1908172 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.inst 1543851 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1543851 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.inst 3452023 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3452023 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.inst 3452023 # number of overall misses +system.cpu.dcache.overall_misses::total 3452023 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 36370896250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 36370896250 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 45057234500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 45057234500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 81428130750 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 81428130750 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 81428130750 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 81428130750 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.inst 148783005 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 148783005 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.inst 57210034 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 57210034 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 205993447 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 205993447 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 205993447 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 205993447 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.inst 205993039 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 205993039 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 205993039 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 205993039 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.012825 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.012825 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.026985 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.026985 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.026986 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.026986 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.inst 0.016758 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.016758 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.inst 0.016758 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.016758 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 19061.826758 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 19061.826758 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 29191.348521 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 29191.348521 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 23592.113881 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 23592.113881 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 23592.113881 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 23592.113881 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 19060.596346 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 19060.596346 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 29184.963121 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 29184.963121 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 23588.524975 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23588.524975 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 23588.524975 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 23588.524975 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -623,32 +623,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2340010 # number of writebacks -system.cpu.dcache.writebacks::total 2340010 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 143436 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 143436 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 769029 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 769029 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 912465 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 912465 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 912465 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 912465 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 1764682 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1764682 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 774811 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 774811 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.inst 2539493 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2539493 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.inst 2539493 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2539493 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 30204720750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 30204720750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 21179013000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 21179013000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 51383733750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 51383733750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 51383733750 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 51383733750 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 2340032 # number of writebacks +system.cpu.dcache.writebacks::total 2340032 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 143471 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 143471 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 769033 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 769033 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.inst 912504 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 912504 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.inst 912504 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 912504 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 1764701 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1764701 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 774818 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 774818 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.inst 2539519 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2539519 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.inst 2539519 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2539519 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 30202797250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 30202797250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 21174067000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 21174067000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 51376864250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 51376864250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 51376864250 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 51376864250 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.011861 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.011861 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.013543 # mshr miss rate for WriteReq accesses @@ -657,14 +657,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.012328 system.cpu.dcache.demand_mshr_miss_rate::total 0.012328 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.012328 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.012328 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 17116.240065 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17116.240065 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 27334.424782 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27334.424782 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 20233.855242 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20233.855242 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 20233.855242 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20233.855242 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 17114.965793 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17114.965793 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 27327.794398 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27327.794398 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 20230.943045 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20230.943045 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 20230.943045 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20230.943045 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt index 8bc6ffa49..63d0e7cc1 100644 --- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt @@ -1,594 +1,101 @@ ---------- Begin Simulation Statistics ---------- -final_tick 377848323500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -host_inst_rate 209721 # Simulator instruction rate (inst/s) -host_mem_usage 298084 # Number of bytes of host memory used -host_op_rate 236376 # Simulator op (including micro ops) rate (op/s) -host_seconds 2415.51 # Real time elapsed on the host -host_tick_rate 156426000 # Simulator tick rate (ticks/s) +sim_seconds 0.361826 # Number of seconds simulated +sim_ticks 361826015500 # Number of ticks simulated +final_tick 361826015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 231274 # Simulator instruction rate (inst/s) +host_op_rate 250500 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 165186980 # Simulator tick rate (ticks/s) +host_mem_usage 321304 # Number of bytes of host memory used +host_seconds 2190.40 # Real time elapsed on the host sim_insts 506582155 # Number of instructions simulated -sim_ops 570968717 # Number of ops (including micro ops) simulated -sim_seconds 0.377848 # Number of seconds simulated -sim_ticks 377848323500 # Number of ticks simulated +sim_ops 548695378 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 88.099044 # BTB Hit Percentage -system.cpu.branchPred.BTBHits 66115419 # Number of BTB hits -system.cpu.branchPred.BTBLookups 75046693 # Number of BTB lookups -system.cpu.branchPred.RASInCorrect 20332 # Number of incorrect RAS predictions. -system.cpu.branchPred.condIncorrect 6724593 # Number of conditional branches incorrect -system.cpu.branchPred.condPredicted 104577278 # Number of conditional branches predicted -system.cpu.branchPred.lookups 137186083 # Number of BP lookups -system.cpu.branchPred.usedRAS 8950727 # Number of times the RAS was used to get a target. -system.cpu.committedInsts 506582155 # Number of instructions committed -system.cpu.committedOps 570968717 # Number of ops (including micro ops) committed -system.cpu.cpi 1.491755 # CPI: cycles per instruction -system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 1488541 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_hits::cpu.inst 1488541 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits -system.cpu.dcache.ReadReq_accesses::cpu.inst 123498792 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 123498792 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 16388.035885 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16388.035885 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 14278.902943 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14278.902943 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits::cpu.inst 122622654 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 122622654 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 14358180984 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 14358180984 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.007094 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.007094 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses::cpu.inst 876138 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 876138 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 88069 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 88069 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 11252760763 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 11252760763 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.006381 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006381 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 788069 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 788069 # number of ReadReq MSHR misses -system.cpu.dcache.StoreCondReq_accesses::cpu.inst 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_hits::cpu.inst 1488541 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.WriteReq_accesses::cpu.inst 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 29400.581233 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 29400.581233 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 28261.554772 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28261.554772 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits::cpu.inst 53538382 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 53538382 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 20607573000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 20607573000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.012923 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.012923 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses::cpu.inst 700924 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 700924 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 344621 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 344621 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 10069676750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10069676750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.006569 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006569 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 356303 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 356303 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses::cpu.inst 177738098 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 177738098 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 22171.451715 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22171.451715 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 18632.435531 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 18632.435531 # average overall mshr miss latency -system.cpu.dcache.demand_hits::cpu.inst 176161036 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 176161036 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency::cpu.inst 34965753984 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 34965753984 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate::cpu.inst 0.008873 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.008873 # miss rate for demand accesses -system.cpu.dcache.demand_misses::cpu.inst 1577062 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1577062 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits::cpu.inst 432690 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 432690 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 21322437513 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 21322437513 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.006439 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006439 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses::cpu.inst 1144372 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1144372 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses::cpu.inst 177738098 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 177738098 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 22171.451715 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22171.451715 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 18632.435531 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 18632.435531 # average overall mshr miss latency -system.cpu.dcache.overall_hits::cpu.inst 176161036 # number of overall hits -system.cpu.dcache.overall_hits::total 176161036 # number of overall hits -system.cpu.dcache.overall_miss_latency::cpu.inst 34965753984 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 34965753984 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate::cpu.inst 0.008873 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.008873 # miss rate for overall accesses -system.cpu.dcache.overall_misses::cpu.inst 1577062 # number of overall misses -system.cpu.dcache.overall_misses::total 1577062 # number of overall misses -system.cpu.dcache.overall_mshr_hits::cpu.inst 432690 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 432690 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 21322437513 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 21322437513 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.006439 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006439 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses::cpu.inst 1144372 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1144372 # number of overall MSHR misses -system.cpu.dcache.tags.age_task_id_blocks_1024::0 29 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 541 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3508 # Occupied blocks per task id -system.cpu.dcache.tags.avg_refs 156.538362 # Average number of references to valid blocks. -system.cpu.dcache.tags.data_accesses 362574732 # Number of data accesses -system.cpu.dcache.tags.occ_blocks::cpu.inst 4071.496497 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.994018 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.994018 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.replacements 1140276 # number of replacements -system.cpu.dcache.tags.sampled_refs 1144372 # Sample count of references to valid blocks. -system.cpu.dcache.tags.tag_accesses 362574732 # Number of tag accesses -system.cpu.dcache.tags.tagsinuse 4071.496497 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 179138118 # Total number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 4941909250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks::writebacks 1068741 # number of writebacks -system.cpu.dcache.writebacks::total 1068741 # number of writebacks -system.cpu.discardedOps 18127434 # Number of ops (including micro ops) which were discarded before commit -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.icache.ReadReq_accesses::cpu.inst 204480200 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 204480200 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23608.753898 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 23608.753898 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21540.715773 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21540.715773 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits::cpu.inst 204459741 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 204459741 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency::cpu.inst 483011496 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 483011496 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000100 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000100 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses::cpu.inst 20459 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 20459 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 440701504 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 440701504 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000100 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000100 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 20459 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 20459 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses::cpu.inst 204480200 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 204480200 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency::cpu.inst 23608.753898 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 23608.753898 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21540.715773 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 21540.715773 # average overall mshr miss latency -system.cpu.icache.demand_hits::cpu.inst 204459741 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 204459741 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency::cpu.inst 483011496 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 483011496 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate::cpu.inst 0.000100 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000100 # miss rate for demand accesses -system.cpu.icache.demand_misses::cpu.inst 20459 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 20459 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 440701504 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 440701504 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000100 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000100 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses::cpu.inst 20459 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 20459 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses::cpu.inst 204480200 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 204480200 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency::cpu.inst 23608.753898 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 23608.753898 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21540.715773 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 21540.715773 # average overall mshr miss latency -system.cpu.icache.overall_hits::cpu.inst 204459741 # number of overall hits -system.cpu.icache.overall_hits::total 204459741 # number of overall hits -system.cpu.icache.overall_miss_latency::cpu.inst 483011496 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 483011496 # number of overall miss cycles -system.cpu.icache.overall_miss_rate::cpu.inst 0.000100 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000100 # miss rate for overall accesses -system.cpu.icache.overall_misses::cpu.inst 20459 # number of overall misses -system.cpu.icache.overall_misses::total 20459 # number of overall misses -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 440701504 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 440701504 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000100 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000100 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses::cpu.inst 20459 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 20459 # number of overall MSHR misses -system.cpu.icache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 68 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 55 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 315 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1399 # Occupied blocks per task id -system.cpu.icache.tags.avg_refs 9993.633169 # Average number of references to valid blocks. -system.cpu.icache.tags.data_accesses 408980859 # Number of data accesses -system.cpu.icache.tags.occ_blocks::cpu.inst 1204.301311 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.588038 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.588038 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1881 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.918457 # Percentage of cache occupancy per task id -system.cpu.icache.tags.replacements 18578 # number of replacements -system.cpu.icache.tags.sampled_refs 20459 # Sample count of references to valid blocks. -system.cpu.icache.tags.tag_accesses 408980859 # Number of tag accesses -system.cpu.icache.tags.tagsinuse 1204.301311 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 204459741 # Total number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.idleCycles 36857312 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.ipc 0.670351 # IPC: instructions per cycle -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 356556 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 356556 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 70944.376455 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70944.376455 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 58283.052569 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58283.052569 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits::cpu.inst 255641 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 255641 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 7159351750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 7159351750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.283027 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.283027 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses::cpu.inst 100915 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 100915 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 5881634250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5881634250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.283027 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.283027 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 100915 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 100915 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses::cpu.inst 808275 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 808275 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74397.741148 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 74397.741148 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61739.381683 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61739.381683 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits::cpu.inst 764868 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 764868 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 3229382750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 3229382750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.053703 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.053703 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses::cpu.inst 43407 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 43407 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 15 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 15 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 2678995250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2678995250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.053685 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.053685 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 43392 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 43392 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses::writebacks 1068741 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1068741 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits::writebacks 1068741 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1068741 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses::cpu.inst 1164831 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1164831 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71983.027536 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 71983.027536 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59322.344030 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59322.344030 # average overall mshr miss latency -system.cpu.l2cache.demand_hits::cpu.inst 1020509 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1020509 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency::cpu.inst 10388734500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 10388734500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.123900 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.123900 # miss rate for demand accesses -system.cpu.l2cache.demand_misses::cpu.inst 144322 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 144322 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits::cpu.inst 15 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 15 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8560629500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 8560629500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.123887 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.123887 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 144307 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 144307 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses::cpu.inst 1164831 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1164831 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71983.027536 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 71983.027536 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59322.344030 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59322.344030 # average overall mshr miss latency -system.cpu.l2cache.overall_hits::cpu.inst 1020509 # number of overall hits -system.cpu.l2cache.overall_hits::total 1020509 # number of overall hits -system.cpu.l2cache.overall_miss_latency::cpu.inst 10388734500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 10388734500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.123900 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.123900 # miss rate for overall accesses -system.cpu.l2cache.overall_misses::cpu.inst 144322 # number of overall misses -system.cpu.l2cache.overall_misses::total 144322 # number of overall misses -system.cpu.l2cache.overall_mshr_hits::cpu.inst 15 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 15 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8560629500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 8560629500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.123887 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.123887 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 144307 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 144307 # number of overall MSHR misses -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 321 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4944 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 25858 # Occupied blocks per task id -system.cpu.l2cache.tags.avg_refs 11.811039 # Average number of references to valid blocks. -system.cpu.l2cache.tags.data_accesses 18367876 # Number of data accesses -system.cpu.l2cache.tags.occ_blocks::writebacks 23534.473696 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 4154.581244 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.718215 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.126788 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.845003 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 31193 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.951935 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.replacements 111551 # number of replacements -system.cpu.l2cache.tags.sampled_refs 142744 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.tag_accesses 18367876 # Number of tag accesses -system.cpu.l2cache.tags.tagsinuse 27689.054939 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1685955 # Total number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 168523988500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks::writebacks 96655 # number of writebacks -system.cpu.l2cache.writebacks::total 96655 # number of writebacks -system.cpu.numCycles 755696647 # number of cpu cycles simulated -system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.tickCycles 718839335 # Number of cycles that the CPU actually ticked -system.cpu.toL2Bus.data_through_bus 142948608 # Total data (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40918 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3357485 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3398403 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 2185527000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 31384496 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1745291987 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.throughput 378322727 # Throughput (bytes/s) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1309376 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141639232 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 142948608 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.trans_dist::ReadReq 808275 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 808275 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1068741 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 356556 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 356556 # Transaction distribution -system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.membus.data_through_bus 15421568 # Total data (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 385269 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 385269 # Packet count per connected master and slave (bytes) -system.membus.reqLayer0.occupancy 1076098500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 1364495500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.4 # Layer utilization (%) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.throughput 40814176 # Throughput (bytes/s) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15421568 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 15421568 # Cumulative packet size per connected master and slave (bytes) -system.membus.trans_dist::ReadReq 43392 # Transaction distribution -system.membus.trans_dist::ReadResp 43392 # Transaction distribution -system.membus.trans_dist::Writeback 96655 # Transaction distribution -system.membus.trans_dist::ReadExReq 100915 # Transaction distribution -system.membus.trans_dist::ReadExResp 100915 # Transaction distribution -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgGap 1568082.50 # Average gap between requests -system.physmem.avgMemAccLat 29316.89 # Average memory access latency per DRAM burst -system.physmem.avgQLat 10566.89 # Average queueing delay per DRAM burst -system.physmem.avgRdBW 24.43 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgRdBWSys 24.44 # Average system read bandwidth in MiByte/s -system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing -system.physmem.avgWrBW 16.37 # Average achieved write bandwidth in MiByte/s -system.physmem.avgWrBWSys 16.37 # Average system write bandwidth in MiByte/s -system.physmem.avgWrQLen 19.41 # Average write queue length when enqueuing -system.physmem.busUtil 0.32 # Data bus utilization in percentage -system.physmem.busUtilRead 0.19 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.13 # Data bus utilization in percentage for writes -system.physmem.bw_inst_read::cpu.inst 599436 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 599436 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 24442739 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 24442739 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 16371437 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 24442739 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 40814176 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_write::writebacks 16371437 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 16371437 # Write bandwidth from this memory (bytes/s) -system.physmem.bytesPerActivate::samples 65344 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 235.879530 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 156.532408 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 241.691059 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 24749 37.87% 37.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18254 27.94% 65.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 7150 10.94% 76.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7883 12.06% 88.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2042 3.12% 91.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1102 1.69% 93.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 756 1.16% 94.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 612 0.94% 95.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 2796 4.28% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 65344 # Bytes accessed per row activation -system.physmem.bytesReadDRAM 9229248 # Total number of bytes read from DRAM -system.physmem.bytesReadSys 9235648 # Total read bytes from the system interface side -system.physmem.bytesReadWrQ 6400 # Total number of bytes read from write queue -system.physmem.bytesWritten 6184768 # Total number of bytes written to DRAM -system.physmem.bytesWrittenSys 6185920 # Total written bytes from the system interface side -system.physmem.bytes_inst_read::cpu.inst 226496 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 226496 # Number of instructions bytes read from this memory -system.physmem.bytes_read::cpu.inst 9235648 # Number of bytes read from this memory -system.physmem.bytes_read::total 9235648 # Number of bytes read from this memory -system.physmem.bytes_written::writebacks 6185920 # Number of bytes written to this memory -system.physmem.bytes_written::total 6185920 # Number of bytes written to this memory -system.physmem.memoryStateTime::IDLE 265986637250 # Time in different power states -system.physmem.memoryStateTime::REF 12617020000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 99239970250 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.bytes_read::cpu.inst 9220736 # Number of bytes read from this memory +system.physmem.bytes_read::total 9220736 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 221440 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 221440 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6177024 # Number of bytes written to this memory +system.physmem.bytes_written::total 6177024 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 144074 # Number of read requests responded to by this memory +system.physmem.num_reads::total 144074 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 96516 # Number of write requests responded to by this memory +system.physmem.num_writes::total 96516 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 25483894 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 25483894 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 612007 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 612007 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 17071807 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 17071807 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 17071807 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 25483894 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 42555702 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 144074 # Number of read requests accepted +system.physmem.writeReqs 96516 # Number of write requests accepted +system.physmem.readBursts 144074 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 96516 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9213952 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6784 # Total number of bytes read from write queue +system.physmem.bytesWritten 6175488 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9220736 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6177024 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 106 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 9331 # Per bank write bursts +system.physmem.perBankRdBursts::1 8974 # Per bank write bursts +system.physmem.perBankRdBursts::2 8995 # Per bank write bursts +system.physmem.perBankRdBursts::3 8704 # Per bank write bursts +system.physmem.perBankRdBursts::4 9445 # Per bank write bursts +system.physmem.perBankRdBursts::5 9338 # Per bank write bursts +system.physmem.perBankRdBursts::6 8941 # Per bank write bursts +system.physmem.perBankRdBursts::7 8096 # Per bank write bursts +system.physmem.perBankRdBursts::8 8562 # Per bank write bursts +system.physmem.perBankRdBursts::9 8674 # Per bank write bursts +system.physmem.perBankRdBursts::10 8773 # Per bank write bursts +system.physmem.perBankRdBursts::11 9481 # Per bank write bursts +system.physmem.perBankRdBursts::12 9368 # Per bank write bursts +system.physmem.perBankRdBursts::13 9509 # Per bank write bursts +system.physmem.perBankRdBursts::14 8709 # Per bank write bursts +system.physmem.perBankRdBursts::15 9068 # Per bank write bursts +system.physmem.perBankWrBursts::0 6188 # Per bank write bursts +system.physmem.perBankWrBursts::1 6094 # Per bank write bursts +system.physmem.perBankWrBursts::2 6004 # Per bank write bursts +system.physmem.perBankWrBursts::3 5817 # Per bank write bursts +system.physmem.perBankWrBursts::4 6158 # Per bank write bursts +system.physmem.perBankWrBursts::5 6168 # Per bank write bursts +system.physmem.perBankWrBursts::6 6012 # Per bank write bursts +system.physmem.perBankWrBursts::7 5489 # Per bank write bursts +system.physmem.perBankWrBursts::8 5725 # Per bank write bursts +system.physmem.perBankWrBursts::9 5819 # Per bank write bursts +system.physmem.perBankWrBursts::10 5961 # Per bank write bursts +system.physmem.perBankWrBursts::11 6448 # Per bank write bursts +system.physmem.perBankWrBursts::12 6304 # Per bank write bursts +system.physmem.perBankWrBursts::13 6266 # Per bank write bursts +system.physmem.perBankWrBursts::14 5996 # Per bank write bursts +system.physmem.perBankWrBursts::15 6043 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.num_reads::cpu.inst 144307 # Number of read requests responded to by this memory -system.physmem.num_reads::total 144307 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 96655 # Number of write requests responded to by this memory -system.physmem.num_writes::total 96655 # Number of write requests responded to by this memory -system.physmem.pageHitRate 72.86 # Row buffer hit rate, read and write combined -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.perBankRdBursts::0 9328 # Per bank write bursts -system.physmem.perBankRdBursts::1 8986 # Per bank write bursts -system.physmem.perBankRdBursts::2 9010 # Per bank write bursts -system.physmem.perBankRdBursts::3 8718 # Per bank write bursts -system.physmem.perBankRdBursts::4 9475 # Per bank write bursts -system.physmem.perBankRdBursts::5 9358 # Per bank write bursts -system.physmem.perBankRdBursts::6 8951 # Per bank write bursts -system.physmem.perBankRdBursts::7 8100 # Per bank write bursts -system.physmem.perBankRdBursts::8 8572 # Per bank write bursts -system.physmem.perBankRdBursts::9 8669 # Per bank write bursts -system.physmem.perBankRdBursts::10 8784 # Per bank write bursts -system.physmem.perBankRdBursts::11 9499 # Per bank write bursts -system.physmem.perBankRdBursts::12 9376 # Per bank write bursts -system.physmem.perBankRdBursts::13 9538 # Per bank write bursts -system.physmem.perBankRdBursts::14 8741 # Per bank write bursts -system.physmem.perBankRdBursts::15 9102 # Per bank write bursts -system.physmem.perBankWrBursts::0 6202 # Per bank write bursts -system.physmem.perBankWrBursts::1 6099 # Per bank write bursts -system.physmem.perBankWrBursts::2 6021 # Per bank write bursts -system.physmem.perBankWrBursts::3 5821 # Per bank write bursts -system.physmem.perBankWrBursts::4 6172 # Per bank write bursts -system.physmem.perBankWrBursts::5 6184 # Per bank write bursts -system.physmem.perBankWrBursts::6 6018 # Per bank write bursts -system.physmem.perBankWrBursts::7 5493 # Per bank write bursts -system.physmem.perBankWrBursts::8 5732 # Per bank write bursts -system.physmem.perBankWrBursts::9 5815 # Per bank write bursts -system.physmem.perBankWrBursts::10 5965 # Per bank write bursts -system.physmem.perBankWrBursts::11 6456 # Per bank write bursts -system.physmem.perBankWrBursts::12 6307 # Per bank write bursts -system.physmem.perBankWrBursts::13 6282 # Per bank write bursts -system.physmem.perBankWrBursts::14 6014 # Per bank write bursts -system.physmem.perBankWrBursts::15 6056 # Per bank write bursts -system.physmem.rdPerTurnAround::samples 5563 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 25.922344 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 382.692234 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 5559 99.93% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 3 0.05% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5563 # Reads before turning the bus around for writes -system.physmem.rdQLenPdf::0 143841 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 346 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 20 # What read queue length does an incoming req see +system.physmem.totGap 361825986500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 144074 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 96516 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 143606 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 344 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 18 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -618,46 +125,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.readBursts 144307 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 144307 # Read request sizes (log2) -system.physmem.readReqs 144307 # Number of read requests accepted -system.physmem.readRowHitRate 76.88 # Row buffer hit rate for reads -system.physmem.readRowHits 110862 # Number of row buffer hits during reads -system.physmem.servicedByWrQ 100 # Number of DRAM read bursts serviced by the write queue -system.physmem.totBusLat 721035000 # Total ticks spent in databus transfers -system.physmem.totGap 377848294500 # Total gap between requests -system.physmem.totMemAccLat 4227701250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totQLat 1523820000 # Total ticks spent queuing -system.physmem.wrPerTurnAround::samples 5563 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.371382 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.273622 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.337365 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-17 2499 44.92% 44.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18-19 2925 52.58% 97.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-21 45 0.81% 98.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22-23 18 0.32% 98.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-25 19 0.34% 98.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26-27 16 0.29% 99.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-29 12 0.22% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30-31 7 0.13% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-33 2 0.04% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34-35 3 0.05% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-37 1 0.02% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::38-39 4 0.07% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-41 4 0.07% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::42-43 2 0.04% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::46-47 1 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-49 1 0.02% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-53 1 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::70-71 2 0.04% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-73 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5563 # Writes before turning the bus around for reads system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see @@ -673,36 +140,36 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 3052 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3240 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5530 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5663 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5670 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5657 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5657 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5655 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5664 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5671 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5684 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5707 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5632 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5620 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5645 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5589 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5570 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2930 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5541 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5647 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5676 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5658 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5671 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5685 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5655 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5675 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5648 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5690 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5726 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5661 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5642 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5632 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5590 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5576 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 6 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 5 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see @@ -722,17 +189,551 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.writeBursts 96655 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 96655 # Write request sizes (log2) -system.physmem.writeReqs 96655 # Number of write requests accepted -system.physmem.writeRowHitRate 66.87 # Row buffer hit rate for writes -system.physmem.writeRowHits 64630 # Number of row buffer hits during writes -system.voltage_domain.voltage 1 # Voltage in Volts +system.physmem.bytesPerActivate::samples 64715 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 237.790435 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 157.392081 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 243.201287 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 24444 37.77% 37.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18161 28.06% 65.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6768 10.46% 76.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7845 12.12% 88.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2212 3.42% 91.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1114 1.72% 93.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 793 1.23% 94.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 596 0.92% 95.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 2782 4.30% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 64715 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5568 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 25.855065 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 382.360630 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 5564 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 3 0.05% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 5568 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5568 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.329741 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.226111 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.490816 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-17 2624 47.13% 47.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18-19 2801 50.31% 97.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-21 48 0.86% 98.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22-23 25 0.45% 98.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-25 21 0.38% 99.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26-27 12 0.22% 99.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-29 8 0.14% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30-31 6 0.11% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-33 3 0.05% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34-35 4 0.07% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-37 1 0.02% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::38-39 5 0.09% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-41 2 0.04% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::50-51 1 0.02% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-53 1 0.02% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-57 1 0.02% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::58-59 1 0.02% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-69 2 0.04% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::70-71 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-81 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5568 # Writes before turning the bus around for reads +system.physmem.totQLat 1536727500 # Total ticks spent queuing +system.physmem.totMemAccLat 4236127500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 719840000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10674.09 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 29424.09 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 25.47 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 17.07 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 25.48 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 17.07 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 0.33 # Data bus utilization in percentage +system.physmem.busUtilRead 0.20 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.13 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing +system.physmem.avgWrQLen 19.41 # Average write queue length when enqueuing +system.physmem.readRowHits 111270 # Number of row buffer hits during reads +system.physmem.writeRowHits 64468 # Number of row buffer hits during writes +system.physmem.readRowHitRate 77.29 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 66.80 # Row buffer hit rate for writes +system.physmem.avgGap 1503911.16 # Average gap between requests +system.physmem.pageHitRate 73.08 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 254085865250 # Time in different power states +system.physmem.memoryStateTime::REF 12081940000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 95653103250 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.membus.throughput 42555702 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 43212 # Transaction distribution +system.membus.trans_dist::ReadResp 43212 # Transaction distribution +system.membus.trans_dist::Writeback 96516 # Transaction distribution +system.membus.trans_dist::ReadExReq 100862 # Transaction distribution +system.membus.trans_dist::ReadExResp 100862 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 384664 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 384664 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15397760 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 15397760 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 15397760 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 1075054000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 1362559750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.4 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.branchPred.lookups 132256489 # Number of BP lookups +system.cpu.branchPred.condPredicted 98266035 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6550672 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 68852239 # Number of BTB lookups +system.cpu.branchPred.BTBHits 64692489 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 93.958439 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 9992276 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 17882 # Number of incorrect RAS predictions. +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 548 # Number of system calls +system.cpu.numCycles 723652031 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 506582155 # Number of instructions committed +system.cpu.committedOps 548695378 # Number of ops (including micro ops) committed +system.cpu.discardedOps 14122871 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching +system.cpu.cpi 1.428499 # CPI: cycles per instruction +system.cpu.ipc 0.700036 # IPC: instructions per cycle +system.cpu.tickCycles 687771211 # Number of cycles that the object actually ticked +system.cpu.idleCycles 35880820 # Total number of cycles that the object has spent stopped +system.cpu.icache.tags.replacements 17660 # number of replacements +system.cpu.icache.tags.tagsinuse 1187.686040 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 200323378 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 19531 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 10256.688239 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1187.686040 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.579925 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.579925 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1871 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 63 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 61 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 302 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1404 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.913574 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 400705349 # Number of tag accesses +system.cpu.icache.tags.data_accesses 400705349 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 200323378 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 200323378 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 200323378 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 200323378 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 200323378 # number of overall hits +system.cpu.icache.overall_hits::total 200323378 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 19531 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 19531 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 19531 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 19531 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 19531 # number of overall misses +system.cpu.icache.overall_misses::total 19531 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 466485747 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 466485747 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 466485747 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 466485747 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 466485747 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 466485747 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 200342909 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 200342909 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 200342909 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 200342909 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 200342909 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 200342909 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000097 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000097 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000097 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000097 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000097 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000097 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23884.375966 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 23884.375966 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 23884.375966 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 23884.375966 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 23884.375966 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 23884.375966 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 19531 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 19531 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 19531 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 19531 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 19531 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 19531 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 426041253 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 426041253 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 426041253 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 426041253 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 426041253 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 426041253 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000097 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000097 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000097 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000097 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000097 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000097 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21813.591368 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21813.591368 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21813.591368 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 21813.591368 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21813.591368 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 21813.591368 # average overall mshr miss latency +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 394741942 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 806872 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 806872 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1068421 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 356393 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 356393 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 39062 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3355889 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 3394951 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1249984 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141577920 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 142827904 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 142827904 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 2184264000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 29987747 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 1744465986 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) +system.cpu.l2cache.tags.replacements 111319 # number of replacements +system.cpu.l2cache.tags.tagsinuse 27632.304905 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1684536 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 142508 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 11.820642 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 162493519500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 23524.678269 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 4107.626636 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.717916 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.125355 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.843271 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 31189 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 325 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4925 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 25872 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.951813 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 18352389 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 18352389 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 763644 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 763644 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1068421 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1068421 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.inst 255531 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 255531 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 1019175 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1019175 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 1019175 # number of overall hits +system.cpu.l2cache.overall_hits::total 1019175 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 43228 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 43228 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.inst 100862 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 100862 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 144090 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 144090 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 144090 # number of overall misses +system.cpu.l2cache.overall_misses::total 144090 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 3220977500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 3220977500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 7166346750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 7166346750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 10387324250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 10387324250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 10387324250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 10387324250 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 806872 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 806872 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 1068421 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1068421 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.inst 356393 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 356393 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1163265 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1163265 # 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average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 74511.369945 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 71051.007813 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71051.007813 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72089.140468 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 72089.140468 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72089.140468 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 72089.140468 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # 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Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 550 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3501 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 342864800 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 342864800 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 112789835 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 112789835 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.inst 53538720 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 53538720 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.inst 1488541 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.inst 1488541 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.inst 166328555 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 166328555 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.inst 166328555 # number of overall hits +system.cpu.dcache.overall_hits::total 166328555 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.inst 854310 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 854310 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.inst 700586 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 700586 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.inst 1554896 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1554896 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.inst 1554896 # number of overall misses +system.cpu.dcache.overall_misses::total 1554896 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 13696134233 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 13696134233 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 20619900500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 20619900500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 34316034733 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 34316034733 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 34316034733 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 34316034733 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.inst 113644145 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 113644145 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.inst 54239306 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 1488541 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.inst 1488541 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.inst 167883451 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 167883451 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 167883451 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 167883451 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.007517 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.007517 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.012917 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.012917 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.inst 0.009262 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009262 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.inst 0.009262 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009262 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 16031.808399 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16031.808399 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 29432.361623 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 29432.361623 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 22069.665581 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22069.665581 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 22069.665581 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22069.665581 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 1068421 # number of writebacks +system.cpu.dcache.writebacks::total 1068421 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 66718 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 66718 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 344444 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 344444 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.inst 411162 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 411162 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.inst 411162 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 411162 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 787592 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 787592 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 356142 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 356142 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.inst 1143734 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1143734 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.inst 1143734 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1143734 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 11245323264 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 11245323264 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 10075452250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10075452250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 21320775514 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 21320775514 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 21320775514 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 21320775514 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.006930 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006930 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.006566 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006566 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.006813 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006813 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.006813 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006813 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 14278.107528 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14278.107528 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 28290.547731 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28290.547731 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 18641.375979 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 18641.375979 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 18641.375979 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 18641.375979 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index 522c4ee18..5c43314b3 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,108 +1,108 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.201640 # Number of seconds simulated -sim_ticks 201639641000 # Number of ticks simulated -final_tick 201639641000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.195021 # Number of seconds simulated +sim_ticks 195020773000 # Number of ticks simulated +final_tick 195020773000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 135689 # Simulator instruction rate (inst/s) -host_op_rate 152980 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 54153116 # Simulator tick rate (ticks/s) -host_mem_usage 265540 # Number of bytes of host memory used -host_seconds 3723.51 # Real time elapsed on the host +host_inst_rate 105873 # Simulator instruction rate (inst/s) +host_op_rate 114698 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 40866801 # Simulator tick rate (ticks/s) +host_mem_usage 257276 # Number of bytes of host memory used +host_seconds 4772.11 # Real time elapsed on the host sim_insts 505237723 # Number of instructions simulated -sim_ops 569624283 # Number of ops (including micro ops) simulated +sim_ops 547350944 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 217344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9271296 # Number of bytes read from this memory -system.physmem.bytes_read::total 9488640 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 217344 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 217344 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6252864 # Number of bytes written to this memory -system.physmem.bytes_written::total 6252864 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3396 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 144864 # Number of read requests responded to by this memory -system.physmem.num_reads::total 148260 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 97701 # Number of write requests responded to by this memory -system.physmem.num_writes::total 97701 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1077883 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 45979530 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 47057414 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1077883 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1077883 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 31010093 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 31010093 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 31010093 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1077883 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 45979530 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 78067507 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 148261 # Number of read requests accepted -system.physmem.writeReqs 97701 # Number of write requests accepted -system.physmem.readBursts 148261 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 97701 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9478784 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9920 # Total number of bytes read from write queue -system.physmem.bytesWritten 6251328 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9488704 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6252864 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 155 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 207936 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9274560 # Number of bytes read from this memory +system.physmem.bytes_read::total 9482496 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 207936 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 207936 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6243584 # Number of bytes written to this memory +system.physmem.bytes_written::total 6243584 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3249 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 144915 # Number of read requests responded to by this memory +system.physmem.num_reads::total 148164 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 97556 # Number of write requests responded to by this memory +system.physmem.num_writes::total 97556 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 1066225 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 47556780 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 48623005 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1066225 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1066225 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 32014969 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 32014969 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 32014969 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1066225 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 47556780 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 80637974 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 148164 # Number of read requests accepted +system.physmem.writeReqs 97556 # Number of write requests accepted +system.physmem.readBursts 148164 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 97556 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9474176 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8320 # Total number of bytes read from write queue +system.physmem.bytesWritten 6241856 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9482496 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6243584 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 130 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 8 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9600 # Per bank write bursts -system.physmem.perBankRdBursts::1 9245 # Per bank write bursts -system.physmem.perBankRdBursts::2 9272 # Per bank write bursts -system.physmem.perBankRdBursts::3 9002 # Per bank write bursts -system.physmem.perBankRdBursts::4 9776 # Per bank write bursts -system.physmem.perBankRdBursts::5 9633 # Per bank write bursts -system.physmem.perBankRdBursts::6 9118 # Per bank write bursts -system.physmem.perBankRdBursts::7 8324 # Per bank write bursts -system.physmem.perBankRdBursts::8 8782 # Per bank write bursts -system.physmem.perBankRdBursts::9 8907 # Per bank write bursts -system.physmem.perBankRdBursts::10 8927 # Per bank write bursts -system.physmem.perBankRdBursts::11 9740 # Per bank write bursts -system.physmem.perBankRdBursts::12 9612 # Per bank write bursts -system.physmem.perBankRdBursts::13 9774 # Per bank write bursts -system.physmem.perBankRdBursts::14 8952 # Per bank write bursts -system.physmem.perBankRdBursts::15 9442 # Per bank write bursts -system.physmem.perBankWrBursts::0 6262 # Per bank write bursts -system.physmem.perBankWrBursts::1 6157 # Per bank write bursts -system.physmem.perBankWrBursts::2 6103 # Per bank write bursts -system.physmem.perBankWrBursts::3 5900 # Per bank write bursts -system.physmem.perBankWrBursts::4 6261 # Per bank write bursts -system.physmem.perBankWrBursts::5 6280 # Per bank write bursts -system.physmem.perBankWrBursts::6 6052 # Per bank write bursts -system.physmem.perBankWrBursts::7 5550 # Per bank write bursts -system.physmem.perBankWrBursts::8 5797 # Per bank write bursts -system.physmem.perBankWrBursts::9 5910 # Per bank write bursts -system.physmem.perBankWrBursts::10 5990 # Per bank write bursts -system.physmem.perBankWrBursts::11 6523 # Per bank write bursts -system.physmem.perBankWrBursts::12 6359 # Per bank write bursts -system.physmem.perBankWrBursts::13 6344 # Per bank write bursts -system.physmem.perBankWrBursts::14 6057 # Per bank write bursts -system.physmem.perBankWrBursts::15 6132 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 9 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 9585 # Per bank write bursts +system.physmem.perBankRdBursts::1 9250 # Per bank write bursts +system.physmem.perBankRdBursts::2 9223 # Per bank write bursts +system.physmem.perBankRdBursts::3 8986 # Per bank write bursts +system.physmem.perBankRdBursts::4 9777 # Per bank write bursts +system.physmem.perBankRdBursts::5 9541 # Per bank write bursts +system.physmem.perBankRdBursts::6 9063 # Per bank write bursts +system.physmem.perBankRdBursts::7 8318 # Per bank write bursts +system.physmem.perBankRdBursts::8 8791 # Per bank write bursts +system.physmem.perBankRdBursts::9 8912 # Per bank write bursts +system.physmem.perBankRdBursts::10 8928 # Per bank write bursts +system.physmem.perBankRdBursts::11 9775 # Per bank write bursts +system.physmem.perBankRdBursts::12 9650 # Per bank write bursts +system.physmem.perBankRdBursts::13 9761 # Per bank write bursts +system.physmem.perBankRdBursts::14 8979 # Per bank write bursts +system.physmem.perBankRdBursts::15 9495 # Per bank write bursts +system.physmem.perBankWrBursts::0 6258 # Per bank write bursts +system.physmem.perBankWrBursts::1 6150 # Per bank write bursts +system.physmem.perBankWrBursts::2 6073 # Per bank write bursts +system.physmem.perBankWrBursts::3 5890 # Per bank write bursts +system.physmem.perBankWrBursts::4 6255 # Per bank write bursts +system.physmem.perBankWrBursts::5 6221 # Per bank write bursts +system.physmem.perBankWrBursts::6 6024 # Per bank write bursts +system.physmem.perBankWrBursts::7 5542 # Per bank write bursts +system.physmem.perBankWrBursts::8 5802 # Per bank write bursts +system.physmem.perBankWrBursts::9 5901 # Per bank write bursts +system.physmem.perBankWrBursts::10 5976 # Per bank write bursts +system.physmem.perBankWrBursts::11 6519 # Per bank write bursts +system.physmem.perBankWrBursts::12 6371 # Per bank write bursts +system.physmem.perBankWrBursts::13 6333 # Per bank write bursts +system.physmem.perBankWrBursts::14 6062 # Per bank write bursts +system.physmem.perBankWrBursts::15 6152 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 201639615000 # Total gap between requests +system.physmem.totGap 195020664000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 148261 # Read request sizes (log2) +system.physmem.readPktSize::6 148164 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 97701 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 138302 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 9255 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 486 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 54 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 97556 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 137840 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 9554 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 574 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 60 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -144,32 +144,32 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2250 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2402 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5292 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5790 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5812 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5837 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5844 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5837 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5855 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5847 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5870 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5853 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5913 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6010 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5828 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5851 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5805 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5732 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2265 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5298 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5757 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5823 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5839 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5855 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5867 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5891 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5873 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5884 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5884 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5906 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5955 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5832 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5848 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5868 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5742 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see @@ -193,106 +193,105 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 65483 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 240.203045 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 153.557671 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 255.515687 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 26845 41.00% 41.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17105 26.12% 67.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6057 9.25% 76.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 6227 9.51% 85.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3215 4.91% 90.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1344 2.05% 92.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 866 1.32% 94.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 634 0.97% 95.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 3190 4.87% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 65483 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5723 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 25.877861 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 376.772634 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 5719 99.93% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 3 0.05% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 65254 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 240.825329 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 153.977579 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 256.120796 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 26634 40.82% 40.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17090 26.19% 67.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6012 9.21% 76.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 6427 9.85% 86.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3020 4.63% 90.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1342 2.06% 92.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 838 1.28% 94.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 692 1.06% 95.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 3199 4.90% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 65254 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5732 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 25.824669 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 376.283766 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 5727 99.91% 99.91% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 4 0.07% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5723 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5723 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.067447 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.968448 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.305335 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-17 3462 60.49% 60.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18-19 2077 36.29% 96.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-21 88 1.54% 98.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22-23 26 0.45% 98.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-25 19 0.33% 99.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26-27 9 0.16% 99.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-29 14 0.24% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30-31 5 0.09% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-33 2 0.03% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34-35 1 0.02% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-37 6 0.10% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::38-39 2 0.03% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-41 3 0.05% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-45 2 0.03% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::46-47 1 0.02% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-53 2 0.03% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::54-55 2 0.03% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-57 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-73 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5723 # Writes before turning the bus around for reads -system.physmem.totQLat 1816896000 # Total ticks spent queuing -system.physmem.totMemAccLat 4593883500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 740530000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12267.54 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5732 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5732 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.014829 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.919448 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.243342 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-17 3608 62.94% 62.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18-19 1943 33.90% 96.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-21 77 1.34% 98.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22-23 32 0.56% 98.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-25 17 0.30% 99.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26-27 19 0.33% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-29 11 0.19% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30-31 3 0.05% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-33 2 0.03% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34-35 6 0.10% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-37 2 0.03% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::38-39 3 0.05% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-41 2 0.03% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42-43 1 0.02% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-49 1 0.02% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::50-51 3 0.05% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-61 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-77 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5732 # Writes before turning the bus around for reads +system.physmem.totQLat 1847546250 # Total ticks spent queuing +system.physmem.totMemAccLat 4623183750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 740170000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12480.55 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31017.54 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 47.01 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 31.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 47.06 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 31.01 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 31230.55 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 48.58 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 32.01 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 48.62 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 32.01 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.61 # Data bus utilization in percentage -system.physmem.busUtilRead 0.37 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.24 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing -system.physmem.avgWrQLen 19.04 # Average write queue length when enqueuing -system.physmem.readRowHits 116026 # Number of row buffer hits during reads -system.physmem.writeRowHits 64266 # Number of row buffer hits during writes -system.physmem.readRowHitRate 78.34 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 65.78 # Row buffer hit rate for writes -system.physmem.avgGap 819799.87 # Average gap between requests -system.physmem.pageHitRate 73.35 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 120286035750 # Time in different power states -system.physmem.memoryStateTime::REF 6732960000 # Time in different power states +system.physmem.busUtil 0.63 # Data bus utilization in percentage +system.physmem.busUtilRead 0.38 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.25 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing +system.physmem.avgWrQLen 19.21 # Average write queue length when enqueuing +system.physmem.readRowHits 116004 # Number of row buffer hits during reads +system.physmem.writeRowHits 64298 # Number of row buffer hits during writes +system.physmem.readRowHitRate 78.36 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 65.91 # Row buffer hit rate for writes +system.physmem.avgGap 793670.29 # Average gap between requests +system.physmem.pageHitRate 73.42 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 115260013250 # Time in different power states +system.physmem.memoryStateTime::REF 6511960000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 74617456750 # Time in different power states +system.physmem.memoryStateTime::ACT 73245775250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 78067507 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 46965 # Transaction distribution -system.membus.trans_dist::ReadResp 46964 # Transaction distribution -system.membus.trans_dist::Writeback 97701 # Transaction distribution -system.membus.trans_dist::UpgradeReq 8 # Transaction distribution -system.membus.trans_dist::UpgradeResp 8 # Transaction distribution -system.membus.trans_dist::ReadExReq 101296 # Transaction distribution -system.membus.trans_dist::ReadExResp 101296 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 394238 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 394238 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15741504 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 15741504 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 15741504 # Total data (bytes) +system.membus.throughput 80637974 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 46897 # Transaction distribution +system.membus.trans_dist::ReadResp 46897 # Transaction distribution +system.membus.trans_dist::Writeback 97556 # Transaction distribution +system.membus.trans_dist::UpgradeReq 9 # Transaction distribution +system.membus.trans_dist::UpgradeResp 9 # Transaction distribution +system.membus.trans_dist::ReadExReq 101267 # Transaction distribution +system.membus.trans_dist::ReadExResp 101267 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 393902 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 393902 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15726080 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 15726080 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 15726080 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1079764000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 1396376742 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1079373000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.6 # Layer utilization (%) +system.membus.respLayer1.occupancy 1394503741 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.7 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 185905498 # Number of BP lookups -system.cpu.branchPred.condPredicted 145717903 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 7288959 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 95047377 # Number of BTB lookups -system.cpu.branchPred.BTBHits 88827374 # Number of BTB hits +system.cpu.branchPred.lookups 200189098 # Number of BP lookups +system.cpu.branchPred.condPredicted 149602484 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 7338467 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 107397070 # Number of BTB lookups +system.cpu.branchPred.BTBHits 96034676 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 93.455892 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 12842646 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 117058 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 89.420201 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 14381720 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 112950 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -378,517 +377,516 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 403279283 # number of cpu cycles simulated +system.cpu.numCycles 390041547 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 120682752 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 776131290 # Number of instructions fetch has processed -system.cpu.fetch.Branches 185905498 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 101670020 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 172998904 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 37503258 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 68039482 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 86 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 481 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 57 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 115897812 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2525334 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 391132406 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.225985 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.009732 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 129697358 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 835224616 # Number of instructions fetch has processed +system.cpu.fetch.Branches 200189098 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 110416396 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 251952283 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 16305676 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 54 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 725 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 54 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 125022986 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2819221 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 389803312 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.324321 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.986703 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 218146201 55.77% 55.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 14394493 3.68% 59.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 23167694 5.92% 65.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 22933314 5.86% 71.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 21066439 5.39% 76.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 11728153 3.00% 79.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 13552888 3.47% 83.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 12244725 3.13% 86.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 53898499 13.78% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 204497213 52.46% 52.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 16740879 4.29% 56.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 25096143 6.44% 63.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 25406235 6.52% 69.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 22255484 5.71% 75.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 19361790 4.97% 80.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 11228649 2.88% 83.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 12061789 3.09% 86.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 53155130 13.64% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 391132406 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.460984 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.924550 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 127941260 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 66012107 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 164309835 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3533487 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 29335717 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 26533351 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 77647 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 841607037 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 303900 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 29335717 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 132935936 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 7523486 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 48032128 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 162776327 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 10528812 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 816179204 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 4868 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 4457827 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 3314300 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 1212194 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 4787 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 972434380 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3587695415 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3300630013 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 432 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 666252291 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 306182089 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2293511 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2293509 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 23291983 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 173719051 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 74905434 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 30225729 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 17207987 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 768522572 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 3775769 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 668800812 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1727981 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 200793138 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 527082191 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 798137 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 391132406 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.709909 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.765965 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 389803312 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.513251 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.141373 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 103986680 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 118578898 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 144750042 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 14406980 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 8080712 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 27470111 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 74706 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 847095448 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 284101 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 8080712 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 110645607 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 38128402 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 58728570 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 152416718 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 21803303 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 812473012 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 12287 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 7169304 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 5481410 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 7159011 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 991790845 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3569028243 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 858899446 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 368 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 654123751 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 337667094 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2298389 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 3025745 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 46474458 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 165564895 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 77029612 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 33913346 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 24718127 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 764294822 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 3785962 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 654447179 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 456586 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 218477687 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 578622397 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 808330 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 389803312 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.678916 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.824028 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 138616997 35.44% 35.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 67517265 17.26% 52.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 69869307 17.86% 70.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 51755005 13.23% 83.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 32440287 8.29% 92.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 16135836 4.13% 96.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 9617335 2.46% 98.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3307412 0.85% 99.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1872962 0.48% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 146772690 37.65% 37.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 67318590 17.27% 54.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 64772838 16.62% 71.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 47064670 12.07% 83.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 29521584 7.57% 91.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 16702188 4.28% 95.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 11171964 2.87% 98.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 4070461 1.04% 99.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2408327 0.62% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 391132406 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 389803312 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 630442 6.26% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 6879641 68.30% 74.56% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2562211 25.44% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1532664 16.20% 16.20% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 16.20% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 16.20% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 16.20% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 16.20% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 16.20% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 16.20% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 16.20% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 16.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 16.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 16.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 16.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 16.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 16.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 16.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 16.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 16.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 16.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 16.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 16.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 16.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 16.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 16.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 16.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 16.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 16.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 16.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 16.20% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 4929602 52.11% 68.31% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2998000 31.69% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 449864838 67.26% 67.26% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 383889 0.06% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 102 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 154509639 23.10% 90.42% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 64042341 9.58% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 441248731 67.42% 67.42% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 435633 0.07% 67.49% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.49% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.49% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.49% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.49% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.49% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.49% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.49% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 147725739 22.57% 90.06% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 65037073 9.94% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 668800812 # Type of FU issued -system.cpu.iq.rate 1.658406 # Inst issue rate -system.cpu.iq.fu_busy_cnt 10072294 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.015060 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1740534066 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 973902079 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 649227410 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 239 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 322 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 654447179 # Type of FU issued +system.cpu.iq.rate 1.677891 # Inst issue rate +system.cpu.iq.fu_busy_cnt 9460266 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014455 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1708614343 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 987386046 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 633379143 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 179 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 280 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 678872985 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 121 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 9444118 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 663907354 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 91 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 7666119 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 47689496 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 34046 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 814715 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 18044957 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 49680139 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 29913 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 831675 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 20169135 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 19567 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 5233 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 1622994 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 4397 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 29335717 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 3955691 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1178658 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 773883644 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1025688 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 173719051 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 74905434 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2287227 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 242970 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 870100 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 814715 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4363839 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4034750 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8398589 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 659340001 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 151050186 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 9460811 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 8080712 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 32831376 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2550941 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 769700415 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 729466 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 165564895 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 77029612 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2297420 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 241239 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 2243400 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 831675 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4474207 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4147009 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8621216 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 645315428 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 144284542 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 9131751 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1585303 # number of nop insts executed -system.cpu.iew.exec_refs 213740794 # number of memory reference insts executed -system.cpu.iew.exec_branches 139088077 # Number of branches executed -system.cpu.iew.exec_stores 62690608 # Number of stores executed -system.cpu.iew.exec_rate 1.634946 # Inst execution rate -system.cpu.iew.wb_sent 654323635 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 649227426 # cumulative count of insts written-back -system.cpu.iew.wb_producers 378014910 # num instructions producing a value -system.cpu.iew.wb_consumers 657704988 # num instructions consuming a value +system.cpu.iew.exec_nop 1619631 # number of nop insts executed +system.cpu.iew.exec_refs 207974195 # number of memory reference insts executed +system.cpu.iew.exec_branches 141482846 # Number of branches executed +system.cpu.iew.exec_stores 63689653 # Number of stores executed +system.cpu.iew.exec_rate 1.654479 # Inst execution rate +system.cpu.iew.wb_sent 638544011 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 633379159 # cumulative count of insts written-back +system.cpu.iew.wb_producers 371951295 # num instructions producing a value +system.cpu.iew.wb_consumers 631497340 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.609871 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.574748 # average fanout of values written-back +system.cpu.iew.wb_rate 1.623876 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.588999 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 202955681 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 221053017 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 7214032 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 361796689 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.578146 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.256071 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 7266341 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 357986400 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.532725 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.266212 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 156712744 43.32% 43.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 96319147 26.62% 69.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 33326252 9.21% 79.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 17957546 4.96% 84.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 16748053 4.63% 88.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7262749 2.01% 90.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 6923592 1.91% 92.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3096479 0.86% 93.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 23450127 6.48% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 161840085 45.21% 45.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 93598872 26.15% 71.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 31669454 8.85% 80.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 16147172 4.51% 84.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 14656641 4.09% 88.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 6778711 1.89% 90.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 6277378 1.75% 92.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3013551 0.84% 93.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 24004536 6.71% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 361796689 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 357986400 # Number of insts commited each cycle system.cpu.commit.committedInsts 506581607 # Number of instructions committed -system.cpu.commit.committedOps 570968167 # Number of ops (including micro ops) committed +system.cpu.commit.committedOps 548694828 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 182890032 # Number of memory references committed -system.cpu.commit.loads 126029555 # Number of loads committed +system.cpu.commit.refs 172745233 # Number of memory references committed +system.cpu.commit.loads 115884756 # Number of loads committed system.cpu.commit.membars 1488542 # Number of memory barriers committed system.cpu.commit.branches 121548301 # Number of branches committed system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. -system.cpu.commit.int_insts 470727693 # Number of committed integer instructions. +system.cpu.commit.int_insts 448454354 # Number of committed integer instructions. system.cpu.commit.function_calls 9757362 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 387738913 67.91% 67.91% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 339219 0.06% 67.97% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 67.97% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 0 0.00% 67.97% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 67.97% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 67.97% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 67.97% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 67.97% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 67.97% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 67.97% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 67.97% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 67.97% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 67.97% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 67.97% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 67.97% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 67.97% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 67.97% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 67.97% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 67.97% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 67.97% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 67.97% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 67.97% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 67.97% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 67.97% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 67.97% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 3 0.00% 67.97% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 67.97% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.97% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.97% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 126029555 22.07% 90.04% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 56860477 9.96% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 375610373 68.46% 68.46% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 339219 0.06% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 3 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 115884756 21.12% 89.64% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 56860477 10.36% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 570968167 # Class of committed instruction -system.cpu.commit.bw_lim_events 23450127 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 548694828 # Class of committed instruction +system.cpu.commit.bw_lim_events 24004536 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1112263272 # The number of ROB reads -system.cpu.rob.rob_writes 1577313182 # The number of ROB writes -system.cpu.timesIdled 375340 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 12146877 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 1103722571 # The number of ROB reads +system.cpu.rob.rob_writes 1571491093 # The number of ROB writes +system.cpu.timesIdled 5225 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 238235 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 505237723 # Number of Instructions Simulated -system.cpu.committedOps 569624283 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.798197 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.798197 # CPI: Total CPI of All Threads -system.cpu.ipc 1.252823 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.252823 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3074448522 # number of integer regfile reads -system.cpu.int_regfile_writes 755651134 # number of integer regfile writes +system.cpu.committedOps 547350944 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.771996 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.771996 # CPI: Total CPI of All Threads +system.cpu.ipc 1.295343 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.295343 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 652860530 # number of integer regfile reads +system.cpu.int_regfile_writes 354600440 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 238959520 # number of misc regfile reads +system.cpu.cc_regfile_reads 2339325657 # number of cc regfile reads +system.cpu.cc_regfile_writes 397666160 # number of cc regfile writes +system.cpu.misc_regfile_reads 231739115 # number of misc regfile reads system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes -system.cpu.toL2Bus.throughput 738060588 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 865494 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 865493 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1111057 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 86 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 86 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 348798 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 348798 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 34444 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3505273 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3539717 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1099136 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 147717056 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 148816192 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 148816192 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 6080 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 2273774999 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 26477230 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 764614178 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 866616 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 866616 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1114497 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 52 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 52 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 348819 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 348819 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 30021 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3515389 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 3545410 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 958720 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 148153024 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 149111744 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 149111744 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 3904 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 2279489000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 23116485 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1825044731 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1829335495 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.cpu.icache.tags.replacements 15336 # number of replacements -system.cpu.icache.tags.tagsinuse 1096.367650 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 115876238 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 17184 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 6743.263385 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 13145 # number of replacements +system.cpu.icache.tags.tagsinuse 1062.088688 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 125003617 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 14983 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 8343.029901 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1096.367650 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.535336 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.535336 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1848 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 81 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 301 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1372 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.902344 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 231812889 # Number of tag accesses -system.cpu.icache.tags.data_accesses 231812889 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 115876248 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 115876248 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 115876248 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 115876248 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 115876248 # number of overall hits -system.cpu.icache.overall_hits::total 115876248 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 21562 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 21562 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 21562 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 21562 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 21562 # number of overall misses -system.cpu.icache.overall_misses::total 21562 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 560819979 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 560819979 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 560819979 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 560819979 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 560819979 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 560819979 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 115897810 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 115897810 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 115897810 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 115897810 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 115897810 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 115897810 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000186 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000186 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000186 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000186 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000186 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000186 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 26009.645627 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 26009.645627 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 26009.645627 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 26009.645627 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 26009.645627 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 26009.645627 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1208 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1062.088688 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.518598 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.518598 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1838 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 49 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 70 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 297 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1390 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.897461 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 250061011 # Number of tag accesses +system.cpu.icache.tags.data_accesses 250061011 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 125003619 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 125003619 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 125003619 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 125003619 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 125003619 # number of overall hits +system.cpu.icache.overall_hits::total 125003619 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 19366 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 19366 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 19366 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 19366 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 19366 # number of overall misses +system.cpu.icache.overall_misses::total 19366 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 525397483 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 525397483 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 525397483 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 525397483 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 525397483 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 525397483 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 125022985 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 125022985 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 125022985 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 125022985 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 125022985 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 125022985 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000155 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000155 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000155 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000155 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000155 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000155 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27129.891717 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 27129.891717 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 27129.891717 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 27129.891717 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 27129.891717 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 27129.891717 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1332 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # 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Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 4253859250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4057.383105 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.990572 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.990572 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 1196298 # number of replacements +system.cpu.dcache.tags.tagsinuse 4055.671895 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 184137490 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1200394 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 153.397543 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 4287130250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4055.671895 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.990154 # 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number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 41 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 41 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 5071107 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 5071107 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 5071107 # number of overall misses -system.cpu.dcache.overall_misses::total 5071107 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 29658271464 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 29658271464 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 73164049214 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 73164049214 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 726000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 726000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 102822320678 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 102822320678 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 102822320678 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 102822320678 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 137971682 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 137971682 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 181156081 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 181156081 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 181159953 # number of overall hits +system.cpu.dcache.overall_hits::total 181159953 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1715015 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1715015 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3361431 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3361431 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 76 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 76 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 40 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 40 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 5076446 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 5076446 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 5076522 # number of overall misses +system.cpu.dcache.overall_misses::total 5076522 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 29355008484 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 29355008484 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 73441852684 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 73441852684 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 636000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 636000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 102796861168 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 102796861168 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 102796861168 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 102796861168 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 131993221 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 131993221 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488895 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 1488895 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 3948 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 3948 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488896 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1488896 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 192210988 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 192210988 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 192210988 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 192210988 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012441 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.012441 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.061848 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.061848 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000028 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000028 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.026383 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.026383 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.026383 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.026383 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17277.957997 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17277.957997 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21810.268089 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 21810.268089 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 17707.317073 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 17707.317073 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 20276.109472 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 20276.109472 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 20276.109472 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 20276.109472 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 17575 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 53737 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1744 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 663 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.077408 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 81.051282 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 186232527 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 186232527 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 186236475 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 186236475 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012993 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.012993 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.061974 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.061974 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.019250 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.019250 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000027 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000027 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.027259 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.027259 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.027258 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.027258 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17116.473316 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17116.473316 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21848.389178 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 21848.389178 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15900 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15900 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 20249.769458 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 20249.769458 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 20249.466302 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 20249.466302 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 21467 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 55050 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2269 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 661 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.460996 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 83.282905 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1111057 # number of writebacks -system.cpu.dcache.writebacks::total 1111057 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 867776 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 867776 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3006223 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3006223 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 41 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 41 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3873999 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3873999 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3873999 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3873999 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 848762 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 848762 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348346 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 348346 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1197108 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1197108 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1197108 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1197108 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12264084776 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 12264084776 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10175822989 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10175822989 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22439907765 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 22439907765 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22439907765 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 22439907765 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006152 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006152 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006422 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006422 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006228 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006228 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006228 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006228 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14449.380128 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14449.380128 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29211.826715 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29211.826715 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18745.098826 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 18745.098826 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18745.098826 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 18745.098826 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 1114497 # number of writebacks +system.cpu.dcache.writebacks::total 1114497 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 862982 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 862982 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3013069 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3013069 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 40 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 40 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3876051 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3876051 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3876051 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3876051 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 852033 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 852033 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348362 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 348362 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 51 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 51 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1200395 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1200395 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1200446 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1200446 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12334131763 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 12334131763 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10183047234 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10183047234 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 2581000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 2581000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22517178997 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 22517178997 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22519759997 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 22519759997 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006455 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006455 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006423 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006423 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.012918 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.012918 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006446 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006446 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006446 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006446 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14476.119778 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14476.119778 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29231.222791 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29231.222791 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 50607.843137 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 50607.843137 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18758.141276 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 18758.141276 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18759.494385 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 18759.494385 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt index 2e9e4306a..5ec8e8e19 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.290499 # Number of seconds simulated -sim_ticks 290498967000 # Number of ticks simulated -final_tick 290498967000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.279362 # Number of seconds simulated +sim_ticks 279362297500 # Number of ticks simulated +final_tick 279362297500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1775828 # Simulator instruction rate (inst/s) -host_op_rate 2001536 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1018347697 # Simulator tick rate (ticks/s) -host_mem_usage 304924 # Number of bytes of host memory used -host_seconds 285.27 # Real time elapsed on the host +host_inst_rate 1833232 # Simulator instruction rate (inst/s) +host_op_rate 1985632 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1010964168 # Simulator tick rate (ticks/s) +host_mem_usage 309500 # Number of bytes of host memory used +host_seconds 276.33 # Real time elapsed on the host sim_insts 506581607 # Number of instructions simulated -sim_ops 570968167 # Number of ops (including micro ops) simulated +sim_ops 548694828 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 2066445500 # Number of bytes read from this memory @@ -21,21 +21,21 @@ system.physmem.bytes_inst_read::total 2066445500 # Nu system.physmem.bytes_written::cpu.data 216067624 # Number of bytes written to this memory system.physmem.bytes_written::total 216067624 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 516611375 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 125228857 # Number of read requests responded to by this memory -system.physmem.num_reads::total 641840232 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 115591527 # Number of read requests responded to by this memory +system.physmem.num_reads::total 632202902 # Number of read requests responded to by this memory system.physmem.num_writes::cpu.data 55727847 # Number of write requests responded to by this memory system.physmem.num_writes::total 55727847 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7113434933 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1455608278 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 8569043211 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7113434933 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7113434933 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 743781041 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 743781041 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7113434933 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2199389318 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 9312824252 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 9312824252 # Throughput (bytes/s) +system.physmem.bw_read::cpu.inst 7397009255 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1513635536 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 8910644791 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7397009255 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7397009255 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 773431583 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 773431583 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7397009255 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2287067119 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 9684076374 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 9684076374 # Throughput (bytes/s) system.membus.data_through_bus 2705365825 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu_clk_domain.clock 500 # Clock period in ticks @@ -124,63 +124,65 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 580997935 # number of cpu cycles simulated +system.cpu.numCycles 558724596 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 506581607 # Number of instructions committed -system.cpu.committedOps 570968167 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 470727695 # Number of integer alu accesses +system.cpu.committedOps 548694828 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 448454356 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses system.cpu.num_func_calls 19311615 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 94895872 # number of instructions that are conditional controls -system.cpu.num_int_insts 470727695 # number of integer instructions +system.cpu.num_conditional_control_insts 90667196 # number of instructions that are conditional controls +system.cpu.num_int_insts 448454356 # number of integer instructions system.cpu.num_fp_insts 16 # number of float instructions -system.cpu.num_int_register_reads 2482508148 # number of times the integer registers were read -system.cpu.num_int_register_writes 646169352 # number of times the integer registers were written +system.cpu.num_int_register_reads 749039746 # number of times the integer registers were read +system.cpu.num_int_register_writes 290003067 # number of times the integer registers were written system.cpu.num_fp_register_reads 16 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 182890034 # number of memory refs -system.cpu.num_load_insts 126029555 # Number of load instructions +system.cpu.num_cc_register_reads 1634230247 # number of times the CC registers were read +system.cpu.num_cc_register_writes 344080722 # number of times the CC registers were written +system.cpu.num_mem_refs 172745235 # number of memory refs +system.cpu.num_load_insts 115884756 # Number of load instructions system.cpu.num_store_insts 56860479 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 580997935 # Number of busy cycles +system.cpu.num_busy_cycles 558724596 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 121548301 # Number of branches fetched system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 387739461 67.91% 67.91% # Class of executed instruction -system.cpu.op_class::IntMult 339219 0.06% 67.97% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 3 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::MemRead 126029555 22.07% 90.04% # Class of executed instruction -system.cpu.op_class::MemWrite 56860479 9.96% 100.00% # Class of executed instruction +system.cpu.op_class::IntAlu 375610921 68.46% 68.46% # Class of executed instruction +system.cpu.op_class::IntMult 339219 0.06% 68.52% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 3 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::MemRead 115884756 21.12% 89.64% # Class of executed instruction +system.cpu.op_class::MemWrite 56860479 10.36% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 570968717 # Class of executed instruction +system.cpu.op_class::total 548695378 # Class of executed instruction ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt index ef3fc2a0f..b06ae633b 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.717366 # Number of seconds simulated -sim_ticks 717366012000 # Number of ticks simulated -final_tick 717366012000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.707539 # Number of seconds simulated +sim_ticks 707539023000 # Number of ticks simulated +final_tick 707539023000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 879063 # Simulator instruction rate (inst/s) -host_op_rate 990556 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1248765490 # Simulator tick rate (ticks/s) -host_mem_usage 313636 # Number of bytes of host memory used -host_seconds 574.46 # Real time elapsed on the host +host_inst_rate 1172742 # Simulator instruction rate (inst/s) +host_op_rate 1270027 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1643133313 # Simulator tick rate (ticks/s) +host_mem_usage 319240 # Number of bytes of host memory used +host_seconds 430.60 # Real time elapsed on the host sim_insts 504986853 # Number of instructions simulated -sim_ops 569034839 # Number of ops (including micro ops) simulated +sim_ops 546878104 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 177280 # Number of bytes read from this memory @@ -25,18 +25,18 @@ system.physmem.num_reads::cpu.data 139879 # Nu system.physmem.num_reads::total 142649 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 95953 # Number of write requests responded to by this memory system.physmem.num_writes::total 95953 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 247126 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12479342 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 12726469 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 247126 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 247126 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 8560472 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 8560472 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 8560472 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 247126 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12479342 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 21286941 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 21286941 # Throughput (bytes/s) +system.physmem.bw_read::cpu.inst 250559 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12652667 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 12903226 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 250559 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 250559 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 8679369 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 8679369 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 8679369 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 250559 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12652667 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 21582595 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 21582595 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 41855 # Transaction distribution system.membus.trans_dist::ReadResp 41855 # Transaction distribution system.membus.trans_dist::Writeback 95953 # Transaction distribution @@ -48,9 +48,9 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 15270528 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 15270528 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1006226000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1018523828 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 1283841000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1290155000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits @@ -138,79 +138,81 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 1434732024 # number of cpu cycles simulated +system.cpu.numCycles 1415078046 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 504986853 # Number of instructions committed -system.cpu.committedOps 569034839 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 470727695 # Number of integer alu accesses +system.cpu.committedOps 546878104 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 448454356 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses system.cpu.num_func_calls 19311615 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 94895872 # number of instructions that are conditional controls -system.cpu.num_int_insts 470727695 # number of integer instructions +system.cpu.num_conditional_control_insts 90667196 # number of instructions that are conditional controls +system.cpu.num_int_insts 448454356 # number of integer instructions system.cpu.num_fp_insts 16 # number of float instructions -system.cpu.num_int_register_reads 2861859644 # number of times the integer registers were read -system.cpu.num_int_register_writes 646169352 # number of times the integer registers were written +system.cpu.num_int_register_reads 748355652 # number of times the integer registers were read +system.cpu.num_int_register_writes 290003067 # number of times the integer registers were written system.cpu.num_fp_register_reads 16 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 182890034 # number of memory refs -system.cpu.num_load_insts 126029555 # Number of load instructions +system.cpu.num_cc_register_reads 1984297856 # number of times the CC registers were read +system.cpu.num_cc_register_writes 344080722 # number of times the CC registers were written +system.cpu.num_mem_refs 172745235 # number of memory refs +system.cpu.num_load_insts 115884756 # Number of load instructions system.cpu.num_store_insts 56860479 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 1434732024 # Number of busy cycles +system.cpu.num_busy_cycles 1415078046 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 121548301 # Number of branches fetched system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 387739461 67.91% 67.91% # Class of executed instruction -system.cpu.op_class::IntMult 339219 0.06% 67.97% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 3 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::MemRead 126029555 22.07% 90.04% # Class of executed instruction -system.cpu.op_class::MemWrite 56860479 9.96% 100.00% # Class of executed instruction +system.cpu.op_class::IntAlu 375610921 68.46% 68.46% # Class of executed instruction +system.cpu.op_class::IntMult 339219 0.06% 68.52% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 3 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::MemRead 115884756 21.12% 89.64% # Class of executed instruction +system.cpu.op_class::MemWrite 56860479 10.36% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 570968717 # Class of executed instruction +system.cpu.op_class::total 548695378 # Class of executed instruction system.cpu.icache.tags.replacements 9788 # number of replacements -system.cpu.icache.tags.tagsinuse 982.663229 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 983.372001 # Cycle average of tags in use system.cpu.icache.tags.total_refs 516599855 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 11521 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 44839.845066 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 982.663229 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.479816 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.479816 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 983.372001 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.480162 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.480162 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1733 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 22 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 257 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1403 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 24 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 256 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1402 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.846191 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 1033234273 # Number of tag accesses system.cpu.icache.tags.data_accesses 1033234273 # Number of data accesses @@ -226,12 +228,12 @@ system.cpu.icache.demand_misses::cpu.inst 11521 # n system.cpu.icache.demand_misses::total 11521 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 11521 # number of overall misses system.cpu.icache.overall_misses::total 11521 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 266195000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 266195000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 266195000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 266195000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 266195000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 266195000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 266342000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 266342000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 266342000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 266342000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 266342000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 266342000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 516611376 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 516611376 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 516611376 # number of demand (read+write) accesses @@ -244,12 +246,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23105.199201 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 23105.199201 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 23105.199201 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 23105.199201 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 23105.199201 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 23105.199201 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23117.958511 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 23117.958511 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 23117.958511 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 23117.958511 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 23117.958511 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 23117.958511 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -264,38 +266,38 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 11521 system.cpu.icache.demand_mshr_misses::total 11521 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 11521 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 11521 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 243153000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 243153000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 243153000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 243153000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 243153000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 243153000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 243300000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 243300000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 243300000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 243300000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 243300000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 243300000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000022 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000022 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21105.199201 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21105.199201 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21105.199201 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 21105.199201 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21105.199201 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 21105.199201 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21117.958511 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21117.958511 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21117.958511 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 21117.958511 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21117.958511 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 21117.958511 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 109895 # number of replacements -system.cpu.l2cache.tags.tagsinuse 27243.192324 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 27249.394273 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1668833 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 141072 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 11.829654 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 343698539000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 23381.854289 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 287.865470 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 3573.472565 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.713558 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008785 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.109054 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.831396 # Average percentage of cache occupancy +system.cpu.l2cache.tags.warmup_cycle 338494923500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 23386.993586 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 287.904756 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 3574.495930 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.713714 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008786 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.109085 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.831586 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 31177 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 283 # Occupied blocks per task id @@ -328,17 +330,17 @@ system.cpu.l2cache.demand_misses::total 142649 # nu system.cpu.l2cache.overall_misses::cpu.inst 2770 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 139879 # number of overall misses system.cpu.l2cache.overall_misses::total 142649 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 144122000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2033729000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 2177851000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5241304000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5241304000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 144122000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7275033000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 7419155000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 144122000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7275033000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 7419155000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 144269000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2035873000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 2180142000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5245341000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5245341000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 144269000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7281214000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 7425483000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 144269000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7281214000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 7425483000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 11521 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 782658 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 794179 # number of ReadReq accesses(hits+misses) @@ -363,17 +365,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.123995 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.240431 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.122817 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.123995 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52029.602888 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52033.491109 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52033.233783 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.158740 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.158740 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52029.602888 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52009.472473 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52009.863371 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52029.602888 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52009.472473 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52009.863371 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52082.671480 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52088.345913 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52087.970374 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52040.210727 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52040.210727 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52082.671480 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52053.660664 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52054.224004 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52082.671480 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52053.660664 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52054.224004 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -395,17 +397,17 @@ system.cpu.l2cache.demand_mshr_misses::total 142649 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2770 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 139879 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 142649 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 110882000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1564709000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1675591000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 110883500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1564721500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1675605000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4031776000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4031776000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 110882000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5596485000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 5707367000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 110882000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5596485000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 5707367000 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 110883500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5596497500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 5707381000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 110883500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5596497500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 5707381000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.240431 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.049939 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.052702 # mshr miss rate for ReadReq accesses @@ -417,27 +419,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.123995 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.240431 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.122817 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.123995 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40029.602888 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40033.491109 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40033.233783 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40030.144404 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40033.810925 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40033.568271 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.158740 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.158740 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40029.602888 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40009.472473 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40009.863371 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40029.602888 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40009.472473 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40009.863371 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40030.144404 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40009.561836 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40009.961514 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40030.144404 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40009.561836 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40009.961514 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 1134822 # number of replacements -system.cpu.dcache.tags.tagsinuse 4065.297446 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 179817786 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 4065.318438 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 170180456 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1138918 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 157.884752 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 11885124000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4065.297446 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.992504 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.992504 # Average percentage of cache occupancy +system.cpu.dcache.tags.avg_refs 149.422922 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 11716392000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4065.318438 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.992509 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.992509 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id @@ -445,64 +447,72 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 343 system.cpu.dcache.tags.age_task_id_blocks_1024::3 3546 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 165 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 363052326 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 363052326 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 122957658 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 122957658 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 343777666 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 343777666 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 113317758 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 113317758 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 53883046 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 53883046 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 2570 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 2570 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 176840704 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 176840704 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 176840704 # number of overall hits -system.cpu.dcache.overall_hits::total 176840704 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 782658 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 782658 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 167200804 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 167200804 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 167203374 # number of overall hits +system.cpu.dcache.overall_hits::total 167203374 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 782657 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 782657 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 356260 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 356260 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1138918 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1138918 # number of demand (read+write) misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 1138917 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1138917 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 1138918 # number of overall misses system.cpu.dcache.overall_misses::total 1138918 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11817433000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11817433000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8864744000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8864744000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 20682177000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 20682177000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 20682177000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 20682177000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 123740316 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 123740316 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11819576500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11819576500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8868781000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8868781000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 20688357500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 20688357500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 20688357500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 20688357500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 114100415 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 114100415 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 2571 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 2571 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 177979622 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 177979622 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 177979622 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 177979622 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.006325 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.006325 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 168339721 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 168339721 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 168342292 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 168342292 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.006859 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.006859 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006568 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.006568 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.006399 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.006399 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.006399 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.006399 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15099.102034 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15099.102034 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24882.793465 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 24882.793465 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 18159.496118 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 18159.496118 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 18159.496118 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 18159.496118 # average overall miss latency +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000389 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.000389 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.006766 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.006766 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.006765 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.006765 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15101.860074 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15101.860074 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24894.125077 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 24894.125077 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 18164.938709 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 18164.938709 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 18164.922760 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 18164.922760 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -513,40 +523,48 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 1064905 # number of writebacks system.cpu.dcache.writebacks::total 1064905 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 782658 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 782658 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 782657 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 782657 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356260 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 356260 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1138918 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1138918 # number of demand (read+write) MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1138917 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1138917 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1138918 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1138918 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10252117000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10252117000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8152224000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8152224000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18404341000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 18404341000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18404341000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 18404341000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006325 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006325 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10254262500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10254262500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8156261000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8156261000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 53000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 53000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18410523500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 18410523500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18410576500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 18410576500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006859 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006859 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006568 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006568 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006399 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006399 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006399 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006399 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13099.102034 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13099.102034 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22882.793465 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22882.793465 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16159.496118 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 16159.496118 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16159.496118 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 16159.496118 # average overall mshr miss latency +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000389 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000389 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006766 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006766 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006765 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006765 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13101.860074 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13101.860074 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22894.125077 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22894.125077 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16164.938709 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 16164.938709 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16164.971051 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 16164.971051 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 197642506 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 200387557 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 794179 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 794179 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 1064905 # Transaction distribution diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index bc10d06da..71d3d27a1 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,108 +1,108 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.456433 # Number of seconds simulated -sim_ticks 456433328000 # Number of ticks simulated -final_tick 456433328000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.451995 # Number of seconds simulated +sim_ticks 451994820000 # Number of ticks simulated +final_tick 451994820000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 81383 # Simulator instruction rate (inst/s) -host_op_rate 150486 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 44923021 # Simulator tick rate (ticks/s) -host_mem_usage 402504 # Number of bytes of host memory used -host_seconds 10160.34 # Real time elapsed on the host +host_inst_rate 140398 # Simulator instruction rate (inst/s) +host_op_rate 259611 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 76745378 # Simulator tick rate (ticks/s) +host_mem_usage 366028 # Number of bytes of host memory used +host_seconds 5889.54 # Real time elapsed on the host sim_insts 826877109 # Number of instructions simulated sim_ops 1528988701 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 210304 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24488448 # Number of bytes read from this memory -system.physmem.bytes_read::total 24698752 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 210304 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 210304 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18796480 # Number of bytes written to this memory -system.physmem.bytes_written::total 18796480 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3286 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 382632 # Number of read requests responded to by this memory -system.physmem.num_reads::total 385918 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 293695 # Number of write requests responded to by this memory -system.physmem.num_writes::total 293695 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 460755 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 53651753 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 54112508 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 460755 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 460755 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 41181217 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 41181217 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 41181217 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 460755 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 53651753 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 95293725 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 385918 # Number of read requests accepted -system.physmem.writeReqs 293695 # Number of write requests accepted -system.physmem.readBursts 385918 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 293695 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 24677440 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 21312 # Total number of bytes read from write queue -system.physmem.bytesWritten 18795136 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 24698752 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18796480 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 333 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 225600 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24537408 # Number of bytes read from this memory +system.physmem.bytes_read::total 24763008 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 225600 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 225600 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18819200 # Number of bytes written to this memory +system.physmem.bytes_written::total 18819200 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3525 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 383397 # Number of read requests responded to by this memory +system.physmem.num_reads::total 386922 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 294050 # Number of write requests responded to by this memory +system.physmem.num_writes::total 294050 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 499121 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 54286923 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 54786044 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 499121 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 499121 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 41635875 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 41635875 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 41635875 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 499121 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 54286923 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 96421919 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 386922 # Number of read requests accepted +system.physmem.writeReqs 294050 # Number of write requests accepted +system.physmem.readBursts 386922 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 294050 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 24741248 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 21760 # Total number of bytes read from write queue +system.physmem.bytesWritten 18817856 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 24763008 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18819200 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 340 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 143951 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 24030 # Per bank write bursts -system.physmem.perBankRdBursts::1 26462 # Per bank write bursts -system.physmem.perBankRdBursts::2 24796 # Per bank write bursts -system.physmem.perBankRdBursts::3 24548 # Per bank write bursts -system.physmem.perBankRdBursts::4 23428 # Per bank write bursts -system.physmem.perBankRdBursts::5 23679 # Per bank write bursts -system.physmem.perBankRdBursts::6 24455 # Per bank write bursts -system.physmem.perBankRdBursts::7 24282 # Per bank write bursts -system.physmem.perBankRdBursts::8 23646 # Per bank write bursts -system.physmem.perBankRdBursts::9 23871 # Per bank write bursts -system.physmem.perBankRdBursts::10 24701 # Per bank write bursts -system.physmem.perBankRdBursts::11 23965 # Per bank write bursts -system.physmem.perBankRdBursts::12 23120 # Per bank write bursts -system.physmem.perBankRdBursts::13 22899 # Per bank write bursts -system.physmem.perBankRdBursts::14 23768 # Per bank write bursts -system.physmem.perBankRdBursts::15 23935 # Per bank write bursts -system.physmem.perBankWrBursts::0 18533 # Per bank write bursts -system.physmem.perBankWrBursts::1 19857 # Per bank write bursts -system.physmem.perBankWrBursts::2 18944 # Per bank write bursts -system.physmem.perBankWrBursts::3 18929 # Per bank write bursts -system.physmem.perBankWrBursts::4 18079 # Per bank write bursts -system.physmem.perBankWrBursts::5 18409 # Per bank write bursts -system.physmem.perBankWrBursts::6 18979 # Per bank write bursts -system.physmem.perBankWrBursts::7 18957 # Per bank write bursts -system.physmem.perBankWrBursts::8 18565 # Per bank write bursts -system.physmem.perBankWrBursts::9 18141 # Per bank write bursts -system.physmem.perBankWrBursts::10 18792 # Per bank write bursts -system.physmem.perBankWrBursts::11 17687 # Per bank write bursts -system.physmem.perBankWrBursts::12 17335 # Per bank write bursts -system.physmem.perBankWrBursts::13 16957 # Per bank write bursts -system.physmem.perBankWrBursts::14 17714 # Per bank write bursts -system.physmem.perBankWrBursts::15 17796 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 187441 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 24125 # Per bank write bursts +system.physmem.perBankRdBursts::1 26507 # Per bank write bursts +system.physmem.perBankRdBursts::2 24686 # Per bank write bursts +system.physmem.perBankRdBursts::3 24623 # Per bank write bursts +system.physmem.perBankRdBursts::4 23302 # Per bank write bursts +system.physmem.perBankRdBursts::5 23746 # Per bank write bursts +system.physmem.perBankRdBursts::6 24462 # Per bank write bursts +system.physmem.perBankRdBursts::7 24273 # Per bank write bursts +system.physmem.perBankRdBursts::8 23635 # Per bank write bursts +system.physmem.perBankRdBursts::9 23973 # Per bank write bursts +system.physmem.perBankRdBursts::10 24803 # Per bank write bursts +system.physmem.perBankRdBursts::11 24077 # Per bank write bursts +system.physmem.perBankRdBursts::12 23354 # Per bank write bursts +system.physmem.perBankRdBursts::13 22972 # Per bank write bursts +system.physmem.perBankRdBursts::14 24056 # Per bank write bursts +system.physmem.perBankRdBursts::15 23988 # Per bank write bursts +system.physmem.perBankWrBursts::0 18554 # Per bank write bursts +system.physmem.perBankWrBursts::1 19852 # Per bank write bursts +system.physmem.perBankWrBursts::2 18949 # Per bank write bursts +system.physmem.perBankWrBursts::3 18947 # Per bank write bursts +system.physmem.perBankWrBursts::4 18033 # Per bank write bursts +system.physmem.perBankWrBursts::5 18442 # Per bank write bursts +system.physmem.perBankWrBursts::6 18997 # Per bank write bursts +system.physmem.perBankWrBursts::7 18979 # Per bank write bursts +system.physmem.perBankWrBursts::8 18544 # Per bank write bursts +system.physmem.perBankWrBursts::9 18172 # Per bank write bursts +system.physmem.perBankWrBursts::10 18845 # Per bank write bursts +system.physmem.perBankWrBursts::11 17739 # Per bank write bursts +system.physmem.perBankWrBursts::12 17374 # Per bank write bursts +system.physmem.perBankWrBursts::13 16976 # Per bank write bursts +system.physmem.perBankWrBursts::14 17812 # Per bank write bursts +system.physmem.perBankWrBursts::15 17814 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 456433277000 # Total gap between requests +system.physmem.totGap 451994795000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 385918 # Read request sizes (log2) +system.physmem.readPktSize::6 386922 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 293695 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 380841 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4378 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 326 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 33 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 294050 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 381621 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4565 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 350 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 36 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -144,43 +144,43 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6284 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 6678 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 16870 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 17435 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 17552 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 17522 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17553 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17543 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17585 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 17598 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 17605 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 17592 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 17759 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 17628 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 17575 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17808 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17489 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17442 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 16856 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 17449 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 17548 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 17578 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17578 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17585 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17629 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 17625 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 17630 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 17600 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 17764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 17623 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 17600 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17825 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17512 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17461 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 30 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 6 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see @@ -193,339 +193,343 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 146599 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 296.532446 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 174.978677 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 323.931077 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 54105 36.91% 36.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 40284 27.48% 64.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 13640 9.30% 73.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7345 5.01% 78.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 5124 3.50% 82.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3885 2.65% 84.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3054 2.08% 86.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2802 1.91% 88.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 16360 11.16% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 146599 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17413 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 22.143169 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 209.002812 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 17400 99.93% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 9 0.05% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 2 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 147161 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 295.990160 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 174.516116 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 323.823787 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 54586 37.09% 37.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 40330 27.41% 64.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 13573 9.22% 73.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7350 4.99% 78.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 5242 3.56% 82.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3782 2.57% 84.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3105 2.11% 86.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2774 1.89% 88.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 16419 11.16% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 147161 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17431 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 22.177500 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 209.580978 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 17417 99.92% 99.92% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 9 0.05% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 3 0.02% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::3072-4095 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17413 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17413 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.865216 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.791721 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.763276 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 17216 98.87% 98.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 134 0.77% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 42 0.24% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 4 0.02% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 3 0.02% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 2 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 1 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 2 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 1 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 17431 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17431 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.868166 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.795967 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.664820 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 17240 98.90% 98.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 139 0.80% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 22 0.13% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 7 0.04% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 7 0.04% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 1 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 2 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 2 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 1 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 1 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 1 0.01% 99.95% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::68-71 1 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 2 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::244-247 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17413 # Writes before turning the bus around for reads -system.physmem.totQLat 4238739250 # Total ticks spent queuing -system.physmem.totMemAccLat 11468458000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1927925000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10993.01 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::72-75 2 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 1 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 1 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::248-251 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 17431 # Writes before turning the bus around for reads +system.physmem.totQLat 4215540250 # Total ticks spent queuing +system.physmem.totMemAccLat 11463952750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1932910000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10904.65 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29743.01 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 54.07 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 41.18 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 54.11 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 41.18 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29654.65 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 54.74 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 41.63 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 54.79 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 41.64 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.74 # Data bus utilization in percentage -system.physmem.busUtilRead 0.42 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.32 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.44 # Average write queue length when enqueuing -system.physmem.readRowHits 317362 # Number of row buffer hits during reads -system.physmem.writeRowHits 215286 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.31 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.30 # Row buffer hit rate for writes -system.physmem.avgGap 671607.63 # Average gap between requests -system.physmem.pageHitRate 78.41 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 317298172500 # Time in different power states -system.physmem.memoryStateTime::REF 15241200000 # Time in different power states +system.physmem.busUtil 0.75 # Data bus utilization in percentage +system.physmem.busUtilRead 0.43 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.33 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing +system.physmem.avgWrQLen 21.68 # Average write queue length when enqueuing +system.physmem.readRowHits 317951 # Number of row buffer hits during reads +system.physmem.writeRowHits 215487 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.25 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.28 # Row buffer hit rate for writes +system.physmem.avgGap 663749.46 # Average gap between requests +system.physmem.pageHitRate 78.37 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 313004335000 # Time in different power states +system.physmem.memoryStateTime::REF 15093000000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 123890904750 # Time in different power states +system.physmem.memoryStateTime::ACT 123894751250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 95293725 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 179074 # Transaction distribution -system.membus.trans_dist::ReadResp 179074 # Transaction distribution -system.membus.trans_dist::Writeback 293695 # Transaction distribution -system.membus.trans_dist::UpgradeReq 143951 # Transaction distribution -system.membus.trans_dist::UpgradeResp 143951 # Transaction distribution -system.membus.trans_dist::ReadExReq 206844 # Transaction distribution -system.membus.trans_dist::ReadExResp 206844 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1353433 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1353433 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1353433 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43495232 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 43495232 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 43495232 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 43495232 # Total data (bytes) +system.membus.throughput 96421919 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 179924 # Transaction distribution +system.membus.trans_dist::ReadResp 179924 # Transaction distribution +system.membus.trans_dist::Writeback 294050 # Transaction distribution +system.membus.trans_dist::UpgradeReq 187441 # Transaction distribution +system.membus.trans_dist::UpgradeResp 187441 # Transaction distribution +system.membus.trans_dist::ReadExReq 206998 # Transaction distribution +system.membus.trans_dist::ReadExResp 206998 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1442776 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1442776 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1442776 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43582208 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 43582208 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 43582208 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 43582208 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 3409046000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 3919297073 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 3478883000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 4009907869 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.9 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 214172576 # Number of BP lookups -system.cpu.branchPred.condPredicted 214172576 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 10017048 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 122104582 # Number of BTB lookups -system.cpu.branchPred.BTBHits 119561484 # Number of BTB hits +system.cpu.branchPred.lookups 231904597 # Number of BP lookups +system.cpu.branchPred.condPredicted 231904597 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 9750550 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 132080719 # Number of BTB lookups +system.cpu.branchPred.BTBHits 129337939 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.917279 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 25755339 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1811393 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 97.923406 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 28018771 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1471173 # Number of incorrect RAS predictions. system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 913134033 # number of cpu cycles simulated +system.cpu.numCycles 903989670 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 172957677 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1180093576 # Number of instructions fetch has processed -system.cpu.fetch.Branches 214172576 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 145316823 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 366593738 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 80936667 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 266990637 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 56859 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 326654 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 167839999 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2941367 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 877562871 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.500418 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.366055 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 186228043 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1278728730 # Number of instructions fetch has processed +system.cpu.fetch.Branches 231904597 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 157356710 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 706545798 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 20232368 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 1261 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 97161 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 819145 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 1413 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 33 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 180562981 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2742944 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 6 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 903809038 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.631393 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.340645 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 515232459 58.71% 58.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 24457756 2.79% 61.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 25984112 2.96% 64.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 28771124 3.28% 67.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 18396810 2.10% 69.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 23701764 2.70% 72.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 30460841 3.47% 76.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 27790154 3.17% 79.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 182767851 20.83% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 493137827 54.56% 54.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 34022388 3.76% 58.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 33226150 3.68% 62.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 33639943 3.72% 65.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 27288864 3.02% 68.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 27888530 3.09% 71.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 37359921 4.13% 75.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 33838464 3.74% 79.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 183406951 20.29% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 877562871 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.234547 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.292355 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 214899100 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 235918889 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 323832333 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 32275243 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 70637306 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2159083489 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 22 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 70637306 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 235683125 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 99102790 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 23033 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 334766565 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 137350052 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2116178959 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 79091 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 86333515 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 11675978 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 34385645 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 2221828274 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5358350843 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3404407883 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 44462 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 903809038 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.256535 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.414539 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 127644706 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 443195641 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 240140806 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 82711701 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 10116184 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2234020290 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 10116184 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 159943307 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 227345077 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 31762 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 285830207 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 220542501 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2184066361 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 187446 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 141210134 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 24116907 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 44409056 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 2289283449 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5527269614 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3515022878 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 52095 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 607787420 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1530 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1409 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 224967788 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 514990281 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 202517058 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 220543258 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 63035338 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2048951027 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 18335 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1800520380 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 873481 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 514890445 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 886881463 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 17783 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 877562871 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.051728 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.961101 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 675242595 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2439 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2426 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 427926698 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 530815140 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 210460978 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 240742093 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 72507120 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2112837832 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 25371 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1829122546 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 418643 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 579202583 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1008004721 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 24819 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 903809038 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.023793 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.068035 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 278621882 31.75% 31.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 139650345 15.91% 47.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 122145227 13.92% 61.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 121221287 13.81% 75.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 101661945 11.58% 86.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 58080162 6.62% 93.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 39790509 4.53% 98.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 14008036 1.60% 99.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2383478 0.27% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 318787682 35.27% 35.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 130796714 14.47% 49.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 120566882 13.34% 63.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 111745228 12.36% 75.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 90951236 10.06% 85.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 61425555 6.80% 92.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 43081513 4.77% 97.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 19099237 2.11% 99.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 7354991 0.81% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 877562871 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 903809038 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 8996464 42.62% 42.62% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 42.62% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 42.62% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.62% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.62% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.62% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 42.62% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.62% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 42.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 42.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.62% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9189518 43.53% 86.15% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2923144 13.85% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 11301614 42.50% 42.50% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 42.50% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 42.50% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.50% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.50% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.50% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 42.50% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.50% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 42.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 42.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.50% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 12240522 46.03% 88.53% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3051129 11.47% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2650510 0.15% 0.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1189351125 66.06% 66.20% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 365099 0.02% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 3880777 0.22% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 57 0.00% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 432328086 24.01% 90.45% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 171944726 9.55% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2716130 0.15% 0.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1212914034 66.31% 66.46% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 390088 0.02% 66.48% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 3880828 0.21% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 131 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 435498208 23.81% 90.50% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 173723127 9.50% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1800520380 # Type of FU issued -system.cpu.iq.rate 1.971803 # Inst issue rate -system.cpu.iq.fu_busy_cnt 21109126 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.011724 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4500567659 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2564101057 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1771520383 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 18579 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 42290 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 4796 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1818970082 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 8914 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 181603573 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1829122546 # Type of FU issued +system.cpu.iq.rate 2.023389 # Inst issue rate +system.cpu.iq.fu_busy_cnt 26593265 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014539 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4589034997 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2692332475 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1799432823 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 31041 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 65517 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 6732 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1852985406 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 14275 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 184951720 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 130889258 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 280840 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 356982 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 53356872 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 146715422 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 214760 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 386957 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 61300792 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 17048 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 593 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 19364 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 985 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 70637306 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 60567761 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 9830463 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2048969362 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 565538 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 514991415 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 202517058 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 4133 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 4684109 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 2987973 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 356982 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 5998592 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4475905 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 10474497 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1780058647 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 427019742 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 20461733 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 10116184 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 166422776 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 10091675 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2112863203 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 400666 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 530817579 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 210460978 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 7795 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 4446284 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3513204 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 386957 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 5751076 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4630882 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 10381958 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1808023539 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 429432372 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 21099007 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 595482816 # number of memory reference insts executed -system.cpu.iew.exec_branches 169731635 # Number of branches executed -system.cpu.iew.exec_stores 168463074 # Number of stores executed -system.cpu.iew.exec_rate 1.949395 # Inst execution rate -system.cpu.iew.wb_sent 1776808975 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1771525179 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1358454852 # num instructions producing a value -system.cpu.iew.wb_consumers 2034017500 # num instructions consuming a value +system.cpu.iew.exec_refs 599547125 # number of memory reference insts executed +system.cpu.iew.exec_branches 171962867 # Number of branches executed +system.cpu.iew.exec_stores 170114753 # Number of stores executed +system.cpu.iew.exec_rate 2.000049 # Inst execution rate +system.cpu.iew.wb_sent 1804768043 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1799439555 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1369592486 # num instructions producing a value +system.cpu.iew.wb_consumers 2093220611 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.940049 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.667868 # average fanout of values written-back +system.cpu.iew.wb_rate 1.990553 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.654299 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 520066569 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 584100413 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 10054119 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 806925565 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.894832 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.501115 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 9836004 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 824637269 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.854135 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.503267 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 332217224 41.17% 41.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 181470930 22.49% 63.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 58010021 7.19% 70.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 87470883 10.84% 81.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 24768584 3.07% 84.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 27525249 3.41% 88.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 9963607 1.23% 89.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 11389679 1.41% 90.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 74109388 9.18% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 355822450 43.15% 43.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 175430054 21.27% 64.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 57247046 6.94% 71.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 86422444 10.48% 81.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 27139119 3.29% 85.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 27033560 3.28% 88.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 9709039 1.18% 89.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 8849743 1.07% 90.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 76983814 9.34% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 806925565 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 824637269 # Number of insts commited each cycle system.cpu.commit.committedInsts 826877109 # Number of instructions committed system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -571,245 +575,244 @@ system.cpu.commit.op_class_0::MemWrite 149160186 9.76% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1528988701 # Class of committed instruction -system.cpu.commit.bw_lim_events 74109388 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 76983814 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2781871447 # The number of ROB reads -system.cpu.rob.rob_writes 4168935238 # The number of ROB writes -system.cpu.timesIdled 4004498 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 35571162 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2860742569 # The number of ROB reads +system.cpu.rob.rob_writes 4305535749 # The number of ROB writes +system.cpu.timesIdled 2688 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 180632 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826877109 # Number of Instructions Simulated system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.104316 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.104316 # CPI: Total CPI of All Threads -system.cpu.ipc 0.905537 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.905537 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2740022491 # number of integer regfile reads -system.cpu.int_regfile_writes 1443498634 # number of integer regfile writes -system.cpu.fp_regfile_reads 4829 # number of floating regfile reads -system.cpu.fp_regfile_writes 113 # number of floating regfile writes -system.cpu.cc_regfile_reads 599382503 # number of cc regfile reads -system.cpu.cc_regfile_writes 407768692 # number of cc regfile writes -system.cpu.misc_regfile_reads 978269285 # number of misc regfile reads +system.cpu.cpi 1.093258 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.093258 # CPI: Total CPI of All Threads +system.cpu.ipc 0.914698 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.914698 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2763635866 # number of integer regfile reads +system.cpu.int_regfile_writes 1467536960 # number of integer regfile writes +system.cpu.fp_regfile_reads 6799 # number of floating regfile reads +system.cpu.fp_regfile_writes 207 # number of floating regfile writes +system.cpu.cc_regfile_reads 600939716 # number of cc regfile reads +system.cpu.cc_regfile_writes 409698109 # number of cc regfile writes +system.cpu.misc_regfile_reads 991748256 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 703796459 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 1916652 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1916650 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2331152 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 145500 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 145500 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 771513 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 771513 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 160475 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7692392 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7852867 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 475520 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311441408 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 311916928 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 311916928 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 9319232 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 4920349397 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 717782102 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 1964869 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1964868 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2332907 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 189308 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 189308 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 771503 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 771503 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 206675 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7788165 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7994840 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 551936 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311758592 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 312310528 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 312310528 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 12123264 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 4978085168 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 230044243 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 297561992 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3958184582 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3985022632 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.cpu.icache.tags.replacements 5899 # number of replacements -system.cpu.icache.tags.tagsinuse 1053.974853 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 167683081 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 7506 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 22339.872236 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 6996 # number of replacements +system.cpu.icache.tags.tagsinuse 1078.278361 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 180359326 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 8602 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 20967.138572 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1053.974853 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.514636 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.514636 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1607 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 63 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 269 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1203 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.784668 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 335833041 # Number of tag accesses -system.cpu.icache.tags.data_accesses 335833041 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 167684909 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 167684909 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 167684909 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 167684909 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 167684909 # number of overall hits -system.cpu.icache.overall_hits::total 167684909 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 155090 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 155090 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 155090 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 155090 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 155090 # number of overall misses -system.cpu.icache.overall_misses::total 155090 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 984545992 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 984545992 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 984545992 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 984545992 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 984545992 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 984545992 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 167839999 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 167839999 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 167839999 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 167839999 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 167839999 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 167839999 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000924 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000924 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000924 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000924 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000924 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000924 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6348.223561 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 6348.223561 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 6348.223561 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 6348.223561 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 6348.223561 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 6348.223561 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 296 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1078.278361 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.526503 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.526503 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1606 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 56 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 301 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1173 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.784180 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 361324012 # Number of tag accesses +system.cpu.icache.tags.data_accesses 361324012 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 180362453 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 180362453 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 180362453 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 180362453 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 180362453 # number of overall hits +system.cpu.icache.overall_hits::total 180362453 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 200528 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 200528 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 200528 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 200528 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 200528 # number of overall misses +system.cpu.icache.overall_misses::total 200528 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1221704738 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1221704738 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1221704738 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1221704738 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1221704738 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1221704738 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 180562981 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 180562981 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 180562981 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 180562981 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 180562981 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 180562981 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001111 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.001111 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.001111 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.001111 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.001111 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.001111 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6092.439649 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 6092.439649 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 6092.439649 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 6092.439649 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 6092.439649 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 6092.439649 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 899 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 14 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 59.200000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 64.214286 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2045 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2045 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2045 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2045 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2045 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2045 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 153045 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 153045 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 153045 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 153045 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 153045 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 153045 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 588350757 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 588350757 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 588350757 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 588350757 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 588350757 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 588350757 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000912 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000912 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000912 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000912 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000912 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000912 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 3844.299108 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 3844.299108 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 3844.299108 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 3844.299108 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 3844.299108 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 3844.299108 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2477 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2477 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2477 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2477 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2477 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2477 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 198051 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 198051 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 198051 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 198051 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 198051 # 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Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3703753 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 386599 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 9.580348 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 196870877000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 21114.566965 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 251.784741 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 8320.474659 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.644365 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007684 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.253921 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.905970 # 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number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 22865571481 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 23067647981 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 202076500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 22865571481 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 23067647981 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.442277 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099675 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.101113 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.989203 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.989203 # 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average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60434.932062 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10048.475853 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10048.475853 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59194.176530 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59194.176530 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61477.487070 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59755.213538 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59769.881876 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61477.487070 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59755.213538 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59769.881876 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3526 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 176399 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 179925 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 187409 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 187409 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 207030 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 207030 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3526 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 383429 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 386955 # 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number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 215844500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 22877151744 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 23092996244 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 215844500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 22877151744 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 23092996244 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.408812 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099840 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.101341 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.989969 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.989969 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268346 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268346 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.408812 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.151056 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.151929 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.408812 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.151056 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.151929 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61215.116279 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60394.677475 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60410.755659 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10087.290440 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10087.290440 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59042.607506 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59042.607506 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61215.116279 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59664.636071 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59678.764311 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61215.116279 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59664.636071 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59678.764311 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 2531024 # number of replacements -system.cpu.dcache.tags.tagsinuse 4088.627952 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 389841381 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2535120 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 153.776303 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1681469250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4088.627952 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.998200 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.998200 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 2534225 # number of replacements +system.cpu.dcache.tags.tagsinuse 4088.724937 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 389006458 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2538321 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 153.253453 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1658510250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4088.724937 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.998224 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.998224 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 738 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3313 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 803 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3247 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 788808720 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 788808720 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 241135682 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 241135682 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148226318 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148226318 # 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number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3707417 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3707417 # number of overall misses +system.cpu.dcache.overall_misses::total 3707417 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 55514293617 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 55514293617 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 27913016377 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 27913016377 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 83427309994 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 83427309994 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 83427309994 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 83427309994 # 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miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.006261 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009602 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009602 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009602 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009602 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20099.015546 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 20099.015546 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28701.123833 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 28701.123833 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22227.173673 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22227.173673 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22227.173673 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22227.173673 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 6549 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 751 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 8.720373 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 392296957 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 392296957 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 392296957 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 392296957 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011222 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.011222 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006563 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.006563 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.009451 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009451 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009451 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009451 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20346.047970 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 20346.047970 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28514.326494 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 28514.326494 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22502.812603 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22502.812603 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22502.812603 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22502.812603 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 9167 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 150 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1009 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.085233 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 37.500000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2331152 # number of writebacks -system.cpu.dcache.writebacks::total 2331152 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1077049 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1077049 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 17132 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 17132 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1094181 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1094181 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1094181 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1094181 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1763867 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1763867 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 916752 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 916752 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2680619 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2680619 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2680619 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2680619 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30539375250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 30539375250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 24659789417 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 24659789417 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 55199164667 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 55199164667 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 55199164667 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 55199164667 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007230 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007230 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006146 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006146 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006819 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006819 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006819 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006819 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17313.876415 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17313.876415 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26899.084395 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26899.084395 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20591.947109 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20591.947109 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20591.947109 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20591.947109 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 2332907 # number of writebacks +system.cpu.dcache.writebacks::total 2332907 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 961470 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 961470 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18318 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 18318 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 979788 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 979788 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 979788 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 979788 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1767035 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1767035 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 960594 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 960594 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2727629 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2727629 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2727629 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2727629 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30608716000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 30608716000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 25669918867 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 25669918867 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 56278634867 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 56278634867 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 56278634867 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 56278634867 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007268 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007268 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006440 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006440 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006953 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006953 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006953 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006953 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17322.076812 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17322.076812 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26722.963986 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26722.963986 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20632.804119 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20632.804119 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20632.804119 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20632.804119 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |