diff options
Diffstat (limited to 'tests/long/se/20.parser/ref')
15 files changed, 376 insertions, 119 deletions
diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini index 08e7e2cb5..52f83ef58 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini @@ -492,9 +492,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -525,9 +524,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout index 5e99fb7a2..90b73e8ee 100755 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:17:37 -gem5 started May 8 2012 16:25:50 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:14:06 +gem5 started Jun 4 2012 17:38:42 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -67,4 +67,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 233090215000 because target called exit() +Exiting @ tick 233057542500 because target called exit() diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index 8dc91f46c..b64f135f3 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -4,23 +4,36 @@ sim_seconds 0.233058 # Nu sim_ticks 233057542500 # Number of ticks simulated final_tick 233057542500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 104599 # Simulator instruction rate (inst/s) -host_op_rate 117832 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 47897344 # Simulator tick rate (ticks/s) -host_mem_usage 237516 # Number of bytes of host memory used -host_seconds 4865.77 # Real time elapsed on the host +host_inst_rate 102553 # Simulator instruction rate (inst/s) +host_op_rate 115527 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 46960535 # Simulator tick rate (ticks/s) +host_mem_usage 237172 # Number of bytes of host memory used +host_seconds 4962.84 # Real time elapsed on the host sim_insts 508954936 # Number of instructions simulated sim_ops 573341497 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 15214144 # Number of bytes read from this memory -system.physmem.bytes_inst_read 246208 # Number of instructions bytes read from this memory -system.physmem.bytes_written 10947904 # Number of bytes written to this memory -system.physmem.num_reads 237721 # Number of read requests responded to by this memory -system.physmem.num_writes 171061 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 65280633 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1056426 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 46975111 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 112255745 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 246208 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 14967936 # Number of bytes read from this memory +system.physmem.bytes_read::total 15214144 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 246208 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 246208 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 10947904 # Number of bytes written to this memory +system.physmem.bytes_written::total 10947904 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3847 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 233874 # Number of read requests responded to by this memory +system.physmem.num_reads::total 237721 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 171061 # Number of write requests responded to by this memory +system.physmem.num_writes::total 171061 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 1056426 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 64224208 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 65280633 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1056426 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1056426 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 46975111 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 46975111 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 46975111 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1056426 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 64224208 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 112255745 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -368,11 +381,17 @@ system.cpu.icache.demand_accesses::total 126860220 # nu system.cpu.icache.overall_accesses::cpu.inst 126860220 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 126860220 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000157 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000157 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000157 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000157 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000157 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000157 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13468.126288 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13468.126288 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 13468.126288 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13468.126288 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 13468.126288 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13468.126288 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -402,11 +421,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 171640500 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 171640500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 171640500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000143 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000143 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000143 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000143 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000143 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000143 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 9466.164792 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 9466.164792 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 9466.164792 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 9466.164792 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 9466.164792 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 9466.164792 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 1204809 # number of replacements system.cpu.dcache.tagsinuse 4052.906677 # Cycle average of tags in use @@ -462,15 +487,25 @@ system.cpu.dcache.demand_accesses::total 195622115 # nu system.cpu.dcache.overall_accesses::cpu.data 195622115 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 195622115 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009328 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.009328 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.026850 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.026850 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000035 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000035 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.014186 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.014186 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.014186 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.014186 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11591.851869 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11591.851869 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17278.996354 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 17278.996354 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 10839.743590 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 10839.743590 # average LoadLockedReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 14576.321503 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14576.321503 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 14576.321503 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14576.321503 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 602000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -508,13 +543,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 10589925497 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10589925497 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 10589925497 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006138 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006138 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006292 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006292 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006181 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006181 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006181 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006181 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7154.602287 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7154.602287 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 12837.889185 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 12837.889185 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8758.830640 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 8758.830640 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8758.830640 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 8758.830640 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 218501 # number of replacements system.cpu.l2cache.tagsinuse 20930.395337 # Cycle average of tags in use @@ -587,20 +630,30 @@ system.cpu.l2cache.overall_accesses::cpu.data 1208896 system.cpu.l2cache.overall_accesses::total 1226913 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.213798 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.143718 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.145145 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.230769 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.230769 # miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.319698 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.319698 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.213798 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.193480 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.193778 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.213798 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.193480 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.193778 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34286.474559 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34198.118961 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34200.768309 # average ReadReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 6212.121212 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 6212.121212 # average UpgradeReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34242.649952 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34242.649952 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34286.474559 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34218.925424 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34220.019853 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34286.474559 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34218.925424 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34220.019853 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -648,20 +701,30 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7255661000 system.cpu.l2cache.overall_mshr_miss_latency::total 7375243500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.213521 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.143693 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.145114 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.230769 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.230769 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.319698 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.319698 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.213521 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.193462 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.193756 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.213521 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.193462 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.193756 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31084.611385 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31036.880970 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31038.310611 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31045.454545 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31045.454545 # average UpgradeReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31008.610514 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31008.610514 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31084.611385 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31023.670764 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31024.656952 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31084.611385 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31023.670764 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31024.656952 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini index 6e34c6137..f2f9dd654 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini @@ -112,9 +112,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout index 61ef97f09..5bc6f404c 100755 --- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:17:37 -gem5 started May 8 2012 16:27:44 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:14:06 +gem5 started Jun 4 2012 17:42:59 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt index 4ec8704b3..eec1b9eb1 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt @@ -4,23 +4,35 @@ sim_seconds 0.290499 # Nu sim_ticks 290498972000 # Number of ticks simulated final_tick 290498972000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1142576 # Simulator instruction rate (inst/s) -host_op_rate 1287798 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 655209825 # Simulator tick rate (ticks/s) -host_mem_usage 224168 # Number of bytes of host memory used -host_seconds 443.37 # Real time elapsed on the host +host_inst_rate 2223848 # Simulator instruction rate (inst/s) +host_op_rate 2506499 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1275264214 # Simulator tick rate (ticks/s) +host_mem_usage 224628 # Number of bytes of host memory used +host_seconds 227.80 # Real time elapsed on the host sim_insts 506581615 # Number of instructions simulated sim_ops 570968176 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 2489298238 # Number of bytes read from this memory -system.physmem.bytes_inst_read 2066445536 # Number of instructions bytes read from this memory -system.physmem.bytes_written 216067624 # Number of bytes written to this memory -system.physmem.num_reads 641840242 # Number of read requests responded to by this memory -system.physmem.num_writes 55727847 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 8569043191 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 7113434935 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 743781028 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 9312824219 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 2066445536 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 422852702 # Number of bytes read from this memory +system.physmem.bytes_read::total 2489298238 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 2066445536 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 2066445536 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 216067624 # Number of bytes written to this memory +system.physmem.bytes_written::total 216067624 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 516611384 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 125228858 # Number of read requests responded to by this memory +system.physmem.num_reads::total 641840242 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 55727847 # Number of write requests responded to by this memory +system.physmem.num_writes::total 55727847 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 7113434935 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1455608256 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 8569043191 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7113434935 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7113434935 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 743781028 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 743781028 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7113434935 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2199389284 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 9312824219 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini index 77531d0fb..036427da7 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini @@ -161,9 +161,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -194,9 +193,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout b/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout index 22208540d..ec9ed9cd5 100755 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:17:37 -gem5 started May 8 2012 16:29:57 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:14:06 +gem5 started Jun 4 2012 17:46:58 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt index 8678fa0ad..85dc67786 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt @@ -4,23 +4,36 @@ sim_seconds 0.722234 # Nu sim_ticks 722234364000 # Number of ticks simulated final_tick 722234364000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 593765 # Simulator instruction rate (inst/s) -host_op_rate 669073 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 849204818 # Simulator tick rate (ticks/s) -host_mem_usage 233356 # Number of bytes of host memory used -host_seconds 850.48 # Real time elapsed on the host +host_inst_rate 1114772 # Simulator instruction rate (inst/s) +host_op_rate 1256160 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1594352181 # Simulator tick rate (ticks/s) +host_mem_usage 233804 # Number of bytes of host memory used +host_seconds 453.00 # Real time elapsed on the host sim_insts 504986861 # Number of instructions simulated sim_ops 569034848 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 14797056 # Number of bytes read from this memory -system.physmem.bytes_inst_read 188608 # Number of instructions bytes read from this memory -system.physmem.bytes_written 11027328 # Number of bytes written to this memory -system.physmem.num_reads 231204 # Number of read requests responded to by this memory -system.physmem.num_writes 172302 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 20487887 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 261145 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 15268351 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 35756238 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 188608 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 14608448 # Number of bytes read from this memory +system.physmem.bytes_read::total 14797056 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 188608 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 188608 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 11027328 # Number of bytes written to this memory +system.physmem.bytes_written::total 11027328 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2947 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 228257 # Number of read requests responded to by this memory +system.physmem.num_reads::total 231204 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 172302 # Number of write requests responded to by this memory +system.physmem.num_writes::total 172302 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 261145 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 20226742 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 20487887 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 261145 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 261145 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 15268351 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 15268351 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 15268351 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 261145 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 20226742 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 35756238 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -120,11 +133,17 @@ system.cpu.icache.demand_accesses::total 516611385 # nu system.cpu.icache.overall_accesses::cpu.inst 516611385 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 516611385 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000022 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24743.338252 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 24743.338252 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 24743.338252 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 24743.338252 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 24743.338252 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 24743.338252 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -146,11 +165,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 250505000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 250505000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 250505000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000022 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000022 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21743.338252 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21743.338252 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21743.338252 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 21743.338252 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21743.338252 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 21743.338252 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 1134822 # number of replacements system.cpu.dcache.tagsinuse 4065.490059 # Cycle average of tags in use @@ -202,13 +227,21 @@ system.cpu.dcache.demand_accesses::total 177979623 # nu system.cpu.dcache.overall_accesses::cpu.data 177979623 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 177979623 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.006325 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.006325 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006568 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.006568 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.006399 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.006399 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.006399 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.006399 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19807.762778 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 19807.762778 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28150.625947 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 28150.625947 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 22417.457622 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22417.457622 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 22417.457622 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22417.457622 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -236,13 +269,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 22114892000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22114892000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 22114892000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006325 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006325 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006568 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006568 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006399 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006399 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006399 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006399 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16807.762778 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16807.762778 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25150.625947 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25150.625947 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19417.457622 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 19417.457622 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19417.457622 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 19417.457622 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 212089 # number of replacements system.cpu.l2cache.tagsinuse 20443.163614 # Cycle average of tags in use @@ -307,18 +348,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 1138918 system.cpu.l2cache.overall_accesses::total 1150439 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.255794 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.138280 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.139985 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.336920 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.336920 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.255794 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.200416 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.200970 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.255794 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.200416 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.200970 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -353,18 +402,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9130280000 system.cpu.l2cache.overall_mshr_miss_latency::total 9248160000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.255794 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.138280 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.139985 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.336920 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.336920 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.255794 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.200416 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.200970 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.255794 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.200416 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.200970 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout index e360d8cc6..29af0d223 100755 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 3 2012 13:30:44 -gem5 started Jun 3 2012 13:30:59 -gem5 executing on burrito +gem5 compiled Jun 4 2012 13:44:28 +gem5 started Jun 4 2012 15:27:18 +gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index 1dc4deb54..4a5cfadf8 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -4,23 +4,36 @@ sim_seconds 0.459938 # Nu sim_ticks 459937575500 # Number of ticks simulated final_tick 459937575500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 75971 # Simulator instruction rate (inst/s) -host_op_rate 140479 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 42257715 # Simulator tick rate (ticks/s) -host_mem_usage 287264 # Number of bytes of host memory used -host_seconds 10884.11 # Real time elapsed on the host +host_inst_rate 70939 # Simulator instruction rate (inst/s) +host_op_rate 131174 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 39458742 # Simulator tick rate (ticks/s) +host_mem_usage 264492 # Number of bytes of host memory used +host_seconds 11656.16 # Real time elapsed on the host sim_insts 826877144 # Number of instructions simulated sim_ops 1528988756 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 37483008 # Number of bytes read from this memory -system.physmem.bytes_inst_read 379264 # Number of instructions bytes read from this memory -system.physmem.bytes_written 26316864 # Number of bytes written to this memory -system.physmem.num_reads 585672 # Number of read requests responded to by this memory -system.physmem.num_writes 411201 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 81495859 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 824599 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 57218339 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 138714198 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 379264 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 37103744 # Number of bytes read from this memory +system.physmem.bytes_read::total 37483008 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 379264 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 379264 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 26316864 # Number of bytes written to this memory +system.physmem.bytes_written::total 26316864 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 5926 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 579746 # Number of read requests responded to by this memory +system.physmem.num_reads::total 585672 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 411201 # Number of write requests responded to by this memory +system.physmem.num_writes::total 411201 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 824599 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 80671261 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 81495859 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 824599 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 824599 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 57218339 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 57218339 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 57218339 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 824599 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 80671261 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 138714198 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 551 # Number of system calls system.cpu.numCycles 919875152 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -323,11 +336,17 @@ system.cpu.icache.demand_accesses::total 183482871 # nu system.cpu.icache.overall_accesses::cpu.inst 183482871 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 183482871 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001223 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.001223 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.001223 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.001223 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.001223 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.001223 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 7316.318982 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 7316.318982 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 7316.318982 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 7316.318982 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 7316.318982 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 7316.318982 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -357,11 +376,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 915847000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 915847000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 915847000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001209 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001209 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001209 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.001209 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001209 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.001209 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4128.170455 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4128.170455 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4128.170455 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 4128.170455 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4128.170455 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 4128.170455 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 2527239 # number of replacements system.cpu.dcache.tagsinuse 4087.019700 # Cycle average of tags in use @@ -405,13 +430,21 @@ system.cpu.dcache.demand_accesses::total 418117752 # nu system.cpu.dcache.overall_accesses::cpu.data 418117752 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 418117752 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009926 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.009926 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006630 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.006630 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.008750 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.008750 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.008750 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.008750 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14615.279528 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14615.279528 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 20361.164450 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 20361.164450 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 16168.484782 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16168.484782 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 16168.484782 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16168.484782 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -447,13 +480,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 32037464500 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 32037464500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 32037464500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006548 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006548 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006569 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006569 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006556 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006556 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006556 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006556 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8467.243688 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8467.243688 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 17478.038644 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 17478.038644 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11688.307739 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11688.307739 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11688.307739 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11688.307739 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 574865 # number of replacements system.cpu.l2cache.tagsinuse 21613.693664 # Cycle average of tags in use @@ -526,20 +567,30 @@ system.cpu.l2cache.overall_accesses::cpu.data 2531251 system.cpu.l2cache.overall_accesses::total 2543331 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.490563 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.189057 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.191112 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.993847 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.993847 # miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.320333 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.320333 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.490563 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.229051 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.230293 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.490563 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.229051 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.230293 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34256.749916 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34141.461663 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34143.478877 # average ReadReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 47.078982 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 47.078982 # average UpgradeReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34258.562829 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34258.562829 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34256.749916 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34191.354554 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34192.016199 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34256.749916 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34191.354554 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34192.016199 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -578,20 +629,30 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 17981733500 system.cpu.l2cache.overall_mshr_miss_latency::total 18165638500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.490563 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.189057 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.191112 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.993847 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.993847 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.320333 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.320333 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.490563 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.229051 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.230293 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.490563 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.229051 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.230293 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31033.580830 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31023.222582 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31023.403822 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31001.425472 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31001.425472 # average UpgradeReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31002.716302 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31002.716302 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31033.580830 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31014.485542 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31014.678741 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31033.580830 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31014.485542 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31014.678741 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout index 5153e8f50..337e5053a 100755 --- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout +++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 3 2012 13:30:44 -gem5 started Jun 3 2012 13:30:58 -gem5 executing on burrito +gem5 compiled Jun 4 2012 13:44:28 +gem5 started Jun 4 2012 15:38:11 +gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt index 38deb4a58..a8445ed5c 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt @@ -4,23 +4,35 @@ sim_seconds 0.885229 # Nu sim_ticks 885229360000 # Number of ticks simulated final_tick 885229360000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 648787 # Simulator instruction rate (inst/s) -host_op_rate 1199679 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 694571010 # Simulator tick rate (ticks/s) -host_mem_usage 243520 # Number of bytes of host memory used -host_seconds 1274.50 # Real time elapsed on the host +host_inst_rate 1285236 # Simulator instruction rate (inst/s) +host_op_rate 2376545 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1375933868 # Simulator tick rate (ticks/s) +host_mem_usage 220604 # Number of bytes of host memory used +host_seconds 643.37 # Real time elapsed on the host sim_insts 826877145 # Number of instructions simulated sim_ops 1528988757 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 10832432532 # Number of bytes read from this memory -system.physmem.bytes_inst_read 8546776872 # Number of instructions bytes read from this memory -system.physmem.bytes_written 991849460 # Number of bytes written to this memory -system.physmem.num_reads 1452449298 # Number of read requests responded to by this memory -system.physmem.num_writes 149160201 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 12236865406 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 9654872803 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 1120443475 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 13357308881 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 8546776872 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 2285655660 # Number of bytes read from this memory +system.physmem.bytes_read::total 10832432532 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 8546776872 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 8546776872 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 991849460 # Number of bytes written to this memory +system.physmem.bytes_written::total 991849460 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1068347109 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 384102189 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1452449298 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 149160201 # Number of write requests responded to by this memory +system.physmem.num_writes::total 149160201 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 9654872803 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2581992604 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 12236865406 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 9654872803 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 9654872803 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1120443475 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1120443475 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 9654872803 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3702436078 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 13357308881 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 551 # Number of system calls system.cpu.numCycles 1770458721 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout index c9e0b30c1..1909314a2 100755 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 3 2012 13:30:44 -gem5 started Jun 3 2012 13:30:58 -gem5 executing on burrito +gem5 compiled Jun 4 2012 13:44:28 +gem5 started Jun 4 2012 15:45:58 +gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt index c48e15266..b3396b2cb 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt @@ -4,23 +4,36 @@ sim_seconds 1.658730 # Nu sim_ticks 1658729604000 # Number of ticks simulated final_tick 1658729604000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 478704 # Simulator instruction rate (inst/s) -host_op_rate 885178 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 960288988 # Simulator tick rate (ticks/s) -host_mem_usage 252496 # Number of bytes of host memory used -host_seconds 1727.32 # Real time elapsed on the host +host_inst_rate 615589 # Simulator instruction rate (inst/s) +host_op_rate 1138293 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1234881669 # Simulator tick rate (ticks/s) +host_mem_usage 229524 # Number of bytes of host memory used +host_seconds 1343.23 # Real time elapsed on the host sim_insts 826877145 # Number of instructions simulated sim_ops 1528988757 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 37094976 # Number of bytes read from this memory -system.physmem.bytes_inst_read 148544 # Number of instructions bytes read from this memory -system.physmem.bytes_written 26349376 # Number of bytes written to this memory -system.physmem.num_reads 579609 # Number of read requests responded to by this memory -system.physmem.num_writes 411709 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 22363486 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 89553 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 15885275 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 38248761 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 148544 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 36946432 # Number of bytes read from this memory +system.physmem.bytes_read::total 37094976 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 148544 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 148544 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 26349376 # Number of bytes written to this memory +system.physmem.bytes_written::total 26349376 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2321 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 577288 # Number of read requests responded to by this memory +system.physmem.num_reads::total 579609 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 411709 # Number of write requests responded to by this memory +system.physmem.num_writes::total 411709 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 89553 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 22273933 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 22363486 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 89553 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 89553 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 15885275 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 15885275 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 15885275 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 89553 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 22273933 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 38248761 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 551 # Number of system calls system.cpu.numCycles 3317459208 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -78,11 +91,17 @@ system.cpu.icache.demand_accesses::total 1068347110 # nu system.cpu.icache.overall_accesses::cpu.inst 1068347110 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 1068347110 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000003 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000003 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000003 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000003 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000003 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000003 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48641.791045 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 48641.791045 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 48641.791045 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 48641.791045 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 48641.791045 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 48641.791045 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -104,11 +123,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 128436000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 128436000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 128436000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 45641.791045 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 45641.791045 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 45641.791045 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 45641.791045 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 45641.791045 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 45641.791045 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 2514362 # number of replacements system.cpu.dcache.tagsinuse 4086.472055 # Cycle average of tags in use @@ -152,13 +177,21 @@ system.cpu.dcache.demand_accesses::total 533262390 # nu system.cpu.dcache.overall_accesses::cpu.data 533262390 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 533262390 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004497 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004497 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005303 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.005303 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.004723 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.004723 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.004723 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.004723 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22005.441660 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 22005.441660 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27169.175798 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 27169.175798 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 23627.363053 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23627.363053 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 23627.363053 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 23627.363053 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -186,13 +219,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 51949140000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 51949140000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 51949140000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004497 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004497 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005303 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005303 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.004723 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.004723 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19005.440502 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19005.440502 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24169.168845 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24169.168845 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20627.360075 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20627.360075 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20627.360075 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20627.360075 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 568906 # number of replacements system.cpu.l2cache.tagsinuse 21228.193311 # Cycle average of tags in use @@ -257,18 +298,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 2518458 system.cpu.l2cache.overall_accesses::total 2521272 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.824805 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.190606 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.191637 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.313551 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.313551 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.824805 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.229223 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.229888 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.824805 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.229223 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.229888 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.024190 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.024190 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.010393 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000.010352 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.010393 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000.010352 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -303,18 +352,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23091520000 system.cpu.l2cache.overall_mshr_miss_latency::total 23184360000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.824805 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.190606 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.191637 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.313551 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.313551 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.824805 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.229223 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.229888 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.824805 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.229223 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.229888 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |