diff options
Diffstat (limited to 'tests/long/se/20.parser/ref')
6 files changed, 3021 insertions, 2887 deletions
diff --git a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt index f1692fa7b..93f93a6a3 100644 --- a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt @@ -1,101 +1,101 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.411003 # Number of seconds simulated -sim_ticks 411003011000 # Number of ticks simulated -final_tick 411003011000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.410940 # Number of seconds simulated +sim_ticks 410940483000 # Number of ticks simulated +final_tick 410940483000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 279515 # Simulator instruction rate (inst/s) -host_op_rate 279515 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 187744969 # Simulator tick rate (ticks/s) -host_mem_usage 239248 # Number of bytes of host memory used -host_seconds 2189.16 # Real time elapsed on the host +host_inst_rate 339016 # Simulator instruction rate (inst/s) +host_op_rate 339016 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 227676015 # Simulator tick rate (ticks/s) +host_mem_usage 297088 # Number of bytes of host memory used +host_seconds 1804.94 # Real time elapsed on the host sim_insts 611901617 # Number of instructions simulated sim_ops 611901617 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 24320320 # Number of bytes read from this memory -system.physmem.bytes_read::total 24320320 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 170944 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 170944 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18724480 # Number of bytes written to this memory -system.physmem.bytes_written::total 18724480 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 380005 # Number of read requests responded to by this memory -system.physmem.num_reads::total 380005 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 292570 # Number of write requests responded to by this memory -system.physmem.num_writes::total 292570 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 59173094 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 59173094 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 415919 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 415919 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 45558012 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 45558012 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 45558012 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 59173094 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 104731106 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 380005 # Number of read requests accepted -system.physmem.writeReqs 292570 # Number of write requests accepted -system.physmem.readBursts 380005 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 292570 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 24297088 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 23232 # Total number of bytes read from write queue -system.physmem.bytesWritten 18722944 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 24320320 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18724480 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 363 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 24320576 # Number of bytes read from this memory +system.physmem.bytes_read::total 24320576 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 171008 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 171008 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18724416 # Number of bytes written to this memory +system.physmem.bytes_written::total 18724416 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 380009 # Number of read requests responded to by this memory +system.physmem.num_reads::total 380009 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 292569 # Number of write requests responded to by this memory +system.physmem.num_writes::total 292569 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 59182721 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 59182721 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 416138 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 416138 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 45564788 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 45564788 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 45564788 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 59182721 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 104747509 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 380009 # Number of read requests accepted +system.physmem.writeReqs 292569 # Number of write requests accepted +system.physmem.readBursts 380009 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 292569 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 24297024 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 23552 # Total number of bytes read from write queue +system.physmem.bytesWritten 18722752 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 24320576 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18724416 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 368 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 23737 # Per bank write bursts -system.physmem.perBankRdBursts::1 23219 # Per bank write bursts -system.physmem.perBankRdBursts::2 23515 # Per bank write bursts -system.physmem.perBankRdBursts::3 24536 # Per bank write bursts -system.physmem.perBankRdBursts::4 25458 # Per bank write bursts -system.physmem.perBankRdBursts::5 23589 # Per bank write bursts -system.physmem.perBankRdBursts::6 23674 # Per bank write bursts -system.physmem.perBankRdBursts::7 23973 # Per bank write bursts -system.physmem.perBankRdBursts::8 23176 # Per bank write bursts -system.physmem.perBankRdBursts::9 23944 # Per bank write bursts -system.physmem.perBankRdBursts::10 24674 # Per bank write bursts -system.physmem.perBankRdBursts::11 22747 # Per bank write bursts -system.physmem.perBankRdBursts::12 23719 # Per bank write bursts -system.physmem.perBankRdBursts::13 24413 # Per bank write bursts -system.physmem.perBankRdBursts::14 22804 # Per bank write bursts -system.physmem.perBankRdBursts::15 22464 # Per bank write bursts +system.physmem.perBankRdBursts::0 23736 # Per bank write bursts +system.physmem.perBankRdBursts::1 23216 # Per bank write bursts +system.physmem.perBankRdBursts::2 23510 # Per bank write bursts +system.physmem.perBankRdBursts::3 24529 # Per bank write bursts +system.physmem.perBankRdBursts::4 25457 # Per bank write bursts +system.physmem.perBankRdBursts::5 23594 # Per bank write bursts +system.physmem.perBankRdBursts::6 23677 # Per bank write bursts +system.physmem.perBankRdBursts::7 23981 # Per bank write bursts +system.physmem.perBankRdBursts::8 23173 # Per bank write bursts +system.physmem.perBankRdBursts::9 23945 # Per bank write bursts +system.physmem.perBankRdBursts::10 24675 # Per bank write bursts +system.physmem.perBankRdBursts::11 22741 # Per bank write bursts +system.physmem.perBankRdBursts::12 23723 # Per bank write bursts +system.physmem.perBankRdBursts::13 24409 # Per bank write bursts +system.physmem.perBankRdBursts::14 22807 # Per bank write bursts +system.physmem.perBankRdBursts::15 22468 # Per bank write bursts system.physmem.perBankWrBursts::0 17754 # Per bank write bursts system.physmem.perBankWrBursts::1 17431 # Per bank write bursts -system.physmem.perBankWrBursts::2 17902 # Per bank write bursts +system.physmem.perBankWrBursts::2 17901 # Per bank write bursts system.physmem.perBankWrBursts::3 18773 # Per bank write bursts system.physmem.perBankWrBursts::4 19442 # Per bank write bursts system.physmem.perBankWrBursts::5 18543 # Per bank write bursts -system.physmem.perBankWrBursts::6 18682 # Per bank write bursts -system.physmem.perBankWrBursts::7 18577 # Per bank write bursts -system.physmem.perBankWrBursts::8 18349 # Per bank write bursts +system.physmem.perBankWrBursts::6 18677 # Per bank write bursts +system.physmem.perBankWrBursts::7 18574 # Per bank write bursts +system.physmem.perBankWrBursts::8 18352 # Per bank write bursts system.physmem.perBankWrBursts::9 18833 # Per bank write bursts system.physmem.perBankWrBursts::10 19127 # Per bank write bursts -system.physmem.perBankWrBursts::11 17965 # Per bank write bursts +system.physmem.perBankWrBursts::11 17966 # Per bank write bursts system.physmem.perBankWrBursts::12 18224 # Per bank write bursts -system.physmem.perBankWrBursts::13 18693 # Per bank write bursts +system.physmem.perBankWrBursts::13 18695 # Per bank write bursts system.physmem.perBankWrBursts::14 17148 # Per bank write bursts system.physmem.perBankWrBursts::15 17103 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 411002929500 # Total gap between requests +system.physmem.totGap 410940401000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 380005 # Read request sizes (log2) +system.physmem.readPktSize::6 380009 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 292570 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 378255 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1372 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 15 # What read queue length does an incoming req see +system.physmem.writePktSize::6 292569 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 378252 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1375 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 14 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -140,42 +140,42 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6816 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 7319 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 16971 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 17338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 17419 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 17420 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17397 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17408 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17383 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 17404 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 17430 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 17388 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 17507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 17464 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 17400 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17577 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17388 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 32 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6958 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 7441 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 16889 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 17304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 17388 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 17416 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17420 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17393 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17392 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 17410 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 17400 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 17408 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 17492 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 17470 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 17454 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17578 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17334 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17286 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see @@ -189,123 +189,126 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 141657 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 303.679790 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 179.908631 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 325.510648 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 50805 35.86% 35.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 38362 27.08% 62.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 12861 9.08% 72.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 8208 5.79% 77.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 5905 4.17% 81.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3832 2.71% 84.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2875 2.03% 86.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2523 1.78% 88.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 16286 11.50% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 141657 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17265 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 21.988184 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 229.046433 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 17255 99.94% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 6 0.03% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 3 0.02% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 142331 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 302.240383 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 178.797095 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 325.472154 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 51326 36.06% 36.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 38738 27.22% 63.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 13057 9.17% 72.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7891 5.54% 78.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 5698 4.00% 82.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3672 2.58% 84.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3107 2.18% 86.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2648 1.86% 88.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 16194 11.38% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 142331 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17261 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 21.992932 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 228.052387 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 17249 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 9 0.05% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 2 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::28672-29695 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17265 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17265 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.944454 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.865388 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 3.133478 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 17065 98.84% 98.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 148 0.86% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 28 0.16% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 9 0.05% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 2 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 3 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 1 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 2 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 1 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::236-239 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17265 # Writes before turning the bus around for reads -system.physmem.totQLat 4080991250 # Total ticks spent queuing -system.physmem.totMemAccLat 11199278750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1898210000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10749.58 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 17261 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17261 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.948207 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.879580 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.601828 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 17058 98.82% 98.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 154 0.89% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 25 0.14% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 10 0.06% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 4 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 2 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 1 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 2 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::220-223 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 17261 # Writes before turning the bus around for reads +system.physmem.totQLat 4019056000 # Total ticks spent queuing +system.physmem.totMemAccLat 11137324750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1898205000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10586.46 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29499.58 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 59.12 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 45.55 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 59.17 # Average system read bandwidth in MiByte/s +system.physmem.avgMemAccLat 29336.46 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 59.13 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 45.56 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 59.18 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 45.56 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.82 # Data bus utilization in percentage system.physmem.busUtilRead 0.46 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.36 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 20.64 # Average write queue length when enqueuing -system.physmem.readRowHits 314689 # Number of row buffer hits during reads -system.physmem.writeRowHits 215833 # Number of row buffer hits during writes +system.physmem.avgWrQLen 20.74 # Average write queue length when enqueuing +system.physmem.readRowHits 314673 # Number of row buffer hits during reads +system.physmem.writeRowHits 215171 # Number of row buffer hits during writes system.physmem.readRowHitRate 82.89 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.77 # Row buffer hit rate for writes -system.physmem.avgGap 611088.62 # Average gap between requests -system.physmem.pageHitRate 78.92 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 276203849000 # Time in different power states -system.physmem.memoryStateTime::REF 13724100000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 121069531000 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 545847120 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 524837880 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 297833250 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 286369875 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 1495111800 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 1465471800 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 953117280 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 942373440 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 26844339600 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 26844339600 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 61600136265 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 58531832820 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 192563272500 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 195254766750 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 284299657815 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 283849992165 # Total energy per rank (pJ) -system.physmem.averagePower::0 691.730926 # Core power per rank (mW) -system.physmem.averagePower::1 690.636842 # Core power per rank (mW) -system.cpu.branchPred.lookups 124266527 # Number of BP lookups -system.cpu.branchPred.condPredicted 87927203 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6406168 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 71920312 # Number of BTB lookups -system.cpu.branchPred.BTBHits 67440384 # Number of BTB hits +system.physmem.writeRowHitRate 73.55 # Row buffer hit rate for writes +system.physmem.avgGap 610992.93 # Average gap between requests +system.physmem.pageHitRate 78.82 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 547495200 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 298732500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1495119600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 953078400 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 26840271120 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 61546767165 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 192572713500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 284254177485 # Total energy per rank (pJ) +system.physmem_0.averagePower 691.725104 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 319820574750 # Time in different power states +system.physmem_0.memoryStateTime::REF 13722020000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 77392866750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 528262560 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 288238500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1465495200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 942392880 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 26840271120 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 58539586815 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 195210595500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 283814842575 # Total energy per rank (pJ) +system.physmem_1.averagePower 690.655981 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 324225356250 # Time in different power states +system.physmem_1.memoryStateTime::REF 13722020000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 72987820500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 124267347 # Number of BP lookups +system.cpu.branchPred.condPredicted 87926966 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6405633 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 71910290 # Number of BTB lookups +system.cpu.branchPred.BTBHits 67438494 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 93.770984 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 15061672 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1126459 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 93.781424 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 15062581 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1126311 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 149394307 # DTB read hits -system.cpu.dtb.read_misses 568771 # DTB read misses +system.cpu.dtb.read_hits 149395037 # DTB read hits +system.cpu.dtb.read_misses 569044 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 149963078 # DTB read accesses -system.cpu.dtb.write_hits 57322555 # DTB write hits -system.cpu.dtb.write_misses 67010 # DTB write misses +system.cpu.dtb.read_accesses 149964081 # DTB read accesses +system.cpu.dtb.write_hits 57322306 # DTB write hits +system.cpu.dtb.write_misses 67257 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 57389565 # DTB write accesses -system.cpu.dtb.data_hits 206716862 # DTB hits -system.cpu.dtb.data_misses 635781 # DTB misses +system.cpu.dtb.write_accesses 57389563 # DTB write accesses +system.cpu.dtb.data_hits 206717343 # DTB hits +system.cpu.dtb.data_misses 636301 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 207352643 # DTB accesses -system.cpu.itb.fetch_hits 226799477 # ITB hits +system.cpu.dtb.data_accesses 207353644 # DTB accesses +system.cpu.itb.fetch_hits 226796884 # ITB hits system.cpu.itb.fetch_misses 48 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 226799525 # ITB accesses +system.cpu.itb.fetch_accesses 226796932 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -319,66 +322,66 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 485 # Number of system calls -system.cpu.numCycles 822006022 # number of cpu cycles simulated +system.cpu.numCycles 821880966 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 611901617 # Number of instructions committed system.cpu.committedOps 611901617 # Number of ops (including micro ops) committed -system.cpu.discardedOps 12977706 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 12979255 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.343363 # CPI: cycles per instruction -system.cpu.ipc 0.744400 # IPC: instructions per cycle -system.cpu.tickCycles 741717254 # Number of cycles that the object actually ticked -system.cpu.idleCycles 80288768 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 2535461 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.779511 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 202630719 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2539557 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 79.789790 # Average number of references to valid blocks. +system.cpu.cpi 1.343159 # CPI: cycles per instruction +system.cpu.ipc 0.744514 # IPC: instructions per cycle +system.cpu.tickCycles 741712966 # Number of cycles that the object actually ticked +system.cpu.idleCycles 80168000 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 2535450 # number of replacements +system.cpu.dcache.tags.tagsinuse 4087.778260 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 202631199 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2539546 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 79.790324 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 1608227250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 4087.779511 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.inst 4087.778260 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.inst 0.997993 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.997993 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 68 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 830 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3144 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 69 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 829 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3145 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 414705281 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 414705281 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 146964513 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 146964513 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 55666206 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 55666206 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.inst 202630719 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 202630719 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 202630719 # number of overall hits -system.cpu.dcache.overall_hits::total 202630719 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 1908315 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1908315 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 1543828 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1543828 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.inst 3452143 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3452143 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 3452143 # number of overall misses -system.cpu.dcache.overall_misses::total 3452143 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 36427451000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 36427451000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 45003472500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 45003472500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 81430923500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 81430923500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 81430923500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 81430923500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 148872828 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 148872828 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 414706244 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 414706244 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 146964985 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 146964985 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.inst 55666214 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 55666214 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.inst 202631199 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 202631199 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.inst 202631199 # number of overall hits +system.cpu.dcache.overall_hits::total 202631199 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.inst 1908330 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1908330 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.inst 1543820 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1543820 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.inst 3452150 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3452150 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.inst 3452150 # number of overall misses +system.cpu.dcache.overall_misses::total 3452150 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 36414832750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 36414832750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 44905898000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 44905898000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 81320730750 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 81320730750 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 81320730750 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 81320730750 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.inst 148873315 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 148873315 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.inst 57210034 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 57210034 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 206082862 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 206082862 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 206082862 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 206082862 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.inst 206083349 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 206083349 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 206083349 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 206083349 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.012818 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.012818 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.026985 # miss rate for WriteReq accesses @@ -387,14 +390,14 @@ system.cpu.dcache.demand_miss_rate::cpu.inst 0.016751 system.cpu.dcache.demand_miss_rate::total 0.016751 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.inst 0.016751 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.016751 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 19088.803997 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 19088.803997 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 29150.574092 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 29150.574092 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 23588.514004 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 23588.514004 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 23588.514004 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 23588.514004 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 19082.041759 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 19082.041759 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 29087.521861 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 29087.521861 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 23556.546138 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23556.546138 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 23556.546138 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 23556.546138 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -403,32 +406,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2340066 # number of writebacks -system.cpu.dcache.writebacks::total 2340066 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 143549 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 143549 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 769037 # 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number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 2544567 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2544567 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 2544567 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2544567 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.098154 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.098154 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.265541 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.265541 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.149340 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.149340 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.149340 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.149340 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73163.045484 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 73163.045484 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 71470.302768 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71470.302768 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72242.619834 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 72242.619834 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72242.619834 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 72242.619834 # average overall miss latency +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.149341 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.149341 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.149341 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.149341 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73089.081686 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 73089.081686 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 71230.793801 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71230.793801 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72078.656690 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 72078.656690 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72078.656690 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 72078.656690 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -613,93 +616,93 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 292570 # number of writebacks -system.cpu.l2cache.writebacks::total 292570 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 173378 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 173378 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 206627 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 206627 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 380005 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 380005 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 380005 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 380005 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10473281000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 10473281000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 12138501750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12138501750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22611782750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 22611782750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22611782750 # 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number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 380009 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10460839250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 10460839250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 12089060000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12089060000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22549899250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 22549899250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22549899250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 22549899250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.098154 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.098154 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.265541 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.265541 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.149340 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.149340 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.149340 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.149340 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60407.208527 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60407.208527 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 58745.961322 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58745.961322 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59503.908501 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59503.908501 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59503.908501 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59503.908501 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.149341 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.149341 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.149341 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.149341 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60333.707745 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60333.707745 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 58506.964274 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58506.964274 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59340.434700 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59340.434700 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59340.434700 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59340.434700 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 1766429 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1766429 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2340066 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 778137 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 778137 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10018 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7419180 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7429198 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 320576 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312295872 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 312616448 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 1766435 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1766435 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2340060 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 778132 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 778132 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10042 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7419152 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7429194 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 321344 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312294784 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 312616128 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 4884632 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 4884627 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 4884632 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 4884627 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4884632 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4782382000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 4884627 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4782373500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 8065750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 8080250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3891670500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3891629500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.membus.trans_dist::ReadReq 173378 # Transaction distribution -system.membus.trans_dist::ReadResp 173378 # Transaction distribution -system.membus.trans_dist::Writeback 292570 # Transaction distribution -system.membus.trans_dist::ReadExReq 206627 # Transaction distribution -system.membus.trans_dist::ReadExResp 206627 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1052580 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1052580 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43044800 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 43044800 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 173383 # Transaction distribution +system.membus.trans_dist::ReadResp 173383 # Transaction distribution +system.membus.trans_dist::Writeback 292569 # Transaction distribution +system.membus.trans_dist::ReadExReq 206626 # Transaction distribution +system.membus.trans_dist::ReadExResp 206626 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1052587 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1052587 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43044992 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 43044992 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 672575 # Request fanout histogram +system.membus.snoop_fanout::samples 672578 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 672575 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 672578 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 672575 # Request fanout histogram -system.membus.reqLayer0.occupancy 3222733000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 672578 # Request fanout histogram +system.membus.reqLayer0.occupancy 3222626500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 3617871750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3617752750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.9 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt index 940b25691..a1fa65b86 100644 --- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt @@ -1,101 +1,101 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.365348 # Number of seconds simulated -sim_ticks 365347511000 # Number of ticks simulated -final_tick 365347511000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.365317 # Number of seconds simulated +sim_ticks 365317233000 # Number of ticks simulated +final_tick 365317233000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 224796 # Simulator instruction rate (inst/s) -host_op_rate 243484 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 162123009 # Simulator tick rate (ticks/s) -host_mem_usage 256924 # Number of bytes of host memory used -host_seconds 2253.52 # Real time elapsed on the host +host_inst_rate 241300 # Simulator instruction rate (inst/s) +host_op_rate 261360 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 174011250 # Simulator tick rate (ticks/s) +host_mem_usage 315696 # Number of bytes of host memory used +host_seconds 2099.39 # Real time elapsed on the host sim_insts 506582155 # Number of instructions simulated sim_ops 548695378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 9224896 # Number of bytes read from this memory -system.physmem.bytes_read::total 9224896 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 221312 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 221312 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6179008 # Number of bytes written to this memory -system.physmem.bytes_written::total 6179008 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 144139 # Number of read requests responded to by this memory -system.physmem.num_reads::total 144139 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 96547 # Number of write requests responded to by this memory -system.physmem.num_writes::total 96547 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 25249648 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 25249648 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 605758 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 605758 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 16912687 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 16912687 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 16912687 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 25249648 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 42162335 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 144139 # Number of read requests accepted -system.physmem.writeReqs 96547 # Number of write requests accepted -system.physmem.readBursts 144139 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 96547 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9218048 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6848 # Total number of bytes read from write queue -system.physmem.bytesWritten 6177856 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9224896 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6179008 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 107 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 9226048 # Number of bytes read from this memory +system.physmem.bytes_read::total 9226048 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 222144 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 222144 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6179904 # Number of bytes written to this memory +system.physmem.bytes_written::total 6179904 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 144157 # Number of read requests responded to by this memory +system.physmem.num_reads::total 144157 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 96561 # Number of write requests responded to by this memory +system.physmem.num_writes::total 96561 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 25254894 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 25254894 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 608085 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 608085 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 16916541 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 16916541 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 16916541 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 25254894 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 42171435 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 144157 # Number of read requests accepted +system.physmem.writeReqs 96561 # Number of write requests accepted +system.physmem.readBursts 144157 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 96561 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9219904 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6144 # Total number of bytes read from write queue +system.physmem.bytesWritten 6178688 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9226048 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6179904 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 96 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9344 # Per bank write bursts -system.physmem.perBankRdBursts::1 8969 # Per bank write bursts +system.physmem.perBankRdBursts::0 9347 # Per bank write bursts +system.physmem.perBankRdBursts::1 8970 # Per bank write bursts system.physmem.perBankRdBursts::2 8998 # Per bank write bursts -system.physmem.perBankRdBursts::3 8704 # Per bank write bursts -system.physmem.perBankRdBursts::4 9453 # Per bank write bursts -system.physmem.perBankRdBursts::5 9341 # Per bank write bursts -system.physmem.perBankRdBursts::6 8940 # Per bank write bursts +system.physmem.perBankRdBursts::3 8695 # Per bank write bursts +system.physmem.perBankRdBursts::4 9455 # Per bank write bursts +system.physmem.perBankRdBursts::5 9342 # Per bank write bursts +system.physmem.perBankRdBursts::6 8947 # Per bank write bursts system.physmem.perBankRdBursts::7 8101 # Per bank write bursts -system.physmem.perBankRdBursts::8 8571 # Per bank write bursts -system.physmem.perBankRdBursts::9 8677 # Per bank write bursts -system.physmem.perBankRdBursts::10 8772 # Per bank write bursts -system.physmem.perBankRdBursts::11 9476 # Per bank write bursts -system.physmem.perBankRdBursts::12 9379 # Per bank write bursts -system.physmem.perBankRdBursts::13 9523 # Per bank write bursts -system.physmem.perBankRdBursts::14 8710 # Per bank write bursts -system.physmem.perBankRdBursts::15 9074 # Per bank write bursts -system.physmem.perBankWrBursts::0 6191 # Per bank write bursts -system.physmem.perBankWrBursts::1 6093 # Per bank write bursts +system.physmem.perBankRdBursts::8 8578 # Per bank write bursts +system.physmem.perBankRdBursts::9 8679 # Per bank write bursts +system.physmem.perBankRdBursts::10 8774 # Per bank write bursts +system.physmem.perBankRdBursts::11 9477 # Per bank write bursts +system.physmem.perBankRdBursts::12 9374 # Per bank write bursts +system.physmem.perBankRdBursts::13 9525 # Per bank write bursts +system.physmem.perBankRdBursts::14 8712 # Per bank write bursts +system.physmem.perBankRdBursts::15 9087 # Per bank write bursts +system.physmem.perBankWrBursts::0 6196 # Per bank write bursts +system.physmem.perBankWrBursts::1 6092 # Per bank write bursts system.physmem.perBankWrBursts::2 6006 # Per bank write bursts -system.physmem.perBankWrBursts::3 5817 # Per bank write bursts -system.physmem.perBankWrBursts::4 6161 # Per bank write bursts -system.physmem.perBankWrBursts::5 6171 # Per bank write bursts -system.physmem.perBankWrBursts::6 6013 # Per bank write bursts -system.physmem.perBankWrBursts::7 5494 # Per bank write bursts +system.physmem.perBankWrBursts::3 5813 # Per bank write bursts +system.physmem.perBankWrBursts::4 6163 # Per bank write bursts +system.physmem.perBankWrBursts::5 6172 # Per bank write bursts +system.physmem.perBankWrBursts::6 6014 # Per bank write bursts +system.physmem.perBankWrBursts::7 5493 # Per bank write bursts system.physmem.perBankWrBursts::8 5728 # Per bank write bursts -system.physmem.perBankWrBursts::9 5821 # Per bank write bursts -system.physmem.perBankWrBursts::10 5961 # Per bank write bursts -system.physmem.perBankWrBursts::11 6446 # Per bank write bursts +system.physmem.perBankWrBursts::9 5823 # Per bank write bursts +system.physmem.perBankWrBursts::10 5962 # Per bank write bursts +system.physmem.perBankWrBursts::11 6445 # Per bank write bursts system.physmem.perBankWrBursts::12 6308 # Per bank write bursts -system.physmem.perBankWrBursts::13 6280 # Per bank write bursts -system.physmem.perBankWrBursts::14 5994 # Per bank write bursts -system.physmem.perBankWrBursts::15 6045 # Per bank write bursts +system.physmem.perBankWrBursts::13 6282 # Per bank write bursts +system.physmem.perBankWrBursts::14 5997 # Per bank write bursts +system.physmem.perBankWrBursts::15 6048 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 365347483000 # Total gap between requests +system.physmem.totGap 365317203500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 144139 # Read request sizes (log2) +system.physmem.readPktSize::6 144157 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 96547 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 143660 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 351 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 21 # What read queue length does an incoming req see +system.physmem.writePktSize::6 96561 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 143694 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 347 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 20 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -140,37 +140,37 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5536 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5682 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5670 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5682 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5668 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5678 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5702 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5684 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5698 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5672 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5626 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5628 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5584 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2939 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5543 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5664 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5670 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5672 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5680 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5680 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5691 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5692 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5666 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5669 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5692 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5677 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5633 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5643 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5596 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5580 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see @@ -189,98 +189,119 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 64866 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 237.344433 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 157.101707 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 243.291878 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 24488 37.75% 37.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18300 28.21% 65.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6859 10.57% 76.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7791 12.01% 88.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2064 3.18% 91.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1161 1.79% 93.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 764 1.18% 94.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 681 1.05% 95.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 2758 4.25% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 64866 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5569 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 25.862992 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 382.285392 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 5565 99.93% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 3 0.05% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 65080 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 236.601352 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 156.588709 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 242.751381 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 24737 38.01% 38.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18138 27.87% 65.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6930 10.65% 76.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7871 12.09% 88.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2125 3.27% 91.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1134 1.74% 93.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 708 1.09% 94.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 644 0.99% 95.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 2793 4.29% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 65080 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5572 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 25.854092 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 382.114973 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 5569 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 2 0.04% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5569 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5569 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.333273 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.210704 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 3.188900 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5418 97.29% 97.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 79 1.42% 98.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 23 0.41% 99.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 20 0.36% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 9 0.16% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 7 0.13% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 5 0.09% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 5 0.09% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 1 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5569 # Writes before turning the bus around for reads -system.physmem.totQLat 1570268250 # Total ticks spent queuing -system.physmem.totMemAccLat 4270868250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 720160000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10902.22 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5572 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5572 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.326274 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.230410 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.286782 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-17 2628 47.16% 47.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18-19 2789 50.05% 97.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-21 53 0.95% 98.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22-23 30 0.54% 98.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-25 23 0.41% 99.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26-27 9 0.16% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-29 9 0.16% 99.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30-31 6 0.11% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-33 7 0.13% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34-35 3 0.05% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-37 1 0.02% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::38-39 4 0.07% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-41 1 0.02% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42-43 2 0.04% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-45 2 0.04% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::46-47 2 0.04% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::54-55 1 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::70-71 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::78-79 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5572 # Writes before turning the bus around for reads +system.physmem.totQLat 1534207250 # Total ticks spent queuing +system.physmem.totMemAccLat 4235351000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 720305000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10649.71 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29652.22 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 25.23 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 29399.71 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 25.24 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 16.91 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 25.25 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 16.91 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 16.92 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.33 # Data bus utilization in percentage system.physmem.busUtilRead 0.20 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.13 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 19.86 # Average write queue length when enqueuing -system.physmem.readRowHits 110988 # Number of row buffer hits during reads -system.physmem.writeRowHits 64704 # Number of row buffer hits during writes +system.physmem.avgWrQLen 20.29 # Average write queue length when enqueuing +system.physmem.readRowHits 111019 # Number of row buffer hits during reads +system.physmem.writeRowHits 64498 # Number of row buffer hits during writes system.physmem.readRowHitRate 77.06 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 67.02 # Row buffer hit rate for writes -system.physmem.avgGap 1517942.39 # Average gap between requests -system.physmem.pageHitRate 73.03 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 256543365500 # Time in different power states -system.physmem.memoryStateTime::REF 12199720000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 96603610750 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 246584520 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 243719280 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 134545125 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 132981750 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 560422200 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 562972800 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 310625280 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 314778960 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 23862652320 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 23862652320 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 47112370740 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 46678345380 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 177881368500 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 178262092500 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 250108568685 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 250057542990 # Total energy per rank (pJ) -system.physmem.averagePower::0 684.578732 # Core power per rank (mW) -system.physmem.averagePower::1 684.439068 # Core power per rank (mW) -system.cpu.branchPred.lookups 132580026 # Number of BP lookups -system.cpu.branchPred.condPredicted 98506360 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6554090 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 69003825 # Number of BTB lookups -system.cpu.branchPred.BTBHits 64853184 # Number of BTB hits +system.physmem.writeRowHitRate 66.80 # Row buffer hit rate for writes +system.physmem.avgGap 1517614.82 # Average gap between requests +system.physmem.pageHitRate 72.94 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 247892400 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 135258750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 560445600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 310566960 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 23860618080 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 47138982615 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 177839337750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 250093102155 # Total energy per rank (pJ) +system.physmem_0.averagePower 684.594758 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 295545266000 # Time in different power states +system.physmem_0.memoryStateTime::REF 12198680000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 57571800000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 244014120 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 133142625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 563058600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 314817840 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 23860618080 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 46734210225 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 178194401250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 250044262740 # Total energy per rank (pJ) +system.physmem_1.averagePower 684.461067 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 296138902500 # Time in different power states +system.physmem_1.memoryStateTime::REF 12198680000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 56977968750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 132578917 # Number of BP lookups +system.cpu.branchPred.condPredicted 98507789 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6555100 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 69037584 # Number of BTB lookups +system.cpu.branchPred.BTBHits 64855119 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 93.984912 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 10016062 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 17737 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 93.941756 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 10014942 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 17500 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -302,6 +323,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -323,6 +352,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -344,6 +381,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -366,90 +411,90 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 730695022 # number of cpu cycles simulated +system.cpu.numCycles 730634466 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 506582155 # Number of instructions committed system.cpu.committedOps 548695378 # Number of ops (including micro ops) committed -system.cpu.discardedOps 13461717 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 13461155 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.442402 # CPI: cycles per instruction -system.cpu.ipc 0.693288 # IPC: instructions per cycle -system.cpu.tickCycles 695775254 # Number of cycles that the object actually ticked -system.cpu.idleCycles 34919768 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 1139848 # number of replacements -system.cpu.dcache.tags.tagsinuse 4071.076883 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 171283127 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1143944 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 149.730343 # Average number of references to valid blocks. +system.cpu.cpi 1.442282 # CPI: cycles per instruction +system.cpu.ipc 0.693346 # IPC: instructions per cycle +system.cpu.tickCycles 695780172 # Number of cycles that the object actually ticked +system.cpu.idleCycles 34854294 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 1139812 # number of replacements +system.cpu.dcache.tags.tagsinuse 4071.074819 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 171281876 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1143908 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 149.733961 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 4867376000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 4071.076883 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.inst 4071.074819 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.inst 0.993915 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.993915 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 550 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3502 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 545 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3506 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 346820764 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 346820764 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 114767369 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 114767369 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 53538676 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 53538676 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 346818362 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 346818362 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 114766084 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114766084 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.inst 53538710 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 53538710 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.inst 1488541 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.inst 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.inst 168306045 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168306045 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 168306045 # number of overall hits -system.cpu.dcache.overall_hits::total 168306045 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 854653 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 854653 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 700630 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 700630 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.inst 1555283 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1555283 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 1555283 # number of overall misses -system.cpu.dcache.overall_misses::total 1555283 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 13708895232 # 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average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 29383.216534 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 22051.072526 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22051.072526 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 22051.072526 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22051.072526 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.inst 0.009157 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009157 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.inst 0.009157 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009157 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 16036.677740 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16036.677740 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 29291.596369 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 29291.596369 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 22007.254782 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22007.254782 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 22007.254782 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22007.254782 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -458,103 +503,103 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1068569 # number of writebacks -system.cpu.dcache.writebacks::total 1068569 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 66869 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 66869 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 344470 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 344470 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 411339 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 411339 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 411339 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 411339 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 787784 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 787784 # 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number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 10073374750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10073374750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 21325403765 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 21325403765 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 21325403765 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 21325403765 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.006813 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006813 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.006566 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006566 # 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average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 18674.244119 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 18674.244119 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.006734 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006734 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.006734 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006734 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 14283.502439 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14283.502439 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 28284.555545 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28284.555545 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 18642.586436 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 18642.586436 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 18642.586436 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 18642.586436 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 17642 # number of replacements -system.cpu.icache.tags.tagsinuse 1190.521713 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 200940130 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 19514 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 10297.229169 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 17690 # 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number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 96547 # number of writebacks -system.cpu.l2cache.writebacks::total 96547 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 96561 # number of writebacks +system.cpu.l2cache.writebacks::total 96561 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 17 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::total 17 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 17 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 17 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 17 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 17 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 43270 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 43270 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 100869 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 100869 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 144139 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 144139 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 144139 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 144139 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 2682518500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2682518500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 5916082000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5916082000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8598600500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 8598600500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8598600500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 8598600500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.053615 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.053615 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.283012 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.283012 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.123888 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.123888 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.123888 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.123888 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61994.880980 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61994.880980 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 58651.141580 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58651.141580 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59654.919904 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59654.919904 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59654.919904 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59654.919904 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 43289 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 43289 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 100868 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 100868 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 144157 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 144157 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 144157 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 144157 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 2680290500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2680290500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 5883442250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5883442250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8563732750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 8563732750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8563732750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 8563732750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.053637 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.053637 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.283021 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.283021 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.123903 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.123903 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.123903 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.123903 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61916.202730 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61916.202730 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 58328.134294 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58328.134294 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59405.597716 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59405.597716 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59405.597716 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59405.597716 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 807045 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 807045 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1068569 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 356413 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 356413 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 39028 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3356457 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3395485 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1248896 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141600832 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 142849728 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 807073 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 807073 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1068525 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 356398 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 356398 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 39126 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3356341 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 3395467 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1252032 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141595712 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 142847744 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 2232027 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 2231996 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram @@ -729,41 +774,41 @@ system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Re system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 2232027 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 2231996 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2232027 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2184582500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2231996 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2184523000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 29960995 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 30038495 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1744681985 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1744651235 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.membus.trans_dist::ReadReq 43270 # Transaction distribution -system.membus.trans_dist::ReadResp 43270 # Transaction distribution -system.membus.trans_dist::Writeback 96547 # Transaction distribution -system.membus.trans_dist::ReadExReq 100869 # Transaction distribution -system.membus.trans_dist::ReadExResp 100869 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 384825 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 384825 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15403904 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 15403904 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 43289 # Transaction distribution +system.membus.trans_dist::ReadResp 43289 # Transaction distribution +system.membus.trans_dist::Writeback 96561 # Transaction distribution +system.membus.trans_dist::ReadExReq 100868 # Transaction distribution +system.membus.trans_dist::ReadExResp 100868 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 384875 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 384875 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15405952 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 15405952 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 240686 # Request fanout histogram +system.membus.snoop_fanout::samples 240718 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 240686 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 240718 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 240686 # Request fanout histogram -system.membus.reqLayer0.occupancy 1081853000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 240718 # Request fanout histogram +system.membus.reqLayer0.occupancy 1081999000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 1366563500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1366864750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index e3aeba90b..e36a9b419 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,122 +1,122 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.231519 # Number of seconds simulated -sim_ticks 231518815500 # Number of ticks simulated -final_tick 231518815500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.232212 # Number of seconds simulated +sim_ticks 232211555000 # Number of ticks simulated +final_tick 232211555000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 137569 # Simulator instruction rate (inst/s) -host_op_rate 149036 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 63039200 # Simulator tick rate (ticks/s) -host_mem_usage 324016 # Number of bytes of host memory used -host_seconds 3672.62 # Real time elapsed on the host +host_inst_rate 135087 # Simulator instruction rate (inst/s) +host_op_rate 146347 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 62087234 # Simulator tick rate (ticks/s) +host_mem_usage 317808 # Number of bytes of host memory used +host_seconds 3740.09 # Real time elapsed on the host sim_insts 505237723 # Number of instructions simulated sim_ops 547350944 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 135488 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8576576 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 19999488 # Number of bytes read from this memory -system.physmem.bytes_read::total 28711552 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 135488 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 135488 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 19446336 # Number of bytes written to this memory -system.physmem.bytes_written::total 19446336 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2117 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 134009 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 312492 # Number of read requests responded to by this memory -system.physmem.num_reads::total 448618 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 303849 # Number of write requests responded to by this memory -system.physmem.num_writes::total 303849 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 585214 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 37044834 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 86383856 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 124013903 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 585214 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 585214 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 83994625 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 83994625 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 83994625 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 585214 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 37044834 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 86383856 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 208008528 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 448618 # Number of read requests accepted -system.physmem.writeReqs 303849 # Number of write requests accepted -system.physmem.readBursts 448618 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 303849 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 28559360 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 152192 # Total number of bytes read from write queue -system.physmem.bytesWritten 19444544 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 28711552 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 19446336 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 2378 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 681088 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9254400 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 16474624 # Number of bytes read from this memory +system.physmem.bytes_read::total 26410112 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 681088 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 681088 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18728832 # Number of bytes written to this memory +system.physmem.bytes_written::total 18728832 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 10642 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 144600 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 257416 # Number of read requests responded to by this memory +system.physmem.num_reads::total 412658 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 292638 # Number of write requests responded to by this memory +system.physmem.num_writes::total 292638 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 2933050 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 39853314 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 70946616 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 113732979 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2933050 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2933050 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 80654178 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 80654178 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 80654178 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2933050 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 39853314 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 70946616 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 194387157 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 412658 # Number of read requests accepted +system.physmem.writeReqs 292638 # Number of write requests accepted +system.physmem.readBursts 412658 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 292638 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26271168 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 138944 # Total number of bytes read from write queue +system.physmem.bytesWritten 18727424 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26410112 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18728832 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 2171 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 4 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 28534 # Per bank write bursts -system.physmem.perBankRdBursts::1 27313 # Per bank write bursts -system.physmem.perBankRdBursts::2 27956 # Per bank write bursts -system.physmem.perBankRdBursts::3 26702 # Per bank write bursts -system.physmem.perBankRdBursts::4 30075 # Per bank write bursts -system.physmem.perBankRdBursts::5 29207 # Per bank write bursts -system.physmem.perBankRdBursts::6 27700 # Per bank write bursts -system.physmem.perBankRdBursts::7 26438 # Per bank write bursts -system.physmem.perBankRdBursts::8 28442 # Per bank write bursts -system.physmem.perBankRdBursts::9 26796 # Per bank write bursts -system.physmem.perBankRdBursts::10 28037 # Per bank write bursts -system.physmem.perBankRdBursts::11 28667 # Per bank write bursts -system.physmem.perBankRdBursts::12 28663 # Per bank write bursts -system.physmem.perBankRdBursts::13 27984 # Per bank write bursts -system.physmem.perBankRdBursts::14 26659 # Per bank write bursts -system.physmem.perBankRdBursts::15 27067 # Per bank write bursts -system.physmem.perBankWrBursts::0 19504 # Per bank write bursts -system.physmem.perBankWrBursts::1 19011 # Per bank write bursts -system.physmem.perBankWrBursts::2 18881 # Per bank write bursts -system.physmem.perBankWrBursts::3 18629 # Per bank write bursts -system.physmem.perBankWrBursts::4 19556 # Per bank write bursts -system.physmem.perBankWrBursts::5 19014 # Per bank write bursts -system.physmem.perBankWrBursts::6 18738 # Per bank write bursts -system.physmem.perBankWrBursts::7 18227 # Per bank write bursts -system.physmem.perBankWrBursts::8 18808 # Per bank write bursts -system.physmem.perBankWrBursts::9 18381 # Per bank write bursts -system.physmem.perBankWrBursts::10 19036 # Per bank write bursts -system.physmem.perBankWrBursts::11 19525 # Per bank write bursts -system.physmem.perBankWrBursts::12 19578 # Per bank write bursts -system.physmem.perBankWrBursts::13 19080 # Per bank write bursts -system.physmem.perBankWrBursts::14 18969 # Per bank write bursts -system.physmem.perBankWrBursts::15 18884 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 3 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 26576 # Per bank write bursts +system.physmem.perBankRdBursts::1 25575 # Per bank write bursts +system.physmem.perBankRdBursts::2 25174 # Per bank write bursts +system.physmem.perBankRdBursts::3 24876 # Per bank write bursts +system.physmem.perBankRdBursts::4 27202 # Per bank write bursts +system.physmem.perBankRdBursts::5 26589 # Per bank write bursts +system.physmem.perBankRdBursts::6 25428 # Per bank write bursts +system.physmem.perBankRdBursts::7 24234 # Per bank write bursts +system.physmem.perBankRdBursts::8 25846 # Per bank write bursts +system.physmem.perBankRdBursts::9 24812 # Per bank write bursts +system.physmem.perBankRdBursts::10 25055 # Per bank write bursts +system.physmem.perBankRdBursts::11 26081 # Per bank write bursts +system.physmem.perBankRdBursts::12 26502 # Per bank write bursts +system.physmem.perBankRdBursts::13 25872 # Per bank write bursts +system.physmem.perBankRdBursts::14 25198 # Per bank write bursts +system.physmem.perBankRdBursts::15 25467 # Per bank write bursts +system.physmem.perBankWrBursts::0 18795 # Per bank write bursts +system.physmem.perBankWrBursts::1 18343 # Per bank write bursts +system.physmem.perBankWrBursts::2 17877 # Per bank write bursts +system.physmem.perBankWrBursts::3 18076 # Per bank write bursts +system.physmem.perBankWrBursts::4 18802 # Per bank write bursts +system.physmem.perBankWrBursts::5 18306 # Per bank write bursts +system.physmem.perBankWrBursts::6 18071 # Per bank write bursts +system.physmem.perBankWrBursts::7 17638 # Per bank write bursts +system.physmem.perBankWrBursts::8 18138 # Per bank write bursts +system.physmem.perBankWrBursts::9 17849 # Per bank write bursts +system.physmem.perBankWrBursts::10 18079 # Per bank write bursts +system.physmem.perBankWrBursts::11 18708 # Per bank write bursts +system.physmem.perBankWrBursts::12 18879 # Per bank write bursts +system.physmem.perBankWrBursts::13 18261 # Per bank write bursts +system.physmem.perBankWrBursts::14 18465 # Per bank write bursts +system.physmem.perBankWrBursts::15 18329 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 231518762500 # Total gap between requests +system.physmem.totGap 232211534500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 448618 # Read request sizes (log2) +system.physmem.readPktSize::6 412658 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 303849 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 313690 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 58469 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 20239 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 14456 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 11242 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 9068 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 7428 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 5977 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 4478 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 482 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 255 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 186 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 111 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 72 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 52 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 35 # What read queue length does an incoming req see +system.physmem.writePktSize::6 292638 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 311514 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 49355 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 13370 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9258 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7406 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 6188 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 5306 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4451 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3459 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 94 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 41 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see @@ -148,34 +148,34 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6491 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 6765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 13373 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 15569 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 16671 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 17312 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17994 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 18306 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 18710 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 19076 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 19692 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 20196 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 21097 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 19275 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 18805 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 18387 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 18184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 48 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6204 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6468 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 13583 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 15531 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 16421 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 16883 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17156 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17339 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17608 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 17806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 18103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 18634 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 19068 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 19781 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 18496 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 18131 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17723 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17546 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 85 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see @@ -197,125 +197,111 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 319369 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 150.306987 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 104.535813 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 187.171349 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 189945 59.48% 59.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 84511 26.46% 85.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 17715 5.55% 91.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 8285 2.59% 94.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 5483 1.72% 95.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2730 0.85% 96.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1944 0.61% 97.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1733 0.54% 97.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7023 2.20% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 319369 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17997 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 24.795133 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 115.387055 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 17996 99.99% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::15360-15871 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17997 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17997 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.881758 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.836627 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.284458 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 11076 61.54% 61.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 293 1.63% 63.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 5463 30.36% 93.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 684 3.80% 97.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 201 1.12% 98.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 109 0.61% 99.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 62 0.34% 99.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 46 0.26% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 32 0.18% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 17 0.09% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 10 0.06% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 2 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 2 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17997 # Writes before turning the bus around for reads -system.physmem.totQLat 10651839911 # Total ticks spent queuing -system.physmem.totMemAccLat 19018839911 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2231200000 # Total ticks spent in databus transfers -system.physmem.avgQLat 23870.20 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 307877 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 146.155822 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 102.817953 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 181.897933 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 185209 60.16% 60.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 81919 26.61% 86.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 16650 5.41% 92.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7285 2.37% 94.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 4666 1.52% 96.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2373 0.77% 96.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1833 0.60% 97.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1570 0.51% 97.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6372 2.07% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 307877 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17388 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.607430 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 116.348412 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 17387 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14848-15359 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 17388 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17388 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.828617 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.789393 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.188635 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 10816 62.20% 62.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 278 1.60% 63.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 5484 31.54% 95.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 506 2.91% 98.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 126 0.72% 98.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 66 0.38% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 41 0.24% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 33 0.19% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 20 0.12% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 12 0.07% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 5 0.03% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 17388 # Writes before turning the bus around for reads +system.physmem.totQLat 9526506707 # Total ticks spent queuing +system.physmem.totMemAccLat 17223137957 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2052435000 # Total ticks spent in databus transfers +system.physmem.avgQLat 23207.82 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 42620.20 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 123.36 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 83.99 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 124.01 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 83.99 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 41957.82 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 113.13 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 80.65 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 113.73 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 80.65 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.62 # Data bus utilization in percentage -system.physmem.busUtilRead 0.96 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.66 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.28 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.96 # Average write queue length when enqueuing -system.physmem.readRowHits 331076 # Number of row buffer hits during reads -system.physmem.writeRowHits 99609 # Number of row buffer hits during writes -system.physmem.readRowHitRate 74.19 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 32.78 # Row buffer hit rate for writes -system.physmem.avgGap 307679.62 # Average gap between requests -system.physmem.pageHitRate 57.42 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 82440834065 # Time in different power states -system.physmem.memoryStateTime::REF 7730840000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 141344957185 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 1204270200 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 1209705840 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 657091875 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 660057750 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 1746123600 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 1733674800 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 981894960 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 986450400 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 15121523040 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 15121523040 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 75885673770 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 75815795475 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 72343590000 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 72404886750 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 167940167445 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 167932094055 # Total energy per rank (pJ) -system.physmem.averagePower::0 725.391418 # Core power per rank (mW) -system.physmem.averagePower::1 725.356546 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 445006 # Transaction distribution -system.membus.trans_dist::ReadResp 445005 # Transaction distribution -system.membus.trans_dist::Writeback 303849 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4 # Transaction distribution -system.membus.trans_dist::ReadExReq 3612 # Transaction distribution -system.membus.trans_dist::ReadExResp 3612 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1201092 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1201092 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 48157824 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 48157824 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 752471 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 752471 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 752471 # Request fanout histogram -system.membus.reqLayer0.occupancy 3332077149 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 4185038226 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 1.8 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 175071152 # Number of BP lookups -system.cpu.branchPred.condPredicted 131322715 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 7444793 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 90519847 # Number of BTB lookups -system.cpu.branchPred.BTBHits 83861329 # Number of BTB hits +system.physmem.busUtil 1.51 # Data bus utilization in percentage +system.physmem.busUtilRead 0.88 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.63 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.16 # Average read queue length when enqueuing +system.physmem.avgWrQLen 21.62 # Average write queue length when enqueuing +system.physmem.readRowHits 299737 # Number of row buffer hits during reads +system.physmem.writeRowHits 95481 # Number of row buffer hits during writes +system.physmem.readRowHitRate 73.02 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 32.63 # Row buffer hit rate for writes +system.physmem.avgGap 329239.83 # Average gap between requests +system.physmem.pageHitRate 56.21 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 1161435240 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 633719625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1603960800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 945386640 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 15166784880 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 74505009510 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 73970535750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 167986832445 # Total energy per rank (pJ) +system.physmem_0.averagePower 723.427350 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 122529683190 # Time in different power states +system.physmem_0.memoryStateTime::REF 7753980000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 101926029060 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 1165888080 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 636149250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1597541400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 950557680 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 15166784880 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 73837287855 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 74556205500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 167910414645 # Total energy per rank (pJ) +system.physmem_1.averagePower 723.098525 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 123510236330 # Time in different power states +system.physmem_1.memoryStateTime::REF 7753980000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 100945998170 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 175052211 # Number of BP lookups +system.cpu.branchPred.condPredicted 131310953 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 7443013 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 90523756 # Number of BTB lookups +system.cpu.branchPred.BTBHits 83852008 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.644135 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 12106556 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 104156 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 92.629837 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 12106573 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 104182 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -337,6 +323,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -358,6 +352,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -379,6 +381,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -401,129 +411,129 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 463037632 # number of cpu cycles simulated +system.cpu.numCycles 464423111 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7744945 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 731737281 # Number of instructions fetch has processed -system.cpu.fetch.Branches 175071152 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 95967885 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 447534266 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 14941835 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 1659 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 92 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 5427 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 236688876 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 32715 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 462757306 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.712462 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.175357 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 7829450 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 731665108 # Number of instructions fetch has processed +system.cpu.fetch.Branches 175052211 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 95958581 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 448342475 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 14938309 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 5167 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 75 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 11385 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 236661621 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 34410 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 463657706 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.708988 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.176697 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 90876963 19.64% 19.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 132670365 28.67% 48.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 57846045 12.50% 60.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 181363933 39.19% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 91809808 19.80% 19.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 132662466 28.61% 48.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 57833448 12.47% 60.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 181351984 39.11% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 462757306 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.378093 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.580298 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32282524 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 114399962 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 287068107 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 22024470 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 6982243 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 24051856 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 496503 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 715776548 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 29996318 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 6982243 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 63336368 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 51265821 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 40318949 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 276671864 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 24182061 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 686555121 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 13345686 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 9390411 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2448056 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1886350 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 1781676 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 830967104 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3019014961 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 723882014 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 463657706 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.376924 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.575428 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 32373161 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 115247897 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 287024980 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 22030943 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 6980725 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 24047273 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 496181 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 715717692 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 29980742 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 6980725 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 63423134 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 52089726 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 40328416 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 276637091 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 24198614 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 686503661 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 13339375 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 9395545 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2450716 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1889859 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 1786281 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 830901474 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3018793647 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 723833359 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 416 # Number of floating rename lookups system.cpu.rename.CommittedMaps 654123751 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 176843353 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1544699 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1534843 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 42245148 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 143514956 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 67977247 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 12906743 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 11318799 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 668118132 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2978327 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 610228240 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 5853948 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 122686035 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 319113529 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 695 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 462757306 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.318679 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.100986 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 176777723 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1544705 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1534955 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 42254952 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 143502988 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 67972899 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 12881093 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 11309167 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 668070815 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2978330 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 610220228 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 5852709 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 122637533 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 318907162 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 698 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 463657706 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.316101 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.101419 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 146182906 31.59% 31.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 100038869 21.62% 53.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 146348422 31.63% 84.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 63256392 13.67% 98.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 6930234 1.50% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 483 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 147083310 31.72% 31.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 100037180 21.58% 53.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 146356248 31.57% 84.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 63253795 13.64% 98.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 6926698 1.49% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 475 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 462757306 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 463657706 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 71302550 52.76% 52.76% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 30 0.00% 52.76% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 52.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 52.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 52.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 52.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 52.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 52.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 52.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 52.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 52.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 52.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 52.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 52.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.76% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 44544615 32.96% 85.72% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 19303772 14.28% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 71297182 52.75% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 31 0.00% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 44549866 32.96% 85.71% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 19309097 14.29% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 413152046 67.70% 67.70% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 351776 0.06% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 413143881 67.70% 67.70% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 351753 0.06% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.76% # Type of FU issued @@ -551,84 +561,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.76% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 134203526 21.99% 89.75% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 62520889 10.25% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 134202503 21.99% 89.75% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 62522088 10.25% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 610228240 # Type of FU issued -system.cpu.iq.rate 1.317880 # Inst issue rate -system.cpu.iq.fu_busy_cnt 135150967 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.221476 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1824218408 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 793810560 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 594959757 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 610220228 # Type of FU issued +system.cpu.iq.rate 1.313932 # Inst issue rate +system.cpu.iq.fu_busy_cnt 135156176 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.221488 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1825106754 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 793714763 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 594959628 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 293 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 316 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 745379030 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 745376227 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 177 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 7280442 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 7281483 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 27630200 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 25086 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 28806 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 11116770 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 27618232 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 25000 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 28827 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 11112422 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 223121 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 19597 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 224691 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 19267 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 6982243 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 22081514 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 631252 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 672583080 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 6980725 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 22383279 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 635884 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 672535669 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 143514956 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 67977247 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1489785 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 250111 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 248516 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 28806 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3822828 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3734625 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 7557453 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 599378907 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 129568453 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 10849333 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 143502988 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 67972899 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1489788 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 251092 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 252064 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 28827 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3821462 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3734064 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 7555526 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 599376603 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 129568443 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 10843625 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1486621 # number of nop insts executed -system.cpu.iew.exec_refs 190517594 # number of memory reference insts executed -system.cpu.iew.exec_branches 131372634 # Number of branches executed -system.cpu.iew.exec_stores 60949141 # Number of stores executed -system.cpu.iew.exec_rate 1.294450 # Inst execution rate -system.cpu.iew.wb_sent 596258031 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 594959773 # cumulative count of insts written-back -system.cpu.iew.wb_producers 349881958 # num instructions producing a value -system.cpu.iew.wb_consumers 570306345 # num instructions consuming a value +system.cpu.iew.exec_nop 1486524 # number of nop insts executed +system.cpu.iew.exec_refs 190520911 # number of memory reference insts executed +system.cpu.iew.exec_branches 131371292 # Number of branches executed +system.cpu.iew.exec_stores 60952468 # Number of stores executed +system.cpu.iew.exec_rate 1.290583 # Inst execution rate +system.cpu.iew.wb_sent 596255942 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 594959644 # cumulative count of insts written-back +system.cpu.iew.wb_producers 349870966 # num instructions producing a value +system.cpu.iew.wb_consumers 570295631 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.284906 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.613498 # average fanout of values written-back +system.cpu.iew.wb_rate 1.281072 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.613491 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 109964782 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 109920418 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 6956119 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 445653385 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.231214 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.895145 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 6954584 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 446560356 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.228714 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.894004 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 217106456 48.72% 48.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 116021912 26.03% 74.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 43540852 9.77% 84.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 23444090 5.26% 89.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 10918152 2.45% 92.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 8056532 1.81% 94.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 8490018 1.91% 95.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 4239418 0.95% 96.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 13835955 3.10% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 218012124 48.82% 48.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 116021741 25.98% 74.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 43540177 9.75% 84.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 23444560 5.25% 89.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 10920781 2.45% 92.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 8059552 1.80% 94.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 8487825 1.90% 95.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 4237549 0.95% 96.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 13836047 3.10% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 445653385 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 446560356 # Number of insts commited each cycle system.cpu.commit.committedInsts 506581607 # Number of instructions committed system.cpu.commit.committedOps 548694828 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -674,513 +684,527 @@ system.cpu.commit.op_class_0::MemWrite 56860477 10.36% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 548694828 # Class of committed instruction -system.cpu.commit.bw_lim_events 13835955 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 13836047 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1090469902 # The number of ROB reads -system.cpu.rob.rob_writes 1334452492 # The number of ROB writes -system.cpu.timesIdled 9125 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 280326 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 1091332417 # The number of ROB reads +system.cpu.rob.rob_writes 1334357175 # The number of ROB writes +system.cpu.timesIdled 13678 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 765405 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 505237723 # Number of Instructions Simulated system.cpu.committedOps 547350944 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.916475 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.916475 # CPI: Total CPI of All Threads -system.cpu.ipc 1.091137 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.091137 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 611059162 # number of integer regfile reads -system.cpu.int_regfile_writes 328109228 # number of integer regfile writes +system.cpu.cpi 0.919217 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.919217 # CPI: Total CPI of All Threads +system.cpu.ipc 1.087882 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.087882 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 611063177 # number of integer regfile reads +system.cpu.int_regfile_writes 328106532 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.cc_regfile_reads 2170105339 # number of cc regfile reads -system.cpu.cc_regfile_writes 376537944 # number of cc regfile writes -system.cpu.misc_regfile_reads 217957701 # number of misc regfile reads +system.cpu.cc_regfile_reads 2170100255 # number of cc regfile reads +system.cpu.cc_regfile_writes 376532879 # number of cc regfile writes +system.cpu.misc_regfile_reads 217961412 # number of misc regfile reads system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes -system.cpu.toL2Bus.trans_dist::ReadReq 2375912 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2375911 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2348838 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 453182 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 26 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 26 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 521741 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 521741 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 148122 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7996043 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8144165 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4738880 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 331034560 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 335773440 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 453214 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 5699735 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.079509 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.270532 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 5246553 92.05% 92.05% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 453182 7.95% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5699735 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4972129219 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 2.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 1500 # Layer occupancy (ticks) -system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 111405470 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 4255724730 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.8 # Layer utilization (%) -system.cpu.icache.tags.replacements 73538 # number of replacements -system.cpu.icache.tags.tagsinuse 468.006132 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 236609871 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 74050 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3195.271722 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 114437110000 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 468.006132 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.914074 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.914074 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 2823114 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.633158 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 169651956 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2823626 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 60.083012 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 496259500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.633158 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999284 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999284 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 172 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 274 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 66 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 356228622 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 356228622 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 114681272 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114681272 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 51990753 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 51990753 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 2786 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 2786 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488557 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 1488557 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 166672025 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 166672025 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 166674811 # number of overall hits +system.cpu.dcache.overall_hits::total 166674811 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 4801959 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 4801959 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2248553 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2248553 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 11 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 11 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 66 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 66 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 7050512 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 7050512 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 7050523 # number of overall misses +system.cpu.dcache.overall_misses::total 7050523 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 53499385357 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 53499385357 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 17165986851 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 17165986851 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1002500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 1002500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 70665372208 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 70665372208 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 70665372208 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 70665372208 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 119483231 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 119483231 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 2797 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 2797 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488623 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1488623 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 173722537 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 173722537 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 173725334 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 173725334 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040189 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.040189 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.041456 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.041456 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.003933 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.003933 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000044 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000044 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.040585 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.040585 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.040584 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.040584 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11141.158297 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11141.158297 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7634.237152 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 7634.237152 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15189.393939 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15189.393939 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 10022.729159 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 10022.729159 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 10022.713522 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 10022.713522 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 56 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 454984 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 7 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 10035 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 8 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 45.339711 # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 2354028 # number of writebacks +system.cpu.dcache.writebacks::total 2354028 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2498261 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2498261 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1728610 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1728610 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 66 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 66 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 4226871 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 4226871 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 4226871 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 4226871 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2303698 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 2303698 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 519943 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 519943 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 10 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 10 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2823641 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2823641 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2823651 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2823651 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 25499562714 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 25499562714 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4017408221 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4017408221 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 706750 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 706750 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29516970935 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 29516970935 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29517677685 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 29517677685 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019281 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019281 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009586 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009586 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.003575 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.003575 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016254 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016254 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016254 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.016254 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11068.969420 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11068.969420 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 7726.631998 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 7726.631998 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 70675 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 70675 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10453.514075 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 10453.514075 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10453.727350 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 10453.727350 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.tags.replacements 73454 # number of replacements +system.cpu.icache.tags.tagsinuse 465.665769 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 236580046 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 73966 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 3198.497228 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 114499459250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 465.665769 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.909503 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.909503 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 121 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 119 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 19 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 14 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 16 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 473451718 # Number of tag accesses -system.cpu.icache.tags.data_accesses 473451718 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 236609871 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 236609871 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 236609871 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 236609871 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 236609871 # number of overall hits -system.cpu.icache.overall_hits::total 236609871 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 78950 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 78950 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 78950 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 78950 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 78950 # number of overall misses -system.cpu.icache.overall_misses::total 78950 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 870914265 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 870914265 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 870914265 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 870914265 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 870914265 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 870914265 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 236688821 # 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mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.115385 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.006925 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.006925 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.028469 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.047440 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.046955 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.028469 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.047440 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.080000 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.080000 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.007063 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.007063 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.143898 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.051203 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.053569 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.143898 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.051203 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.173042 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 73450.188805 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62120.549015 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62300.872022 # average ReadReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 59881.524714 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 59881.524714 # average HardPFReq mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.148555 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58219.159448 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61237.788677 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61025.777861 # average ReadReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 65743.908734 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 65743.908734 # average HardPFReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 6001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 6001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64039.787434 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64039.787434 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73450.188805 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62172.316155 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62347.048663 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73450.188805 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62172.316155 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 59881.524714 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60550.545253 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62405.294437 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62405.294437 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58219.159448 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61267.546031 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61058.528060 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58219.159448 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61267.546031 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 65743.908734 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64054.352517 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 2823064 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.644481 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 169655503 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2823576 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 60.085333 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 487301500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.644481 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999306 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999306 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 191 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 255 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 66 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 356232628 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 356232628 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 114685055 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 114685055 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 51990518 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 51990518 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 2782 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 2782 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488556 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 1488556 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 166675573 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 166675573 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 166678355 # number of overall hits -system.cpu.dcache.overall_hits::total 166678355 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 4800209 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 4800209 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2248788 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2248788 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 11 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 11 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 66 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 66 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 7048997 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 7048997 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 7049008 # number of overall misses -system.cpu.dcache.overall_misses::total 7049008 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 52407946970 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 52407946970 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 17171706952 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 17171706952 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1091500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 1091500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 69579653922 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 69579653922 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 69579653922 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 69579653922 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 119485264 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 119485264 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 2793 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 2793 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488622 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 1488622 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 173724570 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 173724570 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 173727363 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 173727363 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040174 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.040174 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.041460 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.041460 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.003938 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.003938 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000044 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000044 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.040576 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.040576 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.040575 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.040575 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 10917.846904 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 10917.846904 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7635.983006 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 7635.983006 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16537.878788 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16537.878788 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 9870.858779 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 9870.858779 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 9870.843376 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 9870.843376 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 90 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 457811 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 10298 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 18 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 44.456302 # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2348838 # number of writebacks -system.cpu.dcache.writebacks::total 2348838 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2496542 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2496542 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1728863 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1728863 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 66 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 66 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4225405 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4225405 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4225405 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4225405 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2303667 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 2303667 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 519925 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 519925 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 10 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 10 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2823592 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2823592 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2823602 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2823602 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24988772774 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 24988772774 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4018318990 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4018318990 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 655000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 655000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29007091764 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 29007091764 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29007746764 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 29007746764 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019280 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019280 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009586 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009586 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.003580 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.003580 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016253 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.016253 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016253 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.016253 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 10847.389303 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 10847.389303 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 7728.651229 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 7728.651229 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 65500 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 65500 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10273.117279 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 10273.117279 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10273.312869 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 10273.312869 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 2375885 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2375884 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2354028 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 335698 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 25 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 25 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 521734 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 521734 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 147954 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8001330 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8149284 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4733504 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 331369856 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 336103360 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 335729 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 5587370 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5.060082 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.237638 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 5251672 93.99% 93.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 335698 6.01% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 5587370 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4979864499 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 2.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 112728958 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 4257992809 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.8 # Layer utilization (%) +system.membus.trans_dist::ReadReq 408974 # Transaction distribution +system.membus.trans_dist::ReadResp 408974 # Transaction distribution +system.membus.trans_dist::Writeback 292638 # Transaction distribution +system.membus.trans_dist::UpgradeReq 3 # Transaction distribution +system.membus.trans_dist::UpgradeResp 3 # Transaction distribution +system.membus.trans_dist::ReadExReq 3684 # Transaction distribution +system.membus.trans_dist::ReadExResp 3684 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1117960 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1117960 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 45138944 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 45138944 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 705299 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 705299 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 705299 # Request fanout histogram +system.membus.reqLayer0.occupancy 3281426491 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 3862639706 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 1.7 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt index aa1528255..29aebf258 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.279362 # Nu sim_ticks 279362297500 # Number of ticks simulated final_tick 279362297500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2087081 # Simulator instruction rate (inst/s) -host_op_rate 2260585 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1150953174 # Simulator tick rate (ticks/s) -host_mem_usage 299952 # Number of bytes of host memory used -host_seconds 242.72 # Real time elapsed on the host +host_inst_rate 1700410 # Simulator instruction rate (inst/s) +host_op_rate 1841769 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 937717572 # Simulator tick rate (ticks/s) +host_mem_usage 304668 # Number of bytes of host memory used +host_seconds 297.92 # Real time elapsed on the host sim_insts 506581607 # Number of instructions simulated sim_ops 548694828 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -35,37 +35,15 @@ system.physmem.bw_write::total 773431583 # Wr system.physmem.bw_total::cpu.inst 7397009255 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2287067119 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 9684076374 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 630711790 # Transaction distribution -system.membus.trans_dist::ReadResp 632200331 # Transaction distribution -system.membus.trans_dist::WriteReq 54239306 # Transaction distribution -system.membus.trans_dist::WriteResp 54239306 # Transaction distribution -system.membus.trans_dist::SoftPFReq 2571 # Transaction distribution -system.membus.trans_dist::SoftPFResp 2571 # Transaction distribution -system.membus.trans_dist::LoadLockedReq 1488541 # Transaction distribution -system.membus.trans_dist::StoreCondReq 1488541 # Transaction distribution -system.membus.trans_dist::StoreCondResp 1488541 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1033222750 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 342638748 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1375861498 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 2066445500 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 638920325 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 2705365825 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 687930749 # Request fanout histogram -system.membus.snoop_fanout::mean 4.750964 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.432455 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::4 171319374 24.90% 24.90% # Request fanout histogram -system.membus.snoop_fanout::5 516611375 75.10% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 4 # Request fanout histogram -system.membus.snoop_fanout::max_value 5 # Request fanout histogram -system.membus.snoop_fanout::total 687930749 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -87,6 +65,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -108,6 +94,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -129,6 +123,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -211,5 +213,35 @@ system.cpu.op_class::MemWrite 56860479 10.36% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 548695378 # Class of executed instruction +system.membus.trans_dist::ReadReq 630711790 # Transaction distribution +system.membus.trans_dist::ReadResp 632200331 # Transaction distribution +system.membus.trans_dist::WriteReq 54239306 # Transaction distribution +system.membus.trans_dist::WriteResp 54239306 # Transaction distribution +system.membus.trans_dist::SoftPFReq 2571 # Transaction distribution +system.membus.trans_dist::SoftPFResp 2571 # Transaction distribution +system.membus.trans_dist::LoadLockedReq 1488541 # Transaction distribution +system.membus.trans_dist::StoreCondReq 1488541 # Transaction distribution +system.membus.trans_dist::StoreCondResp 1488541 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1033222750 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 342638748 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1375861498 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 2066445500 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 638920325 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 2705365825 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 687930749 # Request fanout histogram +system.membus.snoop_fanout::mean 4.750964 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.432455 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::4 171319374 24.90% 24.90% # Request fanout histogram +system.membus.snoop_fanout::5 516611375 75.10% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 4 # Request fanout histogram +system.membus.snoop_fanout::max_value 5 # Request fanout histogram +system.membus.snoop_fanout::total 687930749 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt index a70fb0c6b..efad42105 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.707539 # Nu sim_ticks 707539023000 # Number of ticks simulated final_tick 707539023000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1199909 # Simulator instruction rate (inst/s) -host_op_rate 1299448 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1681197618 # Simulator tick rate (ticks/s) -host_mem_usage 309428 # Number of bytes of host memory used -host_seconds 420.85 # Real time elapsed on the host +host_inst_rate 1166033 # Simulator instruction rate (inst/s) +host_op_rate 1262762 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1633733414 # Simulator tick rate (ticks/s) +host_mem_usage 312880 # Number of bytes of host memory used +host_seconds 433.08 # Real time elapsed on the host sim_insts 504986853 # Number of instructions simulated sim_ops 546878104 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -36,31 +36,15 @@ system.physmem.bw_total::writebacks 8679369 # To system.physmem.bw_total::cpu.inst 250559 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 12652667 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 21582595 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 41855 # Transaction distribution -system.membus.trans_dist::ReadResp 41855 # Transaction distribution -system.membus.trans_dist::Writeback 95953 # Transaction distribution -system.membus.trans_dist::ReadExReq 100794 # Transaction distribution -system.membus.trans_dist::ReadExResp 100794 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 381251 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 381251 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15270528 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 15270528 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 238603 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 238603 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 238603 # Request fanout histogram -system.membus.reqLayer0.occupancy 1018523828 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 1290155000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.2 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -82,6 +66,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -103,6 +95,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -124,6 +124,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -206,6 +214,139 @@ system.cpu.op_class::MemWrite 56860479 10.36% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 548695378 # Class of executed instruction +system.cpu.dcache.tags.replacements 1134822 # number of replacements +system.cpu.dcache.tags.tagsinuse 4065.318438 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 170180456 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1138918 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 149.422922 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 11716392000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4065.318438 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.992509 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.992509 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 343 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3546 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 165 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 343777666 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 343777666 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 113317758 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 113317758 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 53883046 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 53883046 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 2570 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 2570 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 167200804 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 167200804 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 167203374 # number of overall hits +system.cpu.dcache.overall_hits::total 167203374 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 782657 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 782657 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 356260 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 356260 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 1138917 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1138917 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1138918 # number of overall misses +system.cpu.dcache.overall_misses::total 1138918 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11819576500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11819576500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8868781000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8868781000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 20688357500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 20688357500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 20688357500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 20688357500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 114100415 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 114100415 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 2571 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 2571 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 168339721 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 168339721 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 168342292 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 168342292 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.006859 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.006859 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006568 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.006568 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000389 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.000389 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.006766 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.006766 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.006765 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.006765 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15101.860074 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15101.860074 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24894.125077 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 24894.125077 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 18164.938709 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 18164.938709 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 18164.922760 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 18164.922760 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 1064905 # number of writebacks +system.cpu.dcache.writebacks::total 1064905 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 782657 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 782657 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356260 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 356260 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1138917 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1138917 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1138918 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1138918 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10254262500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10254262500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8156261000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8156261000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 53000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 53000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18410523500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 18410523500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18410576500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 18410576500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006859 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006859 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006568 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006568 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000389 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000389 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006766 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006766 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006765 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006765 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13101.860074 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13101.860074 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22894.125077 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22894.125077 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16164.938709 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 16164.938709 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16164.971051 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 16164.971051 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 9788 # number of replacements system.cpu.icache.tags.tagsinuse 983.372001 # Cycle average of tags in use system.cpu.icache.tags.total_refs 516599855 # Total number of references to valid blocks. @@ -439,139 +580,6 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40030.144404 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40009.561836 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40009.961514 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1134822 # number of replacements -system.cpu.dcache.tags.tagsinuse 4065.318438 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 170180456 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1138918 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 149.422922 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 11716392000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4065.318438 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.992509 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.992509 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 343 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3546 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 165 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 343777666 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 343777666 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 113317758 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 113317758 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 53883046 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 53883046 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 2570 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 2570 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 167200804 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 167200804 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 167203374 # number of overall hits -system.cpu.dcache.overall_hits::total 167203374 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 782657 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 782657 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 356260 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 356260 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 1138917 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1138917 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1138918 # number of overall misses -system.cpu.dcache.overall_misses::total 1138918 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11819576500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11819576500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8868781000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8868781000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 20688357500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 20688357500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 20688357500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 20688357500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 114100415 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 114100415 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 2571 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 2571 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 168339721 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 168339721 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 168342292 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 168342292 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.006859 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.006859 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006568 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.006568 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000389 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.000389 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.006766 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.006766 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.006765 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.006765 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15101.860074 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15101.860074 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24894.125077 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 24894.125077 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 18164.938709 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 18164.938709 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 18164.922760 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 18164.922760 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1064905 # number of writebacks -system.cpu.dcache.writebacks::total 1064905 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 782657 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 782657 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356260 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 356260 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1138917 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1138917 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1138918 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1138918 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10254262500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10254262500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8156261000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8156261000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 53000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 53000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18410523500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 18410523500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18410576500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 18410576500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006859 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006859 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006568 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006568 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000389 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000389 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006766 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006766 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006765 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006765 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13101.860074 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13101.860074 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22894.125077 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22894.125077 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53000 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16164.938709 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 16164.938709 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16164.971051 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 16164.971051 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 794179 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 794179 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 1064905 # Transaction distribution @@ -605,5 +613,29 @@ system.cpu.toL2Bus.respLayer0.occupancy 17281500 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 1708377000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.trans_dist::ReadReq 41855 # Transaction distribution +system.membus.trans_dist::ReadResp 41855 # Transaction distribution +system.membus.trans_dist::Writeback 95953 # Transaction distribution +system.membus.trans_dist::ReadExReq 100794 # Transaction distribution +system.membus.trans_dist::ReadExResp 100794 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 381251 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 381251 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15270528 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 15270528 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 238603 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 238603 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 238603 # Request fanout histogram +system.membus.reqLayer0.occupancy 1018523828 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 1290155000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index 666f127d9..be422e790 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,108 +1,108 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.451764 # Number of seconds simulated -sim_ticks 451764406000 # Number of ticks simulated -final_tick 451764406000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.451526 # Number of seconds simulated +sim_ticks 451526391500 # Number of ticks simulated +final_tick 451526391500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 112231 # Simulator instruction rate (inst/s) -host_op_rate 207527 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 61317335 # Simulator tick rate (ticks/s) -host_mem_usage 367016 # Number of bytes of host memory used -host_seconds 7367.65 # Real time elapsed on the host +host_inst_rate 97078 # Simulator instruction rate (inst/s) +host_op_rate 179507 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 53010367 # Simulator tick rate (ticks/s) +host_mem_usage 427448 # Number of bytes of host memory used +host_seconds 8517.70 # Real time elapsed on the host sim_insts 826877109 # Number of instructions simulated sim_ops 1528988701 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 224064 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24540544 # Number of bytes read from this memory -system.physmem.bytes_read::total 24764608 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 224064 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 224064 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18820736 # Number of bytes written to this memory -system.physmem.bytes_written::total 18820736 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3501 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 383446 # Number of read requests responded to by this memory -system.physmem.num_reads::total 386947 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 294074 # Number of write requests responded to by this memory -system.physmem.num_writes::total 294074 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 495975 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 54321553 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 54817528 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 495975 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 495975 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 41660511 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 41660511 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 41660511 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 495975 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 54321553 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 96478039 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 386948 # Number of read requests accepted -system.physmem.writeReqs 294074 # Number of write requests accepted -system.physmem.readBursts 386948 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 294074 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 24743168 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 21504 # Total number of bytes read from write queue -system.physmem.bytesWritten 18819072 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 24764672 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18820736 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 336 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 224960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24535168 # Number of bytes read from this memory +system.physmem.bytes_read::total 24760128 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 224960 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 224960 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18817920 # Number of bytes written to this memory +system.physmem.bytes_written::total 18817920 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3515 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 383362 # Number of read requests responded to by this memory +system.physmem.num_reads::total 386877 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 294030 # Number of write requests responded to by this memory +system.physmem.num_writes::total 294030 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 498221 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 54338281 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 54836502 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 498221 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 498221 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 41676235 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 41676235 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 41676235 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 498221 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 54338281 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 96512737 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 386877 # Number of read requests accepted +system.physmem.writeReqs 294030 # Number of write requests accepted +system.physmem.readBursts 386877 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 294030 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 24738496 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 21632 # Total number of bytes read from write queue +system.physmem.bytesWritten 18816576 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 24760128 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18817920 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 338 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 179060 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 24122 # Per bank write bursts -system.physmem.perBankRdBursts::1 26505 # Per bank write bursts -system.physmem.perBankRdBursts::2 24681 # Per bank write bursts -system.physmem.perBankRdBursts::3 24611 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 180174 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 24137 # Per bank write bursts +system.physmem.perBankRdBursts::1 26529 # Per bank write bursts +system.physmem.perBankRdBursts::2 24699 # Per bank write bursts +system.physmem.perBankRdBursts::3 24593 # Per bank write bursts system.physmem.perBankRdBursts::4 23302 # Per bank write bursts -system.physmem.perBankRdBursts::5 23732 # Per bank write bursts -system.physmem.perBankRdBursts::6 24448 # Per bank write bursts -system.physmem.perBankRdBursts::7 24311 # Per bank write bursts -system.physmem.perBankRdBursts::8 23620 # Per bank write bursts -system.physmem.perBankRdBursts::9 23937 # Per bank write bursts -system.physmem.perBankRdBursts::10 24812 # Per bank write bursts -system.physmem.perBankRdBursts::11 24076 # Per bank write bursts -system.physmem.perBankRdBursts::12 23393 # Per bank write bursts -system.physmem.perBankRdBursts::13 22985 # Per bank write bursts -system.physmem.perBankRdBursts::14 24096 # Per bank write bursts -system.physmem.perBankRdBursts::15 23981 # Per bank write bursts +system.physmem.perBankRdBursts::5 23749 # Per bank write bursts +system.physmem.perBankRdBursts::6 24449 # Per bank write bursts +system.physmem.perBankRdBursts::7 24297 # Per bank write bursts +system.physmem.perBankRdBursts::8 23610 # Per bank write bursts +system.physmem.perBankRdBursts::9 23919 # Per bank write bursts +system.physmem.perBankRdBursts::10 24817 # Per bank write bursts +system.physmem.perBankRdBursts::11 24050 # Per bank write bursts +system.physmem.perBankRdBursts::12 23346 # Per bank write bursts +system.physmem.perBankRdBursts::13 22971 # Per bank write bursts +system.physmem.perBankRdBursts::14 24088 # Per bank write bursts +system.physmem.perBankRdBursts::15 23983 # Per bank write bursts system.physmem.perBankWrBursts::0 18558 # Per bank write bursts -system.physmem.perBankWrBursts::1 19850 # Per bank write bursts -system.physmem.perBankWrBursts::2 18948 # Per bank write bursts -system.physmem.perBankWrBursts::3 18946 # Per bank write bursts +system.physmem.perBankWrBursts::1 19844 # Per bank write bursts +system.physmem.perBankWrBursts::2 18955 # Per bank write bursts +system.physmem.perBankWrBursts::3 18948 # Per bank write bursts system.physmem.perBankWrBursts::4 18040 # Per bank write bursts -system.physmem.perBankWrBursts::5 18437 # Per bank write bursts -system.physmem.perBankWrBursts::6 18993 # Per bank write bursts -system.physmem.perBankWrBursts::7 18991 # Per bank write bursts -system.physmem.perBankWrBursts::8 18543 # Per bank write bursts -system.physmem.perBankWrBursts::9 18160 # Per bank write bursts -system.physmem.perBankWrBursts::10 18841 # Per bank write bursts -system.physmem.perBankWrBursts::11 17736 # Per bank write bursts -system.physmem.perBankWrBursts::12 17380 # Per bank write bursts -system.physmem.perBankWrBursts::13 16967 # Per bank write bursts -system.physmem.perBankWrBursts::14 17832 # Per bank write bursts -system.physmem.perBankWrBursts::15 17826 # Per bank write bursts +system.physmem.perBankWrBursts::5 18446 # Per bank write bursts +system.physmem.perBankWrBursts::6 18985 # Per bank write bursts +system.physmem.perBankWrBursts::7 18975 # Per bank write bursts +system.physmem.perBankWrBursts::8 18547 # Per bank write bursts +system.physmem.perBankWrBursts::9 18155 # Per bank write bursts +system.physmem.perBankWrBursts::10 18842 # Per bank write bursts +system.physmem.perBankWrBursts::11 17721 # Per bank write bursts +system.physmem.perBankWrBursts::12 17374 # Per bank write bursts +system.physmem.perBankWrBursts::13 16974 # Per bank write bursts +system.physmem.perBankWrBursts::14 17821 # Per bank write bursts +system.physmem.perBankWrBursts::15 17824 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 451764392500 # Total gap between requests +system.physmem.totGap 451526286000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 386948 # Read request sizes (log2) +system.physmem.readPktSize::6 386877 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 294074 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 381637 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4588 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 337 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 38 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 294030 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 381438 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4703 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 355 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 33 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -144,418 +144,395 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 6527 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 16919 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 17478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6621 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 16894 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 17467 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 17566 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 17579 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17557 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 17614 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17580 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 17583 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17609 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 17628 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 17613 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 17619 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 17776 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 17688 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 17635 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17848 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17586 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17479 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17612 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 17623 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 17621 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 17592 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 17724 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 17701 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 17610 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17799 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17543 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17462 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 5 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 147402 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 295.521852 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 174.115334 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 323.715133 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 54829 37.20% 37.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 40372 27.39% 64.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 13383 9.08% 73.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7515 5.10% 78.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 5234 3.55% 82.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3732 2.53% 84.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3157 2.14% 86.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2805 1.90% 88.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 16375 11.11% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 147402 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17447 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 22.158537 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 209.201153 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 17434 99.93% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 9 0.05% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 2 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 147686 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 294.912829 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 174.000830 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 322.915309 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 54902 37.17% 37.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 40417 27.37% 64.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 13633 9.23% 73.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7488 5.07% 78.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 5349 3.62% 82.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3749 2.54% 85.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3045 2.06% 87.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2781 1.88% 88.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 16322 11.05% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 147686 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17443 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 22.159892 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 209.587687 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 17430 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 8 0.05% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 3 0.02% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::3072-4095 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17447 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17447 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.853786 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.774474 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.995315 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 17244 98.84% 98.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 149 0.85% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 24 0.14% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 7 0.04% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 4 0.02% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 4 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 2 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 17443 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17443 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.855415 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.780849 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.647023 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 17241 98.84% 98.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 150 0.86% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 25 0.14% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 7 0.04% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 4 0.02% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 2 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 1 0.01% 99.93% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::44-47 2 0.01% 99.94% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::48-51 1 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 2 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 1 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 1 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 1 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 1 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 1 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 2 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.01% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::104-107 1 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::236-239 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17447 # Writes before turning the bus around for reads -system.physmem.totQLat 4338654000 # Total ticks spent queuing -system.physmem.totMemAccLat 11587629000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1933060000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11222.24 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::128-131 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 17443 # Writes before turning the bus around for reads +system.physmem.totQLat 4244351250 # Total ticks spent queuing +system.physmem.totMemAccLat 11491957500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1932695000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10980.40 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29972.24 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 54.77 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 41.66 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 54.82 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 41.66 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29730.40 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 54.79 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 41.67 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 54.84 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 41.68 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.75 # Data bus utilization in percentage system.physmem.busUtilRead 0.43 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.33 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.93 # Average write queue length when enqueuing -system.physmem.readRowHits 317693 # Number of row buffer hits during reads -system.physmem.writeRowHits 215552 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.17 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.30 # Row buffer hit rate for writes -system.physmem.avgGap 663362.41 # Average gap between requests -system.physmem.pageHitRate 78.34 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 312439483250 # Time in different power states -system.physmem.memoryStateTime::REF 15085200000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 124235187750 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 567642600 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 546300720 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 309725625 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 298080750 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 1526397600 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 1488559800 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 976736880 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 928272960 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 29506651200 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 29506651200 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 64826566830 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 62404533090 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 214189673250 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 216314264250 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 311903393985 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 311486662770 # Total energy per rank (pJ) -system.physmem.averagePower::0 690.420687 # Core power per rank (mW) -system.physmem.averagePower::1 689.498222 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 179971 # Transaction distribution -system.membus.trans_dist::ReadResp 179970 # Transaction distribution -system.membus.trans_dist::Writeback 294074 # Transaction distribution -system.membus.trans_dist::UpgradeReq 179060 # Transaction distribution -system.membus.trans_dist::UpgradeResp 179060 # Transaction distribution -system.membus.trans_dist::ReadExReq 206977 # Transaction distribution -system.membus.trans_dist::ReadExResp 206977 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1426089 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1426089 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1426089 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43585344 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43585344 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 43585344 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 860082 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 860082 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 860082 # Request fanout histogram -system.membus.reqLayer0.occupancy 3467694500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 3995364517 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.9 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 231811700 # Number of BP lookups -system.cpu.branchPred.condPredicted 231811700 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 9749774 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 132043202 # Number of BTB lookups -system.cpu.branchPred.BTBHits 129334985 # Number of BTB hits +system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing +system.physmem.avgWrQLen 21.42 # Average write queue length when enqueuing +system.physmem.readRowHits 317756 # Number of row buffer hits during reads +system.physmem.writeRowHits 215101 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.21 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.16 # Row buffer hit rate for writes +system.physmem.avgGap 663124.75 # Average gap between requests +system.physmem.pageHitRate 78.30 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 569336040 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 310649625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1526881200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 976788720 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 29491394400 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 64757369970 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 214110228000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 311742647955 # Total energy per rank (pJ) +system.physmem_0.averagePower 690.421834 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 355630472000 # Time in different power states +system.physmem_0.memoryStateTime::REF 15077400000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 80817135000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 547049160 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 298489125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1487951400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 928182240 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 29491394400 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 62071035210 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 216466682250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 311290783785 # Total energy per rank (pJ) +system.physmem_1.averagePower 689.421031 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 359566067000 # Time in different power states +system.physmem_1.memoryStateTime::REF 15077400000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 76881477500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 231910847 # Number of BP lookups +system.cpu.branchPred.condPredicted 231910847 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 9746486 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 132027793 # Number of BTB lookups +system.cpu.branchPred.BTBHits 129309443 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.948992 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 28034260 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1466603 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 97.941077 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 28045741 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1465755 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 903528833 # number of cpu cycles simulated +system.cpu.numCycles 903052797 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 186193866 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1278658073 # Number of instructions fetch has processed -system.cpu.fetch.Branches 231811700 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 157369245 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 706106364 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 20239877 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 1021 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 98431 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 825605 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 1885 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 18 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 180561661 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2733230 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 2 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 903347128 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.632355 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.341099 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 186172753 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1278263981 # Number of instructions fetch has processed +system.cpu.fetch.Branches 231910847 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 157355184 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 705668368 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 20227891 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 1132 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 96729 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 811106 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 1664 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 49 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 180547715 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2736967 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 7 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 902865746 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.633456 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.342016 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 492680103 54.54% 54.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 34123521 3.78% 58.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 33275891 3.68% 62.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 33627770 3.72% 65.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 27182272 3.01% 68.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 27855831 3.08% 71.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 37310737 4.13% 75.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 33828820 3.74% 79.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 183462183 20.31% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 492504429 54.55% 54.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 33980590 3.76% 58.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 33251729 3.68% 62.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 33383912 3.70% 65.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 27248388 3.02% 68.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 27817475 3.08% 71.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 37350305 4.14% 75.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 33792757 3.74% 79.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 183536161 20.33% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 903347128 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.256563 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.415182 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 127724228 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 442644539 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 240143304 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 82715119 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 10119938 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2233772257 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 10119938 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 159908050 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 227395701 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 31553 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 285948747 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 219943139 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2183809979 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 169165 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 140088736 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 23988102 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 45039827 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 2289176453 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5526365527 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3514194402 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 52054 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 902865746 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.256808 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.415492 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 127621918 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 442269855 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 240334233 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 82525795 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 10113945 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2233625829 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 10113945 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 159854620 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 227411371 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 31769 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 285878914 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 219575127 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2183611721 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 177740 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 139597859 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 24038652 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 44983183 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 2288587317 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5525861457 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3514141602 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 52752 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 675135599 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2312 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2290 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 426537147 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 530783294 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 210410050 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 240827707 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 72173678 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2112785390 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 25204 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1829110925 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 437516 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 579120624 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1007560279 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 24652 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 903347128 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.024815 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.069613 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 674546463 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2421 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2405 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 426714045 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 530721549 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 210389629 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 240824950 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 72195473 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2112352245 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 24995 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1828962616 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 418654 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 578669571 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1006826210 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 24443 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 902865746 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.025730 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.070839 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 319005991 35.31% 35.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 130297139 14.42% 49.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 120325805 13.32% 63.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 111338872 12.33% 75.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 91295017 10.11% 85.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 61401299 6.80% 92.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 43188488 4.78% 97.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 19128067 2.12% 99.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 7366450 0.82% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 318904182 35.32% 35.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 130514441 14.46% 49.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 119555800 13.24% 63.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 110903587 12.28% 75.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 91967934 10.19% 85.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 61336498 6.79% 92.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 43115692 4.78% 97.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 19163460 2.12% 99.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 7404152 0.82% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 903347128 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 902865746 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 11298417 42.44% 42.44% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 42.44% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 42.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 42.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 42.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 42.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.44% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 12271176 46.10% 88.54% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3050228 11.46% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 11303507 42.48% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 12206863 45.87% 88.35% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3099868 11.65% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2719541 0.15% 0.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1212963557 66.31% 66.46% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 389902 0.02% 66.48% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 3881002 0.21% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 122 0.00% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 435438564 23.81% 90.50% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 173718237 9.50% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2714574 0.15% 0.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1212750239 66.31% 66.46% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 388692 0.02% 66.48% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 3881011 0.21% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 116 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 435509272 23.81% 90.50% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 173718712 9.50% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1829110925 # Type of FU issued -system.cpu.iq.rate 2.024408 # Inst issue rate -system.cpu.iq.fu_busy_cnt 26619821 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014553 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4588595925 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2692200263 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1799476115 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 30390 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 66120 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 6655 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1852997149 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 14056 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 185108157 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1828962616 # Type of FU issued +system.cpu.iq.rate 2.025311 # Inst issue rate +system.cpu.iq.fu_busy_cnt 26610238 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014549 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4587788532 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2691313007 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1799275575 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 31338 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 67501 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 6790 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1852843768 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 14512 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 185242573 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 146685050 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 212835 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 388917 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 61249864 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 146624129 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 213999 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 388901 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 61229443 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 18586 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 815 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 19562 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 956 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 10119938 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 166724787 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 10164048 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2112810594 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 401170 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 530787207 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 210410050 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 7737 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 4462758 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3568650 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 388917 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 5751622 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4609702 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 10361324 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1807989007 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 429368726 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 21121918 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 10113945 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 166739883 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 10207354 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2112377240 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 401313 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 530726286 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 210389629 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 7530 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 4519493 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3556436 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 388901 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 5749904 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4643271 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 10393175 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1807883955 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 429428539 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 21078661 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 599512830 # number of memory reference insts executed -system.cpu.iew.exec_branches 171944433 # Number of branches executed -system.cpu.iew.exec_stores 170144104 # Number of stores executed -system.cpu.iew.exec_rate 2.001031 # Inst execution rate -system.cpu.iew.wb_sent 1804759601 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1799482770 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1369602342 # num instructions producing a value -system.cpu.iew.wb_consumers 2093301343 # num instructions consuming a value +system.cpu.iew.exec_refs 599547832 # number of memory reference insts executed +system.cpu.iew.exec_branches 171967250 # Number of branches executed +system.cpu.iew.exec_stores 170119293 # Number of stores executed +system.cpu.iew.exec_rate 2.001969 # Inst execution rate +system.cpu.iew.wb_sent 1804612346 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1799282365 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1369352269 # num instructions producing a value +system.cpu.iew.wb_consumers 2092896532 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.991616 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.654279 # average fanout of values written-back +system.cpu.iew.wb_rate 1.992444 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.654286 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 584047933 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 583616621 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 9837228 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 824173638 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.855178 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.504108 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 9832190 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 823756093 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.856118 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.505218 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 355774644 43.17% 43.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 174944190 21.23% 64.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 57267566 6.95% 71.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 86311577 10.47% 81.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 27168668 3.30% 85.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 27065091 3.28% 88.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 9878369 1.20% 89.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 8803957 1.07% 90.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 76959576 9.34% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 355425849 43.15% 43.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 174994405 21.24% 64.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 57317339 6.96% 71.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 86207861 10.47% 81.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 27016335 3.28% 85.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 27048633 3.28% 88.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 9853927 1.20% 89.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 8829984 1.07% 90.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 77061760 9.35% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 824173638 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 823756093 # Number of insts commited each cycle system.cpu.commit.committedInsts 826877109 # Number of instructions committed system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -601,256 +578,338 @@ system.cpu.commit.op_class_0::MemWrite 149160186 9.76% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1528988701 # Class of committed instruction -system.cpu.commit.bw_lim_events 76959576 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 77061760 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2860250696 # The number of ROB reads -system.cpu.rob.rob_writes 4305432556 # The number of ROB writes -system.cpu.timesIdled 2603 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 181705 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2859299655 # The number of ROB reads +system.cpu.rob.rob_writes 4304507020 # The number of ROB writes +system.cpu.timesIdled 2587 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 187051 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826877109 # Number of Instructions Simulated system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.092700 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.092700 # CPI: Total CPI of All Threads -system.cpu.ipc 0.915164 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.915164 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2763452214 # number of integer regfile reads -system.cpu.int_regfile_writes 1467518123 # number of integer regfile writes -system.cpu.fp_regfile_reads 6756 # number of floating regfile reads -system.cpu.fp_regfile_writes 202 # number of floating regfile writes -system.cpu.cc_regfile_reads 600952146 # number of cc regfile reads -system.cpu.cc_regfile_writes 409697644 # number of cc regfile writes -system.cpu.misc_regfile_reads 991728878 # number of misc regfile reads +system.cpu.cpi 1.092125 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.092125 # CPI: Total CPI of All Threads +system.cpu.ipc 0.915646 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.915646 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2763619398 # number of integer regfile reads +system.cpu.int_regfile_writes 1467382261 # number of integer regfile writes +system.cpu.fp_regfile_reads 6855 # number of floating regfile reads +system.cpu.fp_regfile_writes 205 # number of floating regfile writes +system.cpu.cc_regfile_reads 600921704 # number of cc regfile reads +system.cpu.cc_regfile_writes 409683570 # number of cc regfile writes +system.cpu.misc_regfile_reads 991700936 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.trans_dist::ReadReq 1956687 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1956686 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2333034 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 180860 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 180860 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 771518 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 771518 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 198212 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7771975 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7970187 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 551552 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311785216 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 312336768 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 180976 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 5242099 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 5242099 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5242099 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4970549506 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 284884490 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3981162622 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.cpu.icache.tags.replacements 7001 # number of replacements -system.cpu.icache.tags.tagsinuse 1081.953602 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 180366705 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 8614 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 20938.786278 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 2534340 # number of replacements +system.cpu.dcache.tags.tagsinuse 4088.717392 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 388713882 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2538436 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 153.131252 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1658510250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4088.717392 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.998222 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.998222 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 872 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3178 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 786546356 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 786546356 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 240120715 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 240120715 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148188548 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148188548 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 388309263 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 388309263 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 388309263 # number of overall hits +system.cpu.dcache.overall_hits::total 388309263 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2723043 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2723043 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 971654 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 971654 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3694697 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3694697 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3694697 # number of overall misses +system.cpu.dcache.overall_misses::total 3694697 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 55426039088 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 55426039088 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 27751124058 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 27751124058 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 83177163146 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 83177163146 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 83177163146 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 83177163146 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 242843758 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 242843758 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 392003960 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 392003960 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 392003960 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 392003960 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011213 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.011213 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006514 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.006514 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.009425 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009425 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009425 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009425 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20354.448713 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 20354.448713 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28560.705825 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 28560.705825 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22512.580367 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22512.580367 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22512.580367 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22512.580367 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 9748 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 16 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1054 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 3 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.248577 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 5.333333 # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 2333101 # number of writebacks +system.cpu.dcache.writebacks::total 2333101 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 955922 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 955922 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18334 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 18334 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 974256 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 974256 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 974256 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 974256 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1767121 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1767121 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 953320 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 953320 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2720441 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2720441 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2720441 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2720441 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30613583252 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 30613583252 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 25522867191 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 25522867191 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 56136450443 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 56136450443 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 56136450443 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 56136450443 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007277 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007277 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006391 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006391 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006940 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006940 # 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Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 55 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 311 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1172 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.787598 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 361312916 # Number of tag accesses -system.cpu.icache.tags.data_accesses 361312916 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 180369624 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 180369624 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 180369624 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 180369624 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 180369624 # number of overall hits -system.cpu.icache.overall_hits::total 180369624 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 192037 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 192037 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 192037 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 192037 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 192037 # number of overall misses -system.cpu.icache.overall_misses::total 192037 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1182728989 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1182728989 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1182728989 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1182728989 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1182728989 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1182728989 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 180561661 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 180561661 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 180561661 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 180561661 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 180561661 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 180561661 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001064 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.001064 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.001064 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.001064 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.001064 # 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Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1608 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 53 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 308 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1173 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 361286153 # Number of tag accesses +system.cpu.icache.tags.data_accesses 361286153 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 180354535 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 180354535 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 180354535 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 180354535 # 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number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1193812485 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1193812485 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 180547715 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 180547715 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 180547715 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 180547715 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 180547715 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 180547715 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001070 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.001070 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.001070 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.001070 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.001070 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.001070 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6179.793379 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 6179.793379 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 6179.793379 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 6179.793379 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 6179.793379 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 6179.793379 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1413 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 15 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 16 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 57.133333 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 88.312500 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2443 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2443 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2443 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2443 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2443 # 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average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -859,182 +918,121 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 294074 # number of writebacks -system.cpu.l2cache.writebacks::total 294074 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 1 # 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number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 215395750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23002179739 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 23217575489 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 215395750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23002179739 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 23217575489 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.406243 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099865 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.101352 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.989854 # 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average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60592.344047 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60610.468931 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10095.003698 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10095.003698 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59462.489059 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59462.489059 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61524.064553 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59982.423527 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59996.370613 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61524.064553 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59982.423527 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59996.370613 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 294030 # number of writebacks +system.cpu.l2cache.writebacks::total 294030 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3515 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 176333 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 179848 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 180136 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 180136 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 207067 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 207067 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3515 # 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number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12245228538 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 219087000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 22901536746 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 23120623746 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 219087000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 22901536746 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 23120623746 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.408626 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099798 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.101294 # 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number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 18291 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 966414 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 966414 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 966414 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 966414 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1767294 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1767294 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 952177 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 952177 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2719471 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2719471 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2719471 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2719471 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30652377753 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 30652377753 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 25560484625 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 25560484625 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 56212862378 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 56212862378 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 56212862378 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 56212862378 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007275 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007275 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006384 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006384 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006936 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006936 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006936 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006936 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17344.243659 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17344.243659 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26844.257554 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26844.257554 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20670.513632 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20670.513632 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20670.513632 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20670.513632 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 1957626 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1957626 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2333101 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 182005 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 182005 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 771533 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 771533 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 199325 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7773983 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7973308 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 550528 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311778368 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 312328896 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 182121 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 5244265 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 5244265 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 5244265 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4971600701 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 286576989 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 3981486557 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) +system.membus.trans_dist::ReadReq 179848 # Transaction distribution +system.membus.trans_dist::ReadResp 179848 # Transaction distribution +system.membus.trans_dist::Writeback 294030 # Transaction distribution +system.membus.trans_dist::UpgradeReq 180174 # Transaction distribution +system.membus.trans_dist::UpgradeResp 180174 # Transaction distribution +system.membus.trans_dist::ReadExReq 207029 # Transaction distribution +system.membus.trans_dist::ReadExResp 207029 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1428132 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1428132 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1428132 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43578048 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43578048 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 43578048 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 861081 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 861081 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 861081 # Request fanout histogram +system.membus.reqLayer0.occupancy 3467092000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 3996161130 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.9 # Layer utilization (%) ---------- End Simulation Statistics ---------- |