diff options
Diffstat (limited to 'tests/long/se/20.parser/ref')
20 files changed, 1441 insertions, 1385 deletions
diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/minor-timing/config.ini index a401ada34..e8f37d0a8 100644 --- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/config.ini +++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true @@ -24,6 +25,7 @@ mem_mode=timing mem_ranges= memories=system.physmem mmap_using_noreserve=false +multi_thread=false num_work_ids=16 readfile= symbolfile= @@ -132,9 +134,9 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=false max_miss_count=0 @@ -148,6 +150,7 @@ system=system tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 +writeback_clean=false cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.slave[1] @@ -591,9 +594,9 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=true max_miss_count=0 @@ -607,6 +610,7 @@ system=system tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 +writeback_clean=true cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.slave[0] @@ -626,6 +630,7 @@ eventq_index=0 [system.cpu.isa] type=ArmISA +decoderFlavour=Generic eventq_index=0 fpsid=1090793632 id_aa64afr0_el1=0 @@ -701,9 +706,9 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=20 is_read_only=false max_miss_count=0 @@ -717,6 +722,7 @@ system=system tags=system.cpu.l2cache.tags tgts_per_mshr=12 write_buffers=8 +writeback_clean=false cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] @@ -732,12 +738,14 @@ size=2097152 [system.cpu.toL2Bus] type=CoherentXBar +children=snoop_filter clk_domain=system.cpu_clk_domain eventq_index=0 forward_latency=0 frontend_latency=1 +point_of_coherency=false response_latency=1 -snoop_filter=Null +snoop_filter=system.cpu.toL2Bus.snoop_filter snoop_response_latency=1 system=system use_default_range=false @@ -745,6 +753,13 @@ width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port +[system.cpu.toL2Bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + [system.cpu.tracer] type=ExeTracer eventq_index=0 @@ -759,9 +774,9 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/parser +executable=/dist/m5/cpu2000/binaries/arm/linux/parser gid=100 -input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in +input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in kvmInSE=false max_stack_size=67108864 output=cout @@ -794,6 +809,7 @@ clk_domain=system.clk_domain eventq_index=0 forward_latency=4 frontend_latency=3 +point_of_coherency=true response_latency=2 snoop_filter=Null snoop_response_latency=4 diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/simerr b/tests/long/se/20.parser/ref/arm/linux/minor-timing/simerr index be90b0340..eeb19437b 100755 --- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/simerr +++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/simerr @@ -1,3 +1,2 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) -warn: Sockets disabled, not accepting gdb connections warn: CP14 unimplemented crn[8], opc1[2], crm[9], opc2[4] diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/simout b/tests/long/se/20.parser/ref/arm/linux/minor-timing/simout index 984c172ad..73f574cb5 100755 --- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/simout +++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/simout @@ -3,10 +3,10 @@ Redirecting stderr to build/ARM/tests/opt/long/se/20.parser/arm/linux/minor-timi gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 14 2015 23:29:19 -gem5 started Sep 15 2015 03:04:52 -gem5 executing on ribera.cs.wisc.edu -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/minor-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/minor-timing +gem5 compiled Mar 16 2016 15:51:04 +gem5 started Mar 16 2016 15:55:43 +gem5 executing on dinar2c11, pid 15340 +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/minor-timing -re /home/stever/gem5-public/tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/minor-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -70,4 +70,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 363605295500 because target called exit() +Exiting @ tick 363608804500 because target called exit() diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt index 2d282091b..415eb183d 100644 --- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt @@ -1,104 +1,104 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.363578 # Number of seconds simulated -sim_ticks 363578056500 # Number of ticks simulated -final_tick 363578056500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.363609 # Number of seconds simulated +sim_ticks 363608804500 # Number of ticks simulated +final_tick 363608804500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 233007 # Simulator instruction rate (inst/s) -host_op_rate 252377 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 167231069 # Simulator tick rate (ticks/s) -host_mem_usage 322224 # Number of bytes of host memory used -host_seconds 2174.11 # Real time elapsed on the host -sim_insts 506582156 # Number of instructions simulated -sim_ops 548695379 # Number of ops (including micro ops) simulated +host_inst_rate 100066 # Simulator instruction rate (inst/s) +host_op_rate 108385 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 71824585 # Simulator tick rate (ticks/s) +host_mem_usage 304984 # Number of bytes of host memory used +host_seconds 5062.46 # Real time elapsed on the host +sim_insts 506579366 # Number of instructions simulated +sim_ops 548692589 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 179648 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9032384 # Number of bytes read from this memory -system.physmem.bytes_read::total 9212032 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 179648 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 179648 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6219008 # Number of bytes written to this memory -system.physmem.bytes_written::total 6219008 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2807 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 141131 # Number of read requests responded to by this memory -system.physmem.num_reads::total 143938 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 97172 # Number of write requests responded to by this memory -system.physmem.num_writes::total 97172 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 494111 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 24843039 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 25337151 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 494111 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 494111 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 17105015 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 17105015 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 17105015 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 494111 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 24843039 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 42442165 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 143938 # Number of read requests accepted -system.physmem.writeReqs 97172 # Number of write requests accepted -system.physmem.readBursts 143938 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 97172 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9204928 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7104 # Total number of bytes read from write queue -system.physmem.bytesWritten 6217152 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9212032 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6219008 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 111 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 179584 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9028480 # Number of bytes read from this memory +system.physmem.bytes_read::total 9208064 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 179584 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 179584 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6218624 # Number of bytes written to this memory +system.physmem.bytes_written::total 6218624 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2806 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 141070 # Number of read requests responded to by this memory +system.physmem.num_reads::total 143876 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 97166 # Number of write requests responded to by this memory +system.physmem.num_writes::total 97166 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 493893 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 24830202 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 25324095 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 493893 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 493893 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 17102512 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 17102512 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 17102512 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 493893 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 24830202 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 42426607 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 143876 # Number of read requests accepted +system.physmem.writeReqs 97166 # Number of write requests accepted +system.physmem.readBursts 143876 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 97166 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9201472 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6592 # Total number of bytes read from write queue +system.physmem.bytesWritten 6217344 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9208064 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6218624 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 103 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9337 # Per bank write bursts -system.physmem.perBankRdBursts::1 8920 # Per bank write bursts -system.physmem.perBankRdBursts::2 8993 # Per bank write bursts -system.physmem.perBankRdBursts::3 8670 # Per bank write bursts -system.physmem.perBankRdBursts::4 9385 # Per bank write bursts +system.physmem.perBankRdBursts::0 9345 # Per bank write bursts +system.physmem.perBankRdBursts::1 8917 # Per bank write bursts +system.physmem.perBankRdBursts::2 8955 # Per bank write bursts +system.physmem.perBankRdBursts::3 8654 # Per bank write bursts +system.physmem.perBankRdBursts::4 9386 # Per bank write bursts system.physmem.perBankRdBursts::5 9354 # Per bank write bursts -system.physmem.perBankRdBursts::6 8954 # Per bank write bursts +system.physmem.perBankRdBursts::6 8955 # Per bank write bursts system.physmem.perBankRdBursts::7 8104 # Per bank write bursts -system.physmem.perBankRdBursts::8 8602 # Per bank write bursts +system.physmem.perBankRdBursts::8 8603 # Per bank write bursts system.physmem.perBankRdBursts::9 8629 # Per bank write bursts -system.physmem.perBankRdBursts::10 8738 # Per bank write bursts -system.physmem.perBankRdBursts::11 9458 # Per bank write bursts -system.physmem.perBankRdBursts::12 9338 # Per bank write bursts -system.physmem.perBankRdBursts::13 9514 # Per bank write bursts -system.physmem.perBankRdBursts::14 8722 # Per bank write bursts -system.physmem.perBankRdBursts::15 9109 # Per bank write bursts -system.physmem.perBankWrBursts::0 6210 # Per bank write bursts -system.physmem.perBankWrBursts::1 6096 # Per bank write bursts +system.physmem.perBankRdBursts::10 8742 # Per bank write bursts +system.physmem.perBankRdBursts::11 9454 # Per bank write bursts +system.physmem.perBankRdBursts::12 9335 # Per bank write bursts +system.physmem.perBankRdBursts::13 9509 # Per bank write bursts +system.physmem.perBankRdBursts::14 8712 # Per bank write bursts +system.physmem.perBankRdBursts::15 9119 # Per bank write bursts +system.physmem.perBankWrBursts::0 6212 # Per bank write bursts +system.physmem.perBankWrBursts::1 6095 # Per bank write bursts system.physmem.perBankWrBursts::2 6031 # Per bank write bursts -system.physmem.perBankWrBursts::3 5885 # Per bank write bursts -system.physmem.perBankWrBursts::4 6239 # Per bank write bursts -system.physmem.perBankWrBursts::5 6240 # Per bank write bursts -system.physmem.perBankWrBursts::6 6045 # Per bank write bursts -system.physmem.perBankWrBursts::7 5507 # Per bank write bursts -system.physmem.perBankWrBursts::8 5786 # Per bank write bursts -system.physmem.perBankWrBursts::9 5860 # Per bank write bursts -system.physmem.perBankWrBursts::10 5977 # Per bank write bursts -system.physmem.perBankWrBursts::11 6497 # Per bank write bursts -system.physmem.perBankWrBursts::12 6353 # Per bank write bursts -system.physmem.perBankWrBursts::13 6323 # Per bank write bursts -system.physmem.perBankWrBursts::14 6005 # Per bank write bursts -system.physmem.perBankWrBursts::15 6089 # Per bank write bursts +system.physmem.perBankWrBursts::3 5882 # Per bank write bursts +system.physmem.perBankWrBursts::4 6240 # Per bank write bursts +system.physmem.perBankWrBursts::5 6242 # Per bank write bursts +system.physmem.perBankWrBursts::6 6046 # Per bank write bursts +system.physmem.perBankWrBursts::7 5509 # Per bank write bursts +system.physmem.perBankWrBursts::8 5790 # Per bank write bursts +system.physmem.perBankWrBursts::9 5862 # Per bank write bursts +system.physmem.perBankWrBursts::10 5980 # Per bank write bursts +system.physmem.perBankWrBursts::11 6494 # Per bank write bursts +system.physmem.perBankWrBursts::12 6352 # Per bank write bursts +system.physmem.perBankWrBursts::13 6321 # Per bank write bursts +system.physmem.perBankWrBursts::14 5998 # Per bank write bursts +system.physmem.perBankWrBursts::15 6092 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 363578030500 # Total gap between requests +system.physmem.totGap 363608778500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 143938 # Read request sizes (log2) +system.physmem.readPktSize::6 143876 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 97172 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 143477 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 330 # What read queue length does an incoming req see +system.physmem.writePktSize::6 97166 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 143433 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 320 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 20 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -144,37 +144,37 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2944 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3098 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5566 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5669 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5692 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5718 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5717 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5719 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5721 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5717 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5713 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5741 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5750 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5692 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5700 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5635 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2923 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5563 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5694 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5686 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5706 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5721 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5699 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5724 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5731 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5734 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5734 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5738 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5711 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5678 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5643 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 5621 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see @@ -193,112 +193,109 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 65452 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 235.611563 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 156.275569 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 241.348204 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 24841 37.95% 37.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18422 28.15% 66.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6870 10.50% 76.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7970 12.18% 88.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2117 3.23% 92.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1100 1.68% 93.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 791 1.21% 94.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 584 0.89% 95.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 2757 4.21% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 65452 # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 65427 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 235.654638 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 156.256012 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 241.782834 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 24843 37.97% 37.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18425 28.16% 66.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6952 10.63% 76.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7899 12.07% 88.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2020 3.09% 91.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1104 1.69% 93.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 778 1.19% 94.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 662 1.01% 95.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 2744 4.19% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 65427 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 5612 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 25.626515 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 380.491009 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 25.618496 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 380.574654 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::0-1023 5610 99.96% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::total 5612 # Reads before turning the bus around for writes system.physmem.wrPerTurnAround::samples 5612 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.309872 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.213078 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.394006 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-17 2658 47.36% 47.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18-19 2810 50.07% 97.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-21 50 0.89% 98.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22-23 29 0.52% 98.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-25 20 0.36% 99.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26-27 11 0.20% 99.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-29 6 0.11% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30-31 6 0.11% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-33 3 0.05% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34-35 7 0.12% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-37 1 0.02% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::38-39 1 0.02% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-41 1 0.02% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-45 1 0.02% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::46-47 1 0.02% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-49 1 0.02% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::50-51 1 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-53 2 0.04% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-57 1 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.310406 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.214262 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.369355 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-17 2682 47.79% 47.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18-19 2777 49.48% 97.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-21 56 1.00% 98.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22-23 33 0.59% 98.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-25 17 0.30% 99.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26-27 10 0.18% 99.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-29 7 0.12% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30-31 5 0.09% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-33 7 0.12% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34-35 4 0.07% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-37 3 0.05% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-41 2 0.04% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42-43 4 0.07% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-49 1 0.02% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::50-51 1 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-53 1 0.02% 99.96% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::72-73 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-97 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::98-99 1 0.02% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 5612 # Writes before turning the bus around for reads -system.physmem.totQLat 1537591000 # Total ticks spent queuing -system.physmem.totMemAccLat 4234347250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 719135000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10690.56 # Average queueing delay per DRAM burst +system.physmem.totQLat 1539890250 # Total ticks spent queuing +system.physmem.totMemAccLat 4235634000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 718865000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10710.57 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29440.56 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 25.32 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 29460.57 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 25.31 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 17.10 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 25.34 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 17.11 # Average system write bandwidth in MiByte/s +system.physmem.avgRdBWSys 25.32 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 17.10 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.33 # Data bus utilization in percentage system.physmem.busUtilRead 0.20 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.13 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing -system.physmem.avgWrQLen 19.82 # Average write queue length when enqueuing -system.physmem.readRowHits 110822 # Number of row buffer hits during reads -system.physmem.writeRowHits 64690 # Number of row buffer hits during writes +system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing +system.physmem.avgWrQLen 19.45 # Average write queue length when enqueuing +system.physmem.readRowHits 110770 # Number of row buffer hits during reads +system.physmem.writeRowHits 64716 # Number of row buffer hits during writes system.physmem.readRowHitRate 77.05 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 66.57 # Row buffer hit rate for writes -system.physmem.avgGap 1507934.26 # Average gap between requests +system.physmem.writeRowHitRate 66.60 # Row buffer hit rate for writes +system.physmem.avgGap 1508487.23 # Average gap between requests system.physmem.pageHitRate 72.83 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 249245640 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 135997125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 559174200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 312459120 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 23746700640 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 47224643355 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 176717716500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 248945936580 # Total energy per rank (pJ) -system.physmem_0.averagePower 684.723644 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 293681207750 # Time in different power states -system.physmem_0.memoryStateTime::REF 12140440000 # Time in different power states +system.physmem_0.actEnergy 249041520 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 135885750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 558807600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 312407280 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 23748734880 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 47272879035 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 176694091500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 248971847565 # Total energy per rank (pJ) +system.physmem_0.averagePower 684.736255 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 293641319750 # Time in different power states +system.physmem_0.memoryStateTime::REF 12141480000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 57750923750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 57820495250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 245314440 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 133852125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 562247400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 316716480 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 23746700640 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 46957257495 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 176952265500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 248914354080 # Total energy per rank (pJ) -system.physmem_1.averagePower 684.636777 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 294072895750 # Time in different power states -system.physmem_1.memoryStateTime::REF 12140440000 # Time in different power states +system.physmem_1.actEnergy 245269080 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 133827375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 562192800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 316684080 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 23748734880 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 46853247600 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 177062189250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 248922145065 # Total energy per rank (pJ) +system.physmem_1.averagePower 684.599560 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 294255473500 # Time in different power states +system.physmem_1.memoryStateTime::REF 12141480000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 57359475250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 57206580500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 131892190 # Number of BP lookups -system.cpu.branchPred.condPredicted 98029664 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6137262 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 68271020 # Number of BTB lookups -system.cpu.branchPred.BTBHits 64393265 # Number of BTB hits +system.cpu.branchPred.lookups 131890227 # Number of BP lookups +system.cpu.branchPred.condPredicted 98029520 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6134595 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 68518889 # Number of BTB lookups +system.cpu.branchPred.BTBHits 64416393 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 94.320057 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 9980136 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 17826 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 94.012606 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 9980436 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 18277 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -417,24 +414,24 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 727156113 # number of cpu cycles simulated +system.cpu.numCycles 727217609 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 506582156 # Number of instructions committed -system.cpu.committedOps 548695379 # Number of ops (including micro ops) committed -system.cpu.discardedOps 13195789 # Number of ops (including micro ops) which were discarded before commit +system.cpu.committedInsts 506579366 # Number of instructions committed +system.cpu.committedOps 548692589 # Number of ops (including micro ops) committed +system.cpu.discardedOps 13188504 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.435416 # CPI: cycles per instruction -system.cpu.ipc 0.696662 # IPC: instructions per cycle -system.cpu.tickCycles 690690437 # Number of cycles that the object actually ticked -system.cpu.idleCycles 36465676 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 1139983 # number of replacements -system.cpu.dcache.tags.tagsinuse 4070.787946 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 171168228 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1144079 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 149.612245 # Average number of references to valid blocks. +system.cpu.cpi 1.435545 # CPI: cycles per instruction +system.cpu.ipc 0.696599 # IPC: instructions per cycle +system.cpu.tickCycles 690736700 # Number of cycles that the object actually ticked +system.cpu.idleCycles 36480909 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 1141376 # number of replacements +system.cpu.dcache.tags.tagsinuse 4070.790078 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 171162589 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1145472 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 149.425380 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 4896334500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4070.787946 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 4070.790078 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.993845 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.993845 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -443,72 +440,72 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1 18 system.cpu.dcache.tags.age_task_id_blocks_1024::2 551 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 3500 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 346591347 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 346591347 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 114649758 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 114649758 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 53538635 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 53538635 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 2753 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 2753 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 346584178 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 346584178 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 114644865 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114644865 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 53537898 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 53537898 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 2744 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 2744 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 168188393 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168188393 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168191146 # number of overall hits -system.cpu.dcache.overall_hits::total 168191146 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 854719 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 854719 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 700671 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 700671 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 16 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 16 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 1555390 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1555390 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1555406 # number of overall misses -system.cpu.dcache.overall_misses::total 1555406 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 14046321000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 14046321000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 21904504500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 21904504500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 35950825500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 35950825500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 35950825500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 35950825500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 115504477 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 115504477 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 2769 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 2769 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 168182763 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168182763 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168185507 # number of overall hits +system.cpu.dcache.overall_hits::total 168185507 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 855598 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 855598 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 701151 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 701151 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 15 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 15 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 1556749 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1556749 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1556764 # number of overall misses +system.cpu.dcache.overall_misses::total 1556764 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 14056066500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 14056066500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 21917357000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 21917357000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 35973423500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 35973423500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 35973423500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 35973423500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 115500463 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 115500463 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 54239049 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 54239049 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 2759 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 2759 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 169743783 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 169743783 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 169746552 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 169746552 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.007400 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.007400 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.012918 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.012918 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.005778 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.005778 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009163 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009163 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009163 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009163 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16433.846679 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16433.846679 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31262.182251 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31262.182251 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 23113.704923 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 23113.704923 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 23113.467159 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 23113.467159 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 169739512 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 169739512 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 169742271 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 169742271 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.007408 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.007408 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.012927 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.012927 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.005437 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.005437 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.009171 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009171 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009171 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009171 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16428.353619 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16428.353619 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31259.111090 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31259.111090 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 23108.043429 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23108.043429 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 23107.820774 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 23107.820774 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -517,111 +514,111 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1068257 # number of writebacks -system.cpu.dcache.writebacks::total 1068257 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66817 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 66817 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 344507 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 344507 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 411324 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 411324 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 411324 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 411324 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 787902 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 787902 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356164 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 356164 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 13 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 13 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1144066 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1144066 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1144079 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1144079 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12362476000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 12362476000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11126251500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11126251500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1030500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1030500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23488727500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 23488727500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23489758000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 23489758000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006821 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006821 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006567 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006567 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.004695 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.004695 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006740 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006740 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006740 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006740 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15690.372661 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15690.372661 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31239.124392 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31239.124392 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 79269.230769 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 79269.230769 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20530.919982 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20530.919982 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20531.587417 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20531.587417 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 1069283 # number of writebacks +system.cpu.dcache.writebacks::total 1069283 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66543 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 66543 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 344746 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 344746 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 411289 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 411289 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 411289 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 411289 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 789055 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 789055 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356405 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 356405 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 12 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 12 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1145460 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1145460 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1145472 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1145472 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12372636000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 12372636000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11132196500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11132196500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 944000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 944000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23504832500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 23504832500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23505776500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 23505776500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006832 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006832 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006571 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006571 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.004349 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.004349 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006748 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006748 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006748 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006748 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15680.321397 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15680.321397 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31234.681051 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31234.681051 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 78666.666667 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 78666.666667 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20519.994151 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20519.994151 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20520.603297 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20520.603297 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 17711 # number of replacements -system.cpu.icache.tags.tagsinuse 1188.286888 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 199302654 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 19583 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 10177.330031 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 17687 # number of replacements +system.cpu.icache.tags.tagsinuse 1188.299437 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 199347924 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 19559 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 10192.132727 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1188.286888 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.580218 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.580218 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1188.299437 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.580224 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.580224 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1872 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 62 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 57 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 309 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1403 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 63 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 59 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 305 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1404 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.914062 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 398664057 # Number of tag accesses -system.cpu.icache.tags.data_accesses 398664057 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 199302654 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 199302654 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 199302654 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 199302654 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 199302654 # number of overall hits -system.cpu.icache.overall_hits::total 199302654 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 19583 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 19583 # 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miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.143514 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.123167 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.123508 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.143514 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.123167 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.123508 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78428.545240 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78428.545240 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79789.989312 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79789.989312 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82302.661389 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82302.661389 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79789.989312 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79531.516685 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 79536.558923 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79789.989312 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79531.516685 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 79536.558923 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -766,8 +763,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 97172 # number of writebacks -system.cpu.l2cache.writebacks::total 97172 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 97166 # number of writebacks +system.cpu.l2cache.writebacks::total 97166 # number of writebacks system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 14 # number of ReadSharedReq MSHR hits @@ -778,117 +775,117 @@ system.cpu.l2cache.demand_mshr_hits::total 15 # system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 14 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 15 # 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number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 195877500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9809805000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 10005682500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.283161 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.283161 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.143339 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.143339 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.051047 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.051047 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.143339 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.123358 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.123694 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.143339 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.123358 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.123694 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68394.300605 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68394.300605 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69781.795511 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69781.795511 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72305.188022 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72305.188022 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69781.795511 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69508.506281 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69513.835818 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69781.795511 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69508.506281 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69513.835818 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100917 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 100917 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2806 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2806 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 40153 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 40153 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2806 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 141070 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 143876 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2806 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 141070 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 143876 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6905603500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6905603500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 195670500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 195670500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2903188500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2903188500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 195670500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9808792000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 10004462500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 195670500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9808792000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 10004462500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.282954 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.282954 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.143463 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.143463 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.050903 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.050903 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.143463 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.123154 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.123495 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.143463 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.123154 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.123495 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68428.545240 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68428.545240 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69732.893799 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69732.893799 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72303.152940 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72303.152940 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69732.893799 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69531.381584 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69535.311657 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69732.893799 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69531.381584 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69535.311657 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 2321356 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 1157764 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4913 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2623 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2620 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 2324094 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 1159133 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4986 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2609 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2606 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 3 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 807247 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 1165429 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 17711 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 86920 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 356415 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 356415 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 19583 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 787664 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 56877 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3428141 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3485018 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2386816 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141589504 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 143976320 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 112366 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 1276028 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.005963 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.077021 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadResp 808376 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 1166449 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 17687 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 87231 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 356655 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 356655 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 19559 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 788817 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 56805 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3432320 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 3489125 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2383744 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141744320 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 144128064 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 112304 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 1277335 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.006003 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.077277 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1268422 99.40% 99.40% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 7603 0.60% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1269670 99.40% 99.40% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 7662 0.60% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 3 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1276028 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2246646000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1277335 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2249017000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 29392963 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 29357961 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1716126983 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1718215984 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.membus.trans_dist::ReadResp 43015 # Transaction distribution -system.membus.trans_dist::WritebackDirty 97172 # Transaction distribution -system.membus.trans_dist::CleanEvict 12571 # Transaction distribution -system.membus.trans_dist::ReadExReq 100923 # Transaction distribution -system.membus.trans_dist::ReadExResp 100923 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 43015 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 397619 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 397619 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15431040 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 15431040 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 42959 # Transaction distribution +system.membus.trans_dist::WritebackDirty 97166 # Transaction distribution +system.membus.trans_dist::CleanEvict 12529 # Transaction distribution +system.membus.trans_dist::ReadExReq 100917 # Transaction distribution +system.membus.trans_dist::ReadExResp 100917 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 42959 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 397447 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 397447 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15426688 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 15426688 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 253681 # Request fanout histogram +system.membus.snoop_fanout::samples 253571 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 253681 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 253571 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 253681 # Request fanout histogram -system.membus.reqLayer0.occupancy 685231500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 253571 # Request fanout histogram +system.membus.reqLayer0.occupancy 685058500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 764006500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 763682500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini index 8010a167e..7cd34eb9f 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true @@ -24,6 +25,7 @@ mem_mode=atomic mem_ranges= memories=system.physmem mmap_using_noreserve=false +multi_thread=false num_work_ids=16 readfile= symbolfile= @@ -130,6 +132,7 @@ eventq_index=0 [system.cpu.isa] type=ArmISA +decoderFlavour=Generic eventq_index=0 fpsid=1090793632 id_aa64afr0_el1=0 @@ -213,9 +216,9 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/parser +executable=/dist/m5/cpu2000/binaries/arm/linux/parser gid=100 -input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in +input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in kvmInSE=false max_stack_size=67108864 output=cout @@ -248,6 +251,7 @@ clk_domain=system.clk_domain eventq_index=0 forward_latency=4 frontend_latency=3 +point_of_coherency=true response_latency=2 snoop_filter=Null snoop_response_latency=4 diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simerr b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simerr index 1a4f96712..e69de29bb 100755 --- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simerr +++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simerr @@ -1 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout index af6242a6d..b0dd0015e 100755 --- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout @@ -1,12 +1,14 @@ +Redirecting stdout to build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic/simout +Redirecting stderr to build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2014 12:08:08 -gem5 started Jan 23 2014 17:19:30 -gem5 executing on u200540-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic +gem5 compiled Mar 16 2016 15:51:04 +gem5 started Mar 16 2016 16:37:21 +gem5 executing on dinar2c11, pid 16154 +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic -re /home/stever/gem5-public/tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic + Global frequency set at 1000000000000 ticks per second - 0: system.cpu.isa: ISA system set to: 0 0x5d016c0 info: Entering event queue @ 0. Starting simulation... Reading the dictionary files: ************************************************* @@ -68,4 +70,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 290498967000 because target called exit() +Exiting @ tick 279360903000 because target called exit() diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt index 04541cf46..99322fb1a 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.279362 # Number of seconds simulated -sim_ticks 279362298000 # Number of ticks simulated -final_tick 279362298000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.279361 # Number of seconds simulated +sim_ticks 279360903000 # Number of ticks simulated +final_tick 279360903000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1944100 # Simulator instruction rate (inst/s) -host_op_rate 2105717 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1072104103 # Simulator tick rate (ticks/s) -host_mem_usage 306580 # Number of bytes of host memory used -host_seconds 260.57 # Real time elapsed on the host -sim_insts 506581608 # Number of instructions simulated -sim_ops 548694829 # Number of ops (including micro ops) simulated +host_inst_rate 505182 # Simulator instruction rate (inst/s) +host_op_rate 547179 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 278590581 # Simulator tick rate (ticks/s) +host_mem_usage 293956 # Number of bytes of host memory used +host_seconds 1002.77 # Real time elapsed on the host +sim_insts 506578818 # Number of instructions simulated +sim_ops 548692039 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 2066445504 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 422852701 # Number of bytes read from this memory -system.physmem.bytes_read::total 2489298205 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 2066445504 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 2066445504 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 216067624 # Number of bytes written to this memory -system.physmem.bytes_written::total 216067624 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 516611376 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 115591527 # Number of read requests responded to by this memory -system.physmem.num_reads::total 632202903 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 55727847 # Number of write requests responded to by this memory -system.physmem.num_writes::total 55727847 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7397009256 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1513635534 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 8910644789 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7397009256 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7397009256 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 773431582 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 773431582 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7397009256 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2287067115 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 9684076371 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 2066434344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 422848347 # Number of bytes read from this memory +system.physmem.bytes_read::total 2489282691 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 2066434344 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 2066434344 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 216066596 # Number of bytes written to this memory +system.physmem.bytes_written::total 216066596 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 516608586 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 115590054 # Number of read requests responded to by this memory +system.physmem.num_reads::total 632198640 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 55727590 # Number of write requests responded to by this memory +system.physmem.num_writes::total 55727590 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 7397006245 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1513627506 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 8910633751 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7397006245 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7397006245 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 773431764 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 773431764 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7397006245 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2287059270 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 9684065515 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -153,33 +153,33 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 558724597 # number of cpu cycles simulated +system.cpu.numCycles 558721807 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 506581608 # Number of instructions committed -system.cpu.committedOps 548694829 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 448454356 # Number of integer alu accesses +system.cpu.committedInsts 506578818 # Number of instructions committed +system.cpu.committedOps 548692039 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 448447005 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses system.cpu.num_func_calls 19311615 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 90667196 # number of instructions that are conditional controls -system.cpu.num_int_insts 448454356 # number of integer instructions +system.cpu.num_conditional_control_insts 90670594 # number of instructions that are conditional controls +system.cpu.num_int_insts 448447005 # number of integer instructions system.cpu.num_fp_insts 16 # number of float instructions -system.cpu.num_int_register_reads 749039746 # number of times the integer registers were read -system.cpu.num_int_register_writes 290003067 # number of times the integer registers were written +system.cpu.num_int_register_reads 749023756 # number of times the integer registers were read +system.cpu.num_int_register_writes 289993515 # number of times the integer registers were written system.cpu.num_fp_register_reads 16 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 1634230250 # number of times the CC registers were read -system.cpu.num_cc_register_writes 344080722 # number of times the CC registers were written -system.cpu.num_mem_refs 172745235 # number of memory refs -system.cpu.num_load_insts 115884756 # Number of load instructions -system.cpu.num_store_insts 56860479 # Number of store instructions +system.cpu.num_cc_register_reads 1634221880 # number of times the CC registers were read +system.cpu.num_cc_register_writes 344062197 # number of times the CC registers were written +system.cpu.num_mem_refs 172743505 # number of memory refs +system.cpu.num_load_insts 115883283 # Number of load instructions +system.cpu.num_store_insts 56860222 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 558724596.998000 # Number of busy cycles +system.cpu.num_busy_cycles 558721806.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 121548302 # Number of branches fetched +system.cpu.Branches 121552863 # Number of branches fetched system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 375610922 68.46% 68.46% # Class of executed instruction +system.cpu.op_class::IntAlu 375609862 68.46% 68.46% # Class of executed instruction system.cpu.op_class::IntMult 339219 0.06% 68.52% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 68.52% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 68.52% # Class of executed instruction @@ -208,36 +208,36 @@ system.cpu.op_class::SimdFloatMisc 3 0.00% 68.52% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 68.52% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.52% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::MemRead 115884756 21.12% 89.64% # Class of executed instruction -system.cpu.op_class::MemWrite 56860479 10.36% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 115883283 21.12% 89.64% # Class of executed instruction +system.cpu.op_class::MemWrite 56860222 10.36% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 548695379 # Class of executed instruction -system.membus.trans_dist::ReadReq 630711791 # Transaction distribution -system.membus.trans_dist::ReadResp 632200332 # Transaction distribution -system.membus.trans_dist::WriteReq 54239306 # Transaction distribution -system.membus.trans_dist::WriteResp 54239306 # Transaction distribution +system.cpu.op_class::total 548692589 # Class of executed instruction +system.membus.trans_dist::ReadReq 630707528 # Transaction distribution +system.membus.trans_dist::ReadResp 632196069 # Transaction distribution +system.membus.trans_dist::WriteReq 54239049 # Transaction distribution +system.membus.trans_dist::WriteResp 54239049 # Transaction distribution system.membus.trans_dist::SoftPFReq 2571 # Transaction distribution system.membus.trans_dist::SoftPFResp 2571 # Transaction distribution system.membus.trans_dist::LoadLockedReq 1488541 # Transaction distribution system.membus.trans_dist::StoreCondReq 1488541 # Transaction distribution system.membus.trans_dist::StoreCondResp 1488541 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1033222752 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 342638748 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1375861500 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 2066445504 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 638920325 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 2705365829 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1033217172 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 342635288 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1375852460 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 2066434344 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 638914943 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 2705349287 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 687930750 # Request fanout histogram -system.membus.snoop_fanout::mean 0.750964 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.432455 # Request fanout histogram +system.membus.snoop_fanout::samples 687926230 # Request fanout histogram +system.membus.snoop_fanout::mean 0.750965 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.432454 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 171319374 24.90% 24.90% # Request fanout histogram -system.membus.snoop_fanout::1 516611376 75.10% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 171317644 24.90% 24.90% # Request fanout histogram +system.membus.snoop_fanout::1 516608586 75.10% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 687930750 # Request fanout histogram +system.membus.snoop_fanout::total 687926230 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini index bc3661e7a..46644e2cb 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true @@ -24,6 +25,7 @@ mem_mode=timing mem_ranges= memories=system.physmem mmap_using_noreserve=false +multi_thread=false num_work_ids=16 readfile= symbolfile= @@ -85,9 +87,9 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=false max_miss_count=0 @@ -101,6 +103,7 @@ system=system tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 +writeback_clean=false cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.slave[1] @@ -161,9 +164,9 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=true max_miss_count=0 @@ -177,6 +180,7 @@ system=system tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 +writeback_clean=true cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.slave[0] @@ -196,6 +200,7 @@ eventq_index=0 [system.cpu.isa] type=ArmISA +decoderFlavour=Generic eventq_index=0 fpsid=1090793632 id_aa64afr0_el1=0 @@ -271,9 +276,9 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=20 is_read_only=false max_miss_count=0 @@ -287,6 +292,7 @@ system=system tags=system.cpu.l2cache.tags tgts_per_mshr=12 write_buffers=8 +writeback_clean=false cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] @@ -302,12 +308,14 @@ size=2097152 [system.cpu.toL2Bus] type=CoherentXBar +children=snoop_filter clk_domain=system.cpu_clk_domain eventq_index=0 forward_latency=0 frontend_latency=1 +point_of_coherency=false response_latency=1 -snoop_filter=Null +snoop_filter=system.cpu.toL2Bus.snoop_filter snoop_response_latency=1 system=system use_default_range=false @@ -315,6 +323,13 @@ width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port +[system.cpu.toL2Bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + [system.cpu.tracer] type=ExeTracer eventq_index=0 @@ -329,9 +344,9 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/parser +executable=/dist/m5/cpu2000/binaries/arm/linux/parser gid=100 -input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in +input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in kvmInSE=false max_stack_size=67108864 output=cout @@ -364,6 +379,7 @@ clk_domain=system.clk_domain eventq_index=0 forward_latency=4 frontend_latency=3 +point_of_coherency=true response_latency=2 snoop_filter=Null snoop_response_latency=4 diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/simerr b/tests/long/se/20.parser/ref/arm/linux/simple-timing/simerr index 1a4f96712..e69de29bb 100755 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/simerr +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/simerr @@ -1 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout b/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout index 36fd0e9c5..7596ee7d2 100755 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout @@ -1,12 +1,14 @@ +Redirecting stdout to build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing/simout +Redirecting stderr to build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2014 12:08:08 -gem5 started Jan 23 2014 17:21:27 -gem5 executing on u200540-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing +gem5 compiled Mar 16 2016 15:51:04 +gem5 started Mar 16 2016 15:51:37 +gem5 executing on dinar2c11, pid 15211 +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing -re /home/stever/gem5-public/tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing + Global frequency set at 1000000000000 ticks per second - 0: system.cpu.isa: ISA system set to: 0 0x6322040 info: Entering event queue @ 0. Starting simulation... Reading the dictionary files: ************************************************* @@ -68,4 +70,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 717366012000 because target called exit() +Exiting @ tick 708539449500 because target called exit() diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt index d35883c7b..0a916209d 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.708526 # Number of seconds simulated -sim_ticks 708526400500 # Number of ticks simulated -final_tick 708526400500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.708539 # Number of seconds simulated +sim_ticks 708539449500 # Number of ticks simulated +final_tick 708539449500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 942956 # Simulator instruction rate (inst/s) -host_op_rate 1021179 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1323022561 # Simulator tick rate (ticks/s) -host_mem_usage 320452 # Number of bytes of host memory used -host_seconds 535.54 # Real time elapsed on the host -sim_insts 504986854 # Number of instructions simulated -sim_ops 546878105 # Number of ops (including micro ops) simulated +host_inst_rate 318121 # Simulator instruction rate (inst/s) +host_op_rate 344511 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 446353500 # Simulator tick rate (ticks/s) +host_mem_usage 303968 # Number of bytes of host memory used +host_seconds 1587.40 # Real time elapsed on the host +sim_insts 504984064 # Number of instructions simulated +sim_ops 546875315 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 147392 # Number of bytes read from this memory @@ -25,17 +25,17 @@ system.physmem.num_reads::cpu.data 140061 # Nu system.physmem.num_reads::total 142364 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 96330 # Number of write requests responded to by this memory system.physmem.num_writes::total 96330 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 208026 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12651475 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 12859501 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 208026 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 208026 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 8701327 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 8701327 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 8701327 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 208026 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12651475 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 21560828 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 208022 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12651242 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 12859264 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 208022 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 208022 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 8701167 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 8701167 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 8701167 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 208022 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12651242 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 21560431 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -154,33 +154,33 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 1417052801 # number of cpu cycles simulated +system.cpu.numCycles 1417078899 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 504986854 # Number of instructions committed -system.cpu.committedOps 546878105 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 448454356 # Number of integer alu accesses +system.cpu.committedInsts 504984064 # Number of instructions committed +system.cpu.committedOps 546875315 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 448447005 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses system.cpu.num_func_calls 19311615 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 90667196 # number of instructions that are conditional controls -system.cpu.num_int_insts 448454356 # number of integer instructions +system.cpu.num_conditional_control_insts 90670594 # number of instructions that are conditional controls +system.cpu.num_int_insts 448447005 # number of integer instructions system.cpu.num_fp_insts 16 # number of float instructions -system.cpu.num_int_register_reads 748355652 # number of times the integer registers were read -system.cpu.num_int_register_writes 290003067 # number of times the integer registers were written +system.cpu.num_int_register_reads 748339662 # number of times the integer registers were read +system.cpu.num_int_register_writes 289993515 # number of times the integer registers were written system.cpu.num_fp_register_reads 16 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 1984297859 # number of times the CC registers were read -system.cpu.num_cc_register_writes 344080722 # number of times the CC registers were written -system.cpu.num_mem_refs 172745235 # number of memory refs -system.cpu.num_load_insts 115884756 # Number of load instructions -system.cpu.num_store_insts 56860479 # Number of store instructions +system.cpu.num_cc_register_reads 1984285070 # number of times the CC registers were read +system.cpu.num_cc_register_writes 344062197 # number of times the CC registers were written +system.cpu.num_mem_refs 172743505 # number of memory refs +system.cpu.num_load_insts 115883283 # Number of load instructions +system.cpu.num_store_insts 56860222 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 1417052800.998000 # Number of busy cycles +system.cpu.num_busy_cycles 1417078898.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 121548302 # Number of branches fetched +system.cpu.Branches 121552863 # Number of branches fetched system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 375610922 68.46% 68.46% # Class of executed instruction +system.cpu.op_class::IntAlu 375609862 68.46% 68.46% # Class of executed instruction system.cpu.op_class::IntMult 339219 0.06% 68.52% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 68.52% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 68.52% # Class of executed instruction @@ -209,18 +209,18 @@ system.cpu.op_class::SimdFloatMisc 3 0.00% 68.52% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 68.52% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.52% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::MemRead 115884756 21.12% 89.64% # Class of executed instruction -system.cpu.op_class::MemWrite 56860479 10.36% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 115883283 21.12% 89.64% # Class of executed instruction +system.cpu.op_class::MemWrite 56860222 10.36% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 548695379 # Class of executed instruction -system.cpu.dcache.tags.replacements 1134822 # number of replacements -system.cpu.dcache.tags.tagsinuse 4065.260615 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 170180456 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1138918 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 149.422922 # Average number of references to valid blocks. +system.cpu.op_class::total 548692589 # Class of executed instruction +system.cpu.dcache.tags.replacements 1136276 # number of replacements +system.cpu.dcache.tags.tagsinuse 4065.261181 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 170177272 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1140372 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 149.229613 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 11750119500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4065.260615 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 4065.261181 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.992495 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.992495 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -230,72 +230,72 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 343 system.cpu.dcache.tags.age_task_id_blocks_1024::3 3546 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 165 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 343777666 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 343777666 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 113317758 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 113317758 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 53883046 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 53883046 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 343775660 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 343775660 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 113315079 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 113315079 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 53882541 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 53882541 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 2570 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 2570 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 167200804 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 167200804 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 167203374 # number of overall hits -system.cpu.dcache.overall_hits::total 167203374 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 782657 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 782657 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 356260 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 356260 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 167197620 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 167197620 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 167200190 # number of overall hits +system.cpu.dcache.overall_hits::total 167200190 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 783863 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 783863 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 356508 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 356508 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 1138917 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1138917 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1138918 # number of overall misses -system.cpu.dcache.overall_misses::total 1138918 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 12104797500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 12104797500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9574077500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9574077500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 21678875000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 21678875000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 21678875000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 21678875000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 114100415 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 114100415 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 1140371 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1140371 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1140372 # number of overall misses +system.cpu.dcache.overall_misses::total 1140372 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 12120585500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 12120585500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9577302500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9577302500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 21697888000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 21697888000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 21697888000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 21697888000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 114098942 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 114098942 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 54239049 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 54239049 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 2571 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::total 2571 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 168339721 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 168339721 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 168342292 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 168342292 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.006859 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.006859 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006568 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.006568 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 168337991 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 168337991 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 168340562 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 168340562 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.006870 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.006870 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006573 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.006573 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000389 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.000389 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.006766 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.006766 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.006765 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.006765 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15466.286636 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15466.286636 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26873.849155 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 26873.849155 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 19034.639925 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 19034.639925 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 19034.623213 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 19034.623213 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.006774 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.006774 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.006774 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.006774 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15462.632501 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15462.632501 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26864.200803 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 26864.200803 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 19027.042954 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 19027.042954 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 19027.026269 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 19027.026269 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -304,58 +304,58 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1064678 # number of writebacks -system.cpu.dcache.writebacks::total 1064678 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 782657 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 782657 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356260 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 356260 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 1065708 # number of writebacks +system.cpu.dcache.writebacks::total 1065708 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 783863 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 783863 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356508 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 356508 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1138917 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1138917 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1138918 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1138918 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11322140500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 11322140500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9217817500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 9217817500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 1140371 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1140371 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1140372 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1140372 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11336722500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 11336722500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9220794500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 9220794500 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 61000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 61000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20539958000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 20539958000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20540019000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 20540019000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006859 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006859 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006568 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006568 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20557517000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 20557517000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20557578000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 20557578000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006870 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006870 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006573 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006573 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000389 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000389 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006766 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006766 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006765 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006765 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14466.286636 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14466.286636 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25873.849155 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25873.849155 # average WriteReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006774 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006774 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006774 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006774 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14462.632501 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14462.632501 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25864.200803 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25864.200803 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61000 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18034.639925 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 18034.639925 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18034.677650 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 18034.677650 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18027.042954 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 18027.042954 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18027.080637 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 18027.080637 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 9788 # number of replacements -system.cpu.icache.tags.tagsinuse 983.180611 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 516599856 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 983.198764 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 516597066 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 11521 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 44839.845152 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 44839.602986 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 983.180611 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.480069 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.480069 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 983.198764 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.480078 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.480078 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1733 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id @@ -363,44 +363,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 24 system.cpu.icache.tags.age_task_id_blocks_1024::3 256 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1402 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.846191 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 1033234275 # Number of tag accesses -system.cpu.icache.tags.data_accesses 1033234275 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 516599856 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 516599856 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 516599856 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 516599856 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 516599856 # number of overall hits -system.cpu.icache.overall_hits::total 516599856 # number of overall hits +system.cpu.icache.tags.tag_accesses 1033228695 # Number of tag accesses +system.cpu.icache.tags.data_accesses 1033228695 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 516597066 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 516597066 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 516597066 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 516597066 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 516597066 # number of overall hits +system.cpu.icache.overall_hits::total 516597066 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 11521 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 11521 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 11521 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 11521 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 11521 # number of overall misses system.cpu.icache.overall_misses::total 11521 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 263208000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 263208000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 263208000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 263208000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 263208000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 263208000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 516611377 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 516611377 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 516611377 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 516611377 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 516611377 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 516611377 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 263211000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 263211000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 263211000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 263211000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 263211000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 263211000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 516608587 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 516608587 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 516608587 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 516608587 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 516608587 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 516608587 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000022 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22845.933513 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 22845.933513 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 22845.933513 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 22845.933513 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 22845.933513 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 22845.933513 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22846.193907 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 22846.193907 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 22846.193907 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 22846.193907 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 22846.193907 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 22846.193907 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -417,62 +417,62 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 11521 system.cpu.icache.demand_mshr_misses::total 11521 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 11521 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 11521 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 251687000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 251687000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 251687000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 251687000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 251687000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 251687000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 251690000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 251690000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 251690000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 251690000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 251690000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 251690000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000022 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000022 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21845.933513 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21845.933513 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21845.933513 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 21845.933513 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21845.933513 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 21845.933513 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21846.193907 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21846.193907 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21846.193907 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 21846.193907 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21846.193907 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 21846.193907 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 110394 # number of replacements -system.cpu.l2cache.tags.tagsinuse 27250.637055 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1744409 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 27252.086651 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1747015 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 141582 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 12.320839 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 339114860000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 23374.350264 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 240.190674 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 3636.096117 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.713329 # Average percentage of cache occupancy +system.cpu.l2cache.tags.avg_refs 12.339245 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 339115608000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 23375.830047 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 240.203585 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 3636.053019 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.713374 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007330 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.110965 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.831623 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.110964 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.831668 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 31188 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 283 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3657 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27176 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.951782 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 18830546 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 18830546 # Number of data accesses -system.cpu.l2cache.WritebackDirty_hits::writebacks 1064678 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 1064678 # number of WritebackDirty hits +system.cpu.l2cache.tags.tag_accesses 18853226 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 18853226 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 1065708 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 1065708 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 9751 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::total 9751 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 255472 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 255472 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 255720 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 255720 # number of ReadExReq hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 9218 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 9218 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 743385 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 743385 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 744591 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 744591 # number of ReadSharedReq hits system.cpu.l2cache.demand_hits::cpu.inst 9218 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 998857 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1008075 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1000311 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1009529 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 9218 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 998857 # number of overall hits -system.cpu.l2cache.overall_hits::total 1008075 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1000311 # number of overall hits +system.cpu.l2cache.overall_hits::total 1009529 # number of overall hits system.cpu.l2cache.ReadExReq_misses::cpu.data 100788 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 100788 # number of ReadExReq misses system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2303 # number of ReadCleanReq misses @@ -485,58 +485,58 @@ system.cpu.l2cache.demand_misses::total 142364 # nu system.cpu.l2cache.overall_misses::cpu.inst 2303 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 140061 # number of overall misses system.cpu.l2cache.overall_misses::total 142364 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6000938500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6000938500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 137230000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 137230000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2339453000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 2339453000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 137230000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8340391500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 8477621500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 137230000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8340391500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 8477621500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 1064678 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 1064678 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6000939500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6000939500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 137232000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 137232000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2339459000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 2339459000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 137232000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8340398500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 8477630500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 137232000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8340398500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 8477630500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 1065708 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 1065708 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 9751 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 9751 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 356260 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 356260 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 356508 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 356508 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 11521 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::total 11521 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 782658 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 782658 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 783864 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 783864 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 11521 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1138918 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1150439 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1140372 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1151893 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 11521 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1138918 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1150439 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.282906 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.282906 # miss rate for ReadExReq accesses +system.cpu.l2cache.overall_accesses::cpu.data 1140372 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1151893 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.282709 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.282709 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.199896 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.199896 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.050179 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.050179 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.050102 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.050102 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.199896 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.122977 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.123748 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.122820 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.123591 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.199896 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.122977 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.123748 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59540.208160 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59540.208160 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59587.494572 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59587.494572 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59568.991419 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59568.991419 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59587.494572 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59548.278964 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 59548.913349 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59587.494572 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59548.278964 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 59548.913349 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.122820 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.123591 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59540.218082 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59540.218082 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59588.363005 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59588.363005 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59569.144196 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59569.144196 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59588.363005 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59548.328942 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 59548.976567 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59588.363005 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59548.328942 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 59548.976567 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -561,82 +561,82 @@ system.cpu.l2cache.demand_mshr_misses::total 142364 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2303 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 140061 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 142364 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4993058500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4993058500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 114200000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 114200000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1946723000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1946723000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 114200000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6939781500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 7053981500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 114200000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6939781500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 7053981500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4993059500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4993059500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 114202000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 114202000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1946729000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1946729000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 114202000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6939788500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 7053990500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 114202000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6939788500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 7053990500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.282906 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.282906 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.282709 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.282709 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.199896 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.199896 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.050179 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.050179 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.050102 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.050102 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.199896 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.122977 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.123748 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.122820 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.123591 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.199896 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.122977 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.123748 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49540.208160 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49540.208160 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49587.494572 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49587.494572 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49568.991419 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49568.991419 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49587.494572 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49548.278964 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49548.913349 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49587.494572 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49548.278964 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49548.913349 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.122820 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.123591 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49540.218082 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49540.218082 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49588.363005 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49588.363005 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49569.144196 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49569.144196 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49588.363005 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49548.328942 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49548.976567 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49588.363005 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49548.328942 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49548.976567 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 2295049 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 1144662 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3461 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 2297957 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 1146116 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3565 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 2146 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2145 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 794179 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 1161008 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 795385 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 1162038 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 9788 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 84208 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 356260 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 356260 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 84632 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 356508 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 356508 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 11521 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 782658 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 783864 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 32830 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3412658 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3445488 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3417020 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 3449850 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1363776 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141030144 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 142393920 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141189120 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 142552896 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 110394 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 1260833 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.004489 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.066862 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 1262287 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.004566 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.067432 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1255174 99.55% 99.55% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 5658 0.45% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1256524 99.54% 99.54% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 5762 0.46% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1260833 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2221990500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1262287 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2224474500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 17281500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1708377000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1710558000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) system.membus.trans_dist::ReadResp 41576 # Transaction distribution system.membus.trans_dist::WritebackDirty 96330 # Transaction distribution @@ -659,7 +659,7 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 250615 # Request fanout histogram -system.membus.reqLayer0.occupancy 644475328 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 644476328 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.respLayer1.occupancy 711820000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini index bdb9561f0..9f3703298 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true @@ -24,6 +25,7 @@ mem_mode=atomic mem_ranges= memories=system.physmem mmap_using_noreserve=false +multi_thread=false num_work_ids=16 readfile= symbolfile= @@ -147,9 +149,9 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/parser +executable=/dist/m5/cpu2000/binaries/x86/linux/parser gid=100 -input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in +input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in kvmInSE=false max_stack_size=67108864 output=cout @@ -182,6 +184,7 @@ clk_domain=system.clk_domain eventq_index=0 forward_latency=4 frontend_latency=3 +point_of_coherency=true response_latency=2 snoop_filter=Null snoop_response_latency=4 diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simerr b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simerr index 1a4f96712..e69de29bb 100755 --- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simerr +++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simerr @@ -1 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout index cbb107c47..ff0a5c91f 100755 --- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout +++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout @@ -1,10 +1,13 @@ +Redirecting stdout to build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic/simout +Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:10:34 -gem5 started Jan 22 2014 20:48:32 -gem5 executing on u200540-lin -command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic +gem5 compiled Mar 16 2016 15:38:19 +gem5 started Mar 16 2016 15:38:59 +gem5 executing on dinar2c11, pid 14361 +command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic -re /home/stever/gem5-public/tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic + Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -69,4 +72,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 885229328000 because target called exit() +Exiting @ tick 885256008500 because target called exit() diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt index 1702837e8..a821d05f5 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt @@ -1,72 +1,72 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.885229 # Number of seconds simulated -sim_ticks 885229328000 # Number of ticks simulated -final_tick 885229328000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.885256 # Number of seconds simulated +sim_ticks 885256008500 # Number of ticks simulated +final_tick 885256008500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1361574 # Simulator instruction rate (inst/s) -host_op_rate 2517703 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1457659146 # Simulator tick rate (ticks/s) -host_mem_usage 313840 # Number of bytes of host memory used -host_seconds 607.30 # Real time elapsed on the host -sim_insts 826877110 # Number of instructions simulated -sim_ops 1528988702 # Number of ops (including micro ops) simulated +host_inst_rate 362789 # Simulator instruction rate (inst/s) +host_op_rate 670835 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 388389023 # Simulator tick rate (ticks/s) +host_mem_usage 304128 # Number of bytes of host memory used +host_seconds 2279.30 # Real time elapsed on the host +sim_insts 826906380 # Number of instructions simulated +sim_ops 1529035683 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 8546776520 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 2285655658 # Number of bytes read from this memory -system.physmem.bytes_read::total 10832432178 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 8546776520 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 8546776520 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 991849462 # Number of bytes written to this memory -system.physmem.bytes_written::total 991849462 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1068347065 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 384102186 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1452449251 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 149160202 # Number of write requests responded to by this memory -system.physmem.num_writes::total 149160202 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 9654872754 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2581992695 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 12236865449 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 9654872754 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 9654872754 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1120443517 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1120443517 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 9654872754 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3702436212 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 13357308966 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 8547061720 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 2285750420 # Number of bytes read from this memory +system.physmem.bytes_read::total 10832812140 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 8547061720 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 8547061720 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 991875282 # Number of bytes written to this memory +system.physmem.bytes_written::total 991875282 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1068382715 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 384117854 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1452500569 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 149164510 # Number of write requests responded to by this memory +system.physmem.num_writes::total 149164510 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 9654903935 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2582021921 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 12236925856 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 9654903935 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 9654903935 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1120438915 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1120438915 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 9654903935 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3702460837 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 13357364772 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 1770458657 # number of cpu cycles simulated +system.cpu.numCycles 1770512018 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 826877110 # Number of instructions committed -system.cpu.committedOps 1528988702 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1526605510 # Number of integer alu accesses +system.cpu.committedInsts 826906380 # Number of instructions committed +system.cpu.committedOps 1529035683 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 1526653037 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 35346287 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 92658795 # number of instructions that are conditional controls -system.cpu.num_int_insts 1526605510 # number of integer instructions +system.cpu.num_conditional_control_insts 92662756 # number of instructions that are conditional controls +system.cpu.num_int_insts 1526653037 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 3293771378 # number of times the integer registers were read -system.cpu.num_int_register_writes 1237355109 # number of times the integer registers were written +system.cpu.num_int_register_reads 3293861747 # number of times the integer registers were read +system.cpu.num_int_register_writes 1237389453 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 561334882 # number of times the CC registers were read -system.cpu.num_cc_register_writes 376685745 # number of times the CC registers were written -system.cpu.num_mem_refs 533262343 # number of memory refs -system.cpu.num_load_insts 384102157 # Number of load instructions -system.cpu.num_store_insts 149160186 # Number of store instructions +system.cpu.num_cc_register_reads 561356848 # number of times the CC registers were read +system.cpu.num_cc_register_writes 376698535 # number of times the CC registers were written +system.cpu.num_mem_refs 533282319 # number of memory refs +system.cpu.num_load_insts 384117825 # Number of load instructions +system.cpu.num_store_insts 149164494 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 1770458656.998000 # Number of busy cycles +system.cpu.num_busy_cycles 1770512017.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 149758583 # Number of branches fetched -system.cpu.op_class::No_OpClass 1819099 0.12% 0.12% # Class of executed instruction -system.cpu.op_class::IntAlu 989721890 64.73% 64.85% # Class of executed instruction +system.cpu.Branches 149762544 # Number of branches fetched +system.cpu.op_class::No_OpClass 1818553 0.12% 0.12% # Class of executed instruction +system.cpu.op_class::IntAlu 989751625 64.73% 64.85% # Class of executed instruction system.cpu.op_class::IntMult 306834 0.02% 64.87% # Class of executed instruction -system.cpu.op_class::IntDiv 3878536 0.25% 65.12% # Class of executed instruction +system.cpu.op_class::IntDiv 3876352 0.25% 65.12% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 65.12% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 65.12% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 65.12% # Class of executed instruction @@ -93,35 +93,35 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 65.12% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 65.12% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.12% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.12% # Class of executed instruction -system.cpu.op_class::MemRead 384102157 25.12% 90.24% # Class of executed instruction -system.cpu.op_class::MemWrite 149160186 9.76% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 384117825 25.12% 90.24% # Class of executed instruction +system.cpu.op_class::MemWrite 149164494 9.76% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 1528988702 # Class of executed instruction -system.membus.trans_dist::ReadReq 1452449251 # Transaction distribution -system.membus.trans_dist::ReadResp 1452449251 # Transaction distribution -system.membus.trans_dist::WriteReq 149160202 # Transaction distribution -system.membus.trans_dist::WriteResp 149160202 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 2136694130 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.icache_port::total 2136694130 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 1066524776 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::total 1066524776 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 3203218906 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 8546776520 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::total 8546776520 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 3277505120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::total 3277505120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 11824281640 # Cumulative packet size per connected master and slave (bytes) +system.cpu.op_class::total 1529035683 # Class of executed instruction +system.membus.trans_dist::ReadReq 1452500569 # Transaction distribution +system.membus.trans_dist::ReadResp 1452500569 # Transaction distribution +system.membus.trans_dist::WriteReq 149164510 # Transaction distribution +system.membus.trans_dist::WriteResp 149164510 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 2136765430 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.icache_port::total 2136765430 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 1066564728 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::total 1066564728 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 3203330158 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 8547061720 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::total 8547061720 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 3277625702 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::total 3277625702 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 11824687422 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 1601609453 # Request fanout histogram -system.membus.snoop_fanout::mean 0.667046 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.471270 # Request fanout histogram +system.membus.snoop_fanout::samples 1601665079 # Request fanout histogram +system.membus.snoop_fanout::mean 0.667045 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.471271 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 533262388 33.30% 33.30% # Request fanout histogram -system.membus.snoop_fanout::1 1068347065 66.70% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 533282364 33.30% 33.30% # Request fanout histogram +system.membus.snoop_fanout::1 1068382715 66.70% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 1601609453 # Request fanout histogram +system.membus.snoop_fanout::total 1601665079 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini b/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini index bab78d9da..4292720d5 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true @@ -24,6 +25,7 @@ mem_mode=timing mem_ranges= memories=system.physmem mmap_using_noreserve=false +multi_thread=false num_work_ids=16 readfile= symbolfile= @@ -89,9 +91,9 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=false max_miss_count=0 @@ -105,6 +107,7 @@ system=system tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 +writeback_clean=false cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.slave[1] @@ -139,9 +142,9 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=true max_miss_count=0 @@ -155,6 +158,7 @@ system=system tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 +writeback_clean=true cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.slave[0] @@ -205,9 +209,9 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=20 is_read_only=false max_miss_count=0 @@ -221,6 +225,7 @@ system=system tags=system.cpu.l2cache.tags tgts_per_mshr=12 write_buffers=8 +writeback_clean=false cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] @@ -236,12 +241,14 @@ size=2097152 [system.cpu.toL2Bus] type=CoherentXBar +children=snoop_filter clk_domain=system.cpu_clk_domain eventq_index=0 forward_latency=0 frontend_latency=1 +point_of_coherency=false response_latency=1 -snoop_filter=Null +snoop_filter=system.cpu.toL2Bus.snoop_filter snoop_response_latency=1 system=system use_default_range=false @@ -249,6 +256,13 @@ width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port +[system.cpu.toL2Bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + [system.cpu.tracer] type=ExeTracer eventq_index=0 @@ -263,9 +277,9 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/parser +executable=/dist/m5/cpu2000/binaries/x86/linux/parser gid=100 -input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in +input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in kvmInSE=false max_stack_size=67108864 output=cout @@ -298,6 +312,7 @@ clk_domain=system.clk_domain eventq_index=0 forward_latency=4 frontend_latency=3 +point_of_coherency=true response_latency=2 snoop_filter=Null snoop_response_latency=4 diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simerr b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simerr index 1a4f96712..e69de29bb 100755 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simerr +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simerr @@ -1 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout index 530ac97a0..cd12e9ca0 100755 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout @@ -1,10 +1,13 @@ +Redirecting stdout to build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing/simout +Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:10:34 -gem5 started Jan 22 2014 20:57:08 -gem5 executing on u200540-lin -command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing +gem5 compiled Mar 16 2016 15:38:19 +gem5 started Mar 16 2016 15:38:49 +gem5 executing on dinar2c11, pid 14355 +command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing -re /home/stever/gem5-public/tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing + Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -69,4 +72,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 1647872849000 because target called exit() +Exiting @ tick 1650600522500 because target called exit() diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt index 1b9df2638..58e8c99ef 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt @@ -1,73 +1,73 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.650527 # Number of seconds simulated -sim_ticks 1650526667500 # Number of ticks simulated -final_tick 1650526667500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.650601 # Number of seconds simulated +sim_ticks 1650600522500 # Number of ticks simulated +final_tick 1650600522500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 726731 # Simulator instruction rate (inst/s) -host_op_rate 1343807 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1450624585 # Simulator tick rate (ticks/s) -host_mem_usage 327760 # Number of bytes of host memory used -host_seconds 1137.80 # Real time elapsed on the host -sim_insts 826877110 # Number of instructions simulated -sim_ops 1528988702 # Number of ops (including micro ops) simulated +host_inst_rate 236277 # Simulator instruction rate (inst/s) +host_op_rate 436901 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 471636555 # Simulator tick rate (ticks/s) +host_mem_usage 314152 # Number of bytes of host memory used +host_seconds 3499.73 # Real time elapsed on the host +sim_insts 826906380 # Number of instructions simulated +sim_ops 1529035683 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 115776 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24258944 # Number of bytes read from this memory -system.physmem.bytes_read::total 24374720 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24258880 # Number of bytes read from this memory +system.physmem.bytes_read::total 24374656 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 115776 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 115776 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18765248 # Number of bytes written to this memory -system.physmem.bytes_written::total 18765248 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 18765184 # Number of bytes written to this memory +system.physmem.bytes_written::total 18765184 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 1809 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 379046 # Number of read requests responded to by this memory -system.physmem.num_reads::total 380855 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 293207 # Number of write requests responded to by this memory -system.physmem.num_writes::total 293207 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 70145 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 14697699 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14767844 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 70145 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 70145 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 11369249 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 11369249 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 11369249 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 70145 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 14697699 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 26137092 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::cpu.data 379045 # Number of read requests responded to by this memory +system.physmem.num_reads::total 380854 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 293206 # Number of write requests responded to by this memory +system.physmem.num_writes::total 293206 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 70142 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 14697002 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14767144 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 70142 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 70142 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 11368701 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 11368701 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 11368701 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 70142 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 14697002 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 26135845 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 3301053335 # number of cpu cycles simulated +system.cpu.numCycles 3301201045 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 826877110 # Number of instructions committed -system.cpu.committedOps 1528988702 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1526605510 # Number of integer alu accesses +system.cpu.committedInsts 826906380 # Number of instructions committed +system.cpu.committedOps 1529035683 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 1526653037 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 35346287 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 92658795 # number of instructions that are conditional controls -system.cpu.num_int_insts 1526605510 # number of integer instructions +system.cpu.num_conditional_control_insts 92662756 # number of instructions that are conditional controls +system.cpu.num_int_insts 1526653037 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 3293771378 # number of times the integer registers were read -system.cpu.num_int_register_writes 1237355109 # number of times the integer registers were written +system.cpu.num_int_register_reads 3293861747 # number of times the integer registers were read +system.cpu.num_int_register_writes 1237389453 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 561334882 # number of times the CC registers were read -system.cpu.num_cc_register_writes 376685745 # number of times the CC registers were written -system.cpu.num_mem_refs 533262343 # number of memory refs -system.cpu.num_load_insts 384102157 # Number of load instructions -system.cpu.num_store_insts 149160186 # Number of store instructions +system.cpu.num_cc_register_reads 561356848 # number of times the CC registers were read +system.cpu.num_cc_register_writes 376698535 # number of times the CC registers were written +system.cpu.num_mem_refs 533282319 # number of memory refs +system.cpu.num_load_insts 384117825 # Number of load instructions +system.cpu.num_store_insts 149164494 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 3301053334.998000 # Number of busy cycles +system.cpu.num_busy_cycles 3301201044.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 149758583 # Number of branches fetched -system.cpu.op_class::No_OpClass 1819099 0.12% 0.12% # Class of executed instruction -system.cpu.op_class::IntAlu 989721890 64.73% 64.85% # Class of executed instruction +system.cpu.Branches 149762544 # Number of branches fetched +system.cpu.op_class::No_OpClass 1818553 0.12% 0.12% # Class of executed instruction +system.cpu.op_class::IntAlu 989751625 64.73% 64.85% # Class of executed instruction system.cpu.op_class::IntMult 306834 0.02% 64.87% # Class of executed instruction -system.cpu.op_class::IntDiv 3878536 0.25% 65.12% # Class of executed instruction +system.cpu.op_class::IntDiv 3876352 0.25% 65.12% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 65.12% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 65.12% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 65.12% # Class of executed instruction @@ -94,18 +94,18 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 65.12% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 65.12% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.12% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.12% # Class of executed instruction -system.cpu.op_class::MemRead 384102157 25.12% 90.24% # Class of executed instruction -system.cpu.op_class::MemWrite 149160186 9.76% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 384117825 25.12% 90.24% # Class of executed instruction +system.cpu.op_class::MemWrite 149164494 9.76% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 1528988702 # Class of executed instruction -system.cpu.dcache.tags.replacements 2514362 # number of replacements -system.cpu.dcache.tags.tagsinuse 4086.386622 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 530743930 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2518458 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 210.741624 # Average number of references to valid blocks. +system.cpu.op_class::total 1529035683 # Class of executed instruction +system.cpu.dcache.tags.replacements 2515885 # number of replacements +system.cpu.dcache.tags.tagsinuse 4086.387052 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 530762383 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2519981 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 210.621581 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 8246025500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4086.386622 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 4086.387052 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.997653 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.997653 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -115,56 +115,56 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 29 system.cpu.dcache.tags.age_task_id_blocks_1024::3 4038 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1069043234 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1069043234 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 382374772 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 382374772 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148369158 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148369158 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 530743930 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 530743930 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 530743930 # number of overall hits -system.cpu.dcache.overall_hits::total 530743930 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1727414 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1727414 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 791044 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 791044 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2518458 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2518458 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2518458 # number of overall misses -system.cpu.dcache.overall_misses::total 2518458 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 30918235500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 30918235500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 20395021500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 20395021500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 51313257000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 51313257000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 51313257000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 51313257000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 384102186 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 384102186 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 533262388 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 533262388 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 533262388 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 533262388 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004497 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004497 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005303 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.005303 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.004723 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.004723 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.004723 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.004723 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17898.567165 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17898.567165 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25782.410966 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 25782.410966 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 20374.871052 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 20374.871052 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 20374.871052 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 20374.871052 # average overall miss latency +system.cpu.dcache.tags.tag_accesses 1069084709 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1069084709 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 382389020 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 382389020 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148373363 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148373363 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 530762383 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 530762383 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 530762383 # number of overall hits +system.cpu.dcache.overall_hits::total 530762383 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1728834 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1728834 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 791147 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 791147 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2519981 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2519981 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2519981 # number of overall misses +system.cpu.dcache.overall_misses::total 2519981 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 30936646500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 30936646500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 20396358500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 20396358500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 51333005000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 51333005000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 51333005000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 51333005000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 384117854 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 384117854 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 149164510 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 149164510 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 533282364 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 533282364 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 533282364 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 533282364 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004501 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004501 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005304 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.005304 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.004725 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.004725 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.004725 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.004725 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17894.515321 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17894.515321 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25780.744286 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 25780.744286 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 20370.393666 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 20370.393666 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 20370.393666 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 20370.393666 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -173,50 +173,50 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2323200 # number of writebacks -system.cpu.dcache.writebacks::total 2323200 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1727414 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1727414 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 791044 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 791044 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2518458 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2518458 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2518458 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2518458 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29190821500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 29190821500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19603977500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 19603977500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 48794799000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 48794799000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 48794799000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 48794799000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004497 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004497 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005303 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005303 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.004723 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.004723 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16898.567165 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16898.567165 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24782.410966 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24782.410966 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19374.871052 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 19374.871052 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19374.871052 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 19374.871052 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 2324237 # number of writebacks +system.cpu.dcache.writebacks::total 2324237 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1728834 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1728834 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 791147 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 791147 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2519981 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2519981 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2519981 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2519981 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29207812500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 29207812500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19605211500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 19605211500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 48813024000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 48813024000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 48813024000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 48813024000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004501 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004501 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005304 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005304 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.004725 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.004725 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.004725 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.004725 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16894.515321 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16894.515321 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24780.744286 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24780.744286 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19370.393666 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 19370.393666 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19370.393666 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 19370.393666 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1253 # number of replacements -system.cpu.icache.tags.tagsinuse 881.361122 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1068344251 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 881.377882 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1068379901 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 2814 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 379653.251955 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 379665.920753 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 881.361122 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.430352 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.430352 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 881.377882 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.430360 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.430360 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1561 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id @@ -224,44 +224,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 7 system.cpu.icache.tags.age_task_id_blocks_1024::3 8 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1507 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.762207 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 2136696944 # Number of tag accesses -system.cpu.icache.tags.data_accesses 2136696944 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 1068344251 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1068344251 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1068344251 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1068344251 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1068344251 # number of overall hits -system.cpu.icache.overall_hits::total 1068344251 # number of overall hits +system.cpu.icache.tags.tag_accesses 2136768244 # Number of tag accesses +system.cpu.icache.tags.data_accesses 2136768244 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 1068379901 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1068379901 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1068379901 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1068379901 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1068379901 # number of overall hits +system.cpu.icache.overall_hits::total 1068379901 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 2814 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 2814 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 2814 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 2814 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 2814 # number of overall misses system.cpu.icache.overall_misses::total 2814 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 125252000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 125252000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 125252000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 125252000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 125252000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 125252000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1068347065 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1068347065 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1068347065 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1068347065 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1068347065 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1068347065 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 125256000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 125256000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 125256000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 125256000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 125256000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 125256000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1068382715 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1068382715 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1068382715 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1068382715 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1068382715 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1068382715 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000003 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000003 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000003 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000003 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000003 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000003 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44510.305615 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 44510.305615 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 44510.305615 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 44510.305615 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 44510.305615 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 44510.305615 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44511.727079 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 44511.727079 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 44511.727079 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 44511.727079 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 44511.727079 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 44511.727079 # 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number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 122438000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 122442000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 122442000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 122442000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 122442000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 122442000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 122442000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # 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number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 380854 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10214625500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10214625500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 89567000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 89567000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 8548146000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 8548146000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 89567000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 18762771500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 18852338500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 89567000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 18762771500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 18852338500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.260865 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.260865 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.260831 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.260831 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.642857 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.642857 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.099970 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.099970 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.099888 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.099888 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.642857 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150507 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.151057 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150416 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.150965 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.642857 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150507 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.151057 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.026653 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.026653 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49509.397457 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49509.397457 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500.234524 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500.234524 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49509.397457 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500.121357 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.165417 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49509.397457 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500.121357 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.165417 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150416 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.150965 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.016961 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.016961 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49511.885019 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49511.885019 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500.234526 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500.234526 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49511.885019 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500.116081 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.171982 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49511.885019 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500.116081 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.171982 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 5036887 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2515615 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 5039933 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2517138 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 1729 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1729 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 1730228 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 2616408 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1731648 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 2617444 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 1253 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 246392 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 791044 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 791044 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 246878 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 791147 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 791147 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 2814 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1727414 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1728834 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6881 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7551278 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7558159 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7555847 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7562728 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 260288 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 309866112 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 310126400 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 348438 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 2869710 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 310029952 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 310290240 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 348437 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 2871232 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.000602 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.024538 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.024532 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2867981 99.94% 99.94% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2869503 99.94% 99.94% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 1729 0.06% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2869710 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4842896500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2871232 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4845456500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 4221000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3777687000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3779971500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.trans_dist::ReadResp 174499 # Transaction distribution -system.membus.trans_dist::WritebackDirty 293207 # Transaction distribution +system.membus.trans_dist::ReadResp 174498 # Transaction distribution +system.membus.trans_dist::WritebackDirty 293206 # Transaction distribution system.membus.trans_dist::CleanEvict 53507 # Transaction distribution system.membus.trans_dist::ReadExReq 206356 # Transaction distribution system.membus.trans_dist::ReadExResp 206356 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 174499 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1108424 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1108424 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1108424 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43139968 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43139968 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 43139968 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 174498 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1108421 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1108421 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1108421 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43139840 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43139840 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 43139840 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 727569 # Request fanout histogram +system.membus.snoop_fanout::samples 727567 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 727569 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 727567 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 727569 # Request fanout histogram -system.membus.reqLayer0.occupancy 1900428500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 727567 # Request fanout histogram +system.membus.reqLayer0.occupancy 1900421500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 1904275000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1904270000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- |