diff options
Diffstat (limited to 'tests/long/se/20.parser')
4 files changed, 1668 insertions, 1669 deletions
diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index c258cba07..d43c28cd4 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,103 +1,103 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.202255 # Number of seconds simulated -sim_ticks 202254809500 # Number of ticks simulated -final_tick 202254809500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.202350 # Number of seconds simulated +sim_ticks 202349747500 # Number of ticks simulated +final_tick 202349747500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 148306 # Simulator instruction rate (inst/s) -host_op_rate 167206 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 59369383 # Simulator tick rate (ticks/s) -host_mem_usage 288744 # Number of bytes of host memory used -host_seconds 3406.72 # Real time elapsed on the host +host_inst_rate 166059 # Simulator instruction rate (inst/s) +host_op_rate 187221 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 66507382 # Simulator tick rate (ticks/s) +host_mem_usage 250660 # Number of bytes of host memory used +host_seconds 3042.52 # Real time elapsed on the host sim_insts 505237723 # Number of instructions simulated sim_ops 569624283 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 216064 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9266496 # Number of bytes read from this memory -system.physmem.bytes_read::total 9482560 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 216064 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 216064 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6247616 # Number of bytes written to this memory -system.physmem.bytes_written::total 6247616 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3376 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 144789 # Number of read requests responded to by this memory -system.physmem.num_reads::total 148165 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 97619 # Number of write requests responded to by this memory -system.physmem.num_writes::total 97619 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1068276 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 45815949 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 46884225 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1068276 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1068276 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 30889827 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 30889827 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 30889827 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1068276 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 45815949 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 77774052 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 148166 # Total number of read requests seen -system.physmem.writeReqs 97619 # Total number of write requests seen -system.physmem.cpureqs 245800 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 9482560 # Total number of bytes read from memory -system.physmem.bytesWritten 6247616 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 9482560 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6247616 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 82 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 10 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 9642 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 9223 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 9266 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 8974 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 9810 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 9620 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 9110 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 8299 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 8798 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 8898 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 8934 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 9719 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 9635 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 9761 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 8951 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 9444 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 6285 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 6145 # Track writes on a per bank basis +system.physmem.bytes_read::cpu.inst 216896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9268224 # Number of bytes read from this memory +system.physmem.bytes_read::total 9485120 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 216896 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 216896 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6250688 # Number of bytes written to this memory +system.physmem.bytes_written::total 6250688 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3389 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 144816 # Number of read requests responded to by this memory +system.physmem.num_reads::total 148205 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 97667 # Number of write requests responded to by this memory +system.physmem.num_writes::total 97667 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 1071887 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 45802993 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 46874879 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1071887 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1071887 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 30890515 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 30890515 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 30890515 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1071887 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 45802993 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 77765395 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 148206 # Total number of read requests seen +system.physmem.writeReqs 97667 # Total number of write requests seen +system.physmem.cpureqs 245886 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 9485120 # Total number of bytes read from memory +system.physmem.bytesWritten 6250688 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 9485120 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6250688 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 73 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 7 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 9580 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 9220 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 9246 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 8983 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 9807 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 9644 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 9117 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 8328 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 8806 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 8899 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 8951 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 9734 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 9634 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 9768 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 8963 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 9453 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 6260 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 6146 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 6093 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 5883 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 6272 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 6268 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 6041 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 5542 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 5814 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 5893 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 5986 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 6510 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 6368 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 6328 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 6050 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 6141 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 5891 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 6270 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 6285 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 6047 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 5559 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 5812 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 5895 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 5992 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 6521 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 6360 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 6324 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 6066 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 6146 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 5 # Number of times wr buffer was full causing retry -system.physmem.totGap 202254789500 # Total gap between requests +system.physmem.numWrRetry 6 # Number of times wr buffer was full causing retry +system.physmem.totGap 202349728000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 148166 # Categorize read packet sizes +system.physmem.readPktSize::6 148206 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 97619 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 138581 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 8939 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 502 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 55 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 97667 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 138524 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 9025 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 520 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 58 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -124,31 +124,31 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4226 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4234 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4238 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4238 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4238 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4238 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4237 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4238 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4237 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4238 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4240 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4240 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4240 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4240 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4240 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4241 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 4246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 10 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 9 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 7 # What write queue length does an incoming req see @@ -156,167 +156,166 @@ system.physmem.wrQLenPdf::28 7 # Wh system.physmem.wrQLenPdf::29 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 6 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 56237 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 279.600690 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 133.370876 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 689.275557 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 28174 50.10% 50.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 10389 18.47% 68.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 4755 8.46% 77.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 2751 4.89% 81.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 1840 3.27% 85.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 1148 2.04% 87.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 864 1.54% 88.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 636 1.13% 89.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 440 0.78% 90.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 367 0.65% 91.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 311 0.55% 91.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 257 0.46% 92.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 204 0.36% 92.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 168 0.30% 93.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 168 0.30% 93.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 154 0.27% 93.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 142 0.25% 93.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 160 0.28% 94.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 179 0.32% 94.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 140 0.25% 94.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 187 0.33% 95.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 266 0.47% 95.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 973 1.73% 97.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 245 0.44% 97.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 154 0.27% 97.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 175 0.31% 98.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 98 0.17% 98.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 108 0.19% 98.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 57 0.10% 98.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 69 0.12% 98.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 37 0.07% 98.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 38 0.07% 98.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 29 0.05% 99.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 23 0.04% 99.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 13 0.02% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 16 0.03% 99.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 14 0.02% 99.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 7 0.01% 99.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 15 0.03% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 12 0.02% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 9 0.02% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 15 0.03% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 6 0.01% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 12 0.02% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 9 0.02% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 5 0.01% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 5 0.01% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 1 0.00% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 6 0.01% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 8 0.01% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 3 0.01% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 3 0.01% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 4 0.01% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 4 0.01% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 8 0.01% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 3 0.01% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3649 3 0.01% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 3 0.01% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 2 0.00% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3841 2 0.00% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 3 0.01% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 7 0.01% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 56168 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 280.051275 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 133.674597 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 689.024149 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 28075 49.98% 49.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 10399 18.51% 68.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 4642 8.26% 76.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 2823 5.03% 81.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 1837 3.27% 85.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 1236 2.20% 87.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 832 1.48% 88.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 663 1.18% 89.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 489 0.87% 90.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 349 0.62% 91.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 274 0.49% 91.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 236 0.42% 92.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 206 0.37% 92.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 181 0.32% 93.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 152 0.27% 93.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 162 0.29% 93.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 142 0.25% 93.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 167 0.30% 94.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 179 0.32% 94.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 157 0.28% 94.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 185 0.33% 95.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 244 0.43% 95.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 965 1.72% 97.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 247 0.44% 97.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 159 0.28% 97.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 168 0.30% 98.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 90 0.16% 98.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 119 0.21% 98.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 57 0.10% 98.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 59 0.11% 98.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 42 0.07% 98.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 39 0.07% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 20 0.04% 98.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 31 0.06% 99.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 18 0.03% 99.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 11 0.02% 99.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 21 0.04% 99.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 16 0.03% 99.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 11 0.02% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 15 0.03% 99.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 11 0.02% 99.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 8 0.01% 99.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 7 0.01% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 8 0.01% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 7 0.01% 99.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 7 0.01% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 3 0.01% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 6 0.01% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 4 0.01% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 4 0.01% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 4 0.01% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 2 0.00% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 8 0.01% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 3 0.01% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 3 0.01% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 8 0.01% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3649 7 0.01% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 1 0.00% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3777 4 0.01% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3841 8 0.01% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3905 1 0.00% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3969 5 0.01% 99.41% # Bytes accessed per row activation system.physmem.bytesPerActivate::4032-4033 2 0.00% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 1 0.00% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 2 0.00% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 1 0.00% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 2 0.00% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 4 0.01% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 2 0.00% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 1 0.00% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4673 1 0.00% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4737 1 0.00% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 1 0.00% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 1 0.00% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 1 0.00% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5057 3 0.01% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 4 0.01% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5185 5 0.01% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 2 0.00% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 2 0.00% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5441 1 0.00% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5505 1 0.00% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 1 0.00% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 1 0.00% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4289 2 0.00% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4353 1 0.00% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 2 0.00% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 2 0.00% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 1 0.00% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 2 0.00% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4673 6 0.01% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4737 1 0.00% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4801 1 0.00% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 1 0.00% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4929 2 0.00% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 1 0.00% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5057 1 0.00% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5121 3 0.01% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5185 1 0.00% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5249 1 0.00% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 3 0.01% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5377 3 0.01% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5441 1 0.00% 99.48% # Bytes accessed per row activation system.physmem.bytesPerActivate::5632-5633 1 0.00% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5697 2 0.00% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5825 1 0.00% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 1 0.00% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5953 2 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6017 2 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6209 4 0.01% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6401 1 0.00% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6529 1 0.00% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6721 1 0.00% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6785 2 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 1 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6977 1 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7041 1 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7105 1 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 1 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5697 1 0.00% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5761 2 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5953 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6017 3 0.01% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 1 0.00% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6209 3 0.01% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6465 1 0.00% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6657 1 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 1 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6849 1 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7041 2 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7169 1 0.00% 99.51% # Bytes accessed per row activation system.physmem.bytesPerActivate::7360-7361 2 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7425 1 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7553 1 0.00% 99.52% # Bytes accessed per row activation system.physmem.bytesPerActivate::7616-7617 2 0.00% 99.52% # Bytes accessed per row activation system.physmem.bytesPerActivate::7680-7681 1 0.00% 99.53% # Bytes accessed per row activation system.physmem.bytesPerActivate::7744-7745 1 0.00% 99.53% # Bytes accessed per row activation system.physmem.bytesPerActivate::7808-7809 2 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7873 1 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7937 1 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8001 2 0.00% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 3 0.01% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 257 0.46% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 56237 # Bytes accessed per row activation -system.physmem.totQLat 1508178750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 4631350000 # Sum of mem lat for all requests -system.physmem.totBusLat 740420000 # Total cycles spent in databus access -system.physmem.totBankLat 2382751250 # Total cycles spent in bank access -system.physmem.avgQLat 10184.62 # Average queueing delay per request -system.physmem.avgBankLat 16090.54 # Average bank access latency per request +system.physmem.bytesPerActivate::7872-7873 2 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8129 5 0.01% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 256 0.46% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 56168 # Bytes accessed per row activation +system.physmem.totQLat 1531991500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 4652987750 # Sum of mem lat for all requests +system.physmem.totBusLat 740665000 # Total cycles spent in databus access +system.physmem.totBankLat 2380331250 # Total cycles spent in bank access +system.physmem.avgQLat 10342.00 # Average queueing delay per request +system.physmem.avgBankLat 16068.88 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 31275.15 # Average memory access latency -system.physmem.avgRdBW 46.88 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 31410.88 # Average memory access latency +system.physmem.avgRdBW 46.87 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 30.89 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 46.88 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 46.87 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 30.89 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.61 # Data bus utilization in percentage system.physmem.avgRdQLen 0.02 # Average read queue length over time -system.physmem.avgWrQLen 8.03 # Average write queue length over time -system.physmem.readRowHits 130565 # Number of row buffer hits during reads -system.physmem.writeRowHits 58894 # Number of row buffer hits during writes -system.physmem.readRowHitRate 88.17 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 60.33 # Row buffer hit rate for writes -system.physmem.avgGap 822893.14 # Average gap between requests -system.membus.throughput 77774052 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 46889 # Transaction distribution -system.membus.trans_dist::ReadResp 46888 # Transaction distribution -system.membus.trans_dist::Writeback 97619 # Transaction distribution -system.membus.trans_dist::UpgradeReq 10 # Transaction distribution -system.membus.trans_dist::UpgradeResp 10 # Transaction distribution -system.membus.trans_dist::ReadExReq 101277 # Transaction distribution -system.membus.trans_dist::ReadExResp 101277 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 393970 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 393970 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 15730176 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 15730176 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 15730176 # Total data (bytes) +system.physmem.avgWrQLen 8.35 # Average write queue length over time +system.physmem.readRowHits 130665 # Number of row buffer hits during reads +system.physmem.writeRowHits 58958 # Number of row buffer hits during writes +system.physmem.readRowHitRate 88.21 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 60.37 # Row buffer hit rate for writes +system.physmem.avgGap 822984.74 # Average gap between requests +system.membus.throughput 77765395 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 46900 # Transaction distribution +system.membus.trans_dist::ReadResp 46899 # Transaction distribution +system.membus.trans_dist::Writeback 97667 # Transaction distribution +system.membus.trans_dist::UpgradeReq 7 # Transaction distribution +system.membus.trans_dist::UpgradeResp 7 # Transaction distribution +system.membus.trans_dist::ReadExReq 101306 # Transaction distribution +system.membus.trans_dist::ReadExResp 101306 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 394092 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 394092 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 15735808 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 15735808 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 15735808 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1080021750 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1084180500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 1400430490 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1402154244 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.7 # Layer utilization (%) -system.cpu.branchPred.lookups 182798066 # Number of BP lookups -system.cpu.branchPred.condPredicted 143118312 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 7265128 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 93487974 # Number of BTB lookups -system.cpu.branchPred.BTBHits 87210419 # Number of BTB hits +system.cpu.branchPred.lookups 182791904 # Number of BP lookups +system.cpu.branchPred.condPredicted 143107699 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 7265665 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 92799489 # Number of BTB lookups +system.cpu.branchPred.BTBHits 87211157 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 93.285174 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 12673306 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 115887 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 93.978057 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 12678036 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 116300 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -360,136 +359,136 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 404509620 # number of cpu cycles simulated +system.cpu.numCycles 404699496 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 119370691 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 761605740 # Number of instructions fetch has processed -system.cpu.fetch.Branches 182798066 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 99883725 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 170135363 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 35678308 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 77091190 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 33 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 441 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 119376230 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 761574875 # Number of instructions fetch has processed +system.cpu.fetch.Branches 182791904 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 99889193 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 170142836 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 35680693 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 77102658 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 26 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 212 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 30 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 114522071 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2438323 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 394207776 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.166768 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.987550 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 114526886 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2438240 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 394234025 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.166653 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.987457 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 224085033 56.84% 56.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 14184034 3.60% 60.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 22893795 5.81% 66.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 22742785 5.77% 72.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 20889438 5.30% 77.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 11596058 2.94% 80.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 13058827 3.31% 83.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 11996655 3.04% 86.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 52761151 13.38% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 224103808 56.85% 56.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 14182639 3.60% 60.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 22897810 5.81% 66.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 22745771 5.77% 72.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 20892648 5.30% 77.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 11601037 2.94% 80.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 13057020 3.31% 83.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 11991400 3.04% 86.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 52761892 13.38% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 394207776 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.451900 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.882788 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 129058894 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 72583383 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 158800998 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 6228602 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 27535899 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 26119356 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 76952 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 825527591 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 297029 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 27535899 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 135653385 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 10117573 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 47448086 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 158253744 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 15199089 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 800585743 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1337 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 3048778 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 8951135 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 327 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 954274745 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3500443085 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3500441750 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1335 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 394234025 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.451673 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.881828 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 129061557 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 72597650 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 158807244 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 6229539 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 27538035 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 26120872 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 76664 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 825542137 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 294964 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 27538035 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 135654542 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 10112461 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 47476958 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 158262389 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 15189640 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 800582614 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1358 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 3045147 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 8947899 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 349 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 954230037 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3500483849 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3500482489 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1360 # Number of floating rename lookups system.cpu.rename.CommittedMaps 666252291 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 288022454 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2292887 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2292884 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 41810314 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 170245714 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 73473402 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 28600787 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 15864837 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 755023538 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 3775253 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 665282495 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1376367 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 187359932 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 479861351 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 797621 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 394207776 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.687644 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.734895 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 287977746 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2292997 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2292995 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 41790364 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 170263021 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 73493180 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 28522055 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 15837658 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 755040585 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 3775393 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 665344412 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1377558 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 187353857 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 479696912 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 797761 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 394234025 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.687689 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.735339 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 138685304 35.18% 35.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 69974148 17.75% 52.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 71487489 18.13% 71.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 53410155 13.55% 84.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 31169458 7.91% 92.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15996787 4.06% 96.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8767931 2.22% 98.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 2898481 0.74% 99.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1818023 0.46% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 138748910 35.19% 35.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 69932496 17.74% 52.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 71500115 18.14% 71.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 53381002 13.54% 84.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 31138415 7.90% 92.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15994110 4.06% 96.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8838982 2.24% 98.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 2889382 0.73% 99.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1810613 0.46% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 394207776 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 394234025 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 480591 5.01% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 6540572 68.21% 73.22% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2567937 26.78% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 479873 5.03% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 6514297 68.24% 73.27% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2551723 26.73% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 447761903 67.30% 67.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 383485 0.06% 67.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 447783022 67.30% 67.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 383422 0.06% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 94 0.00% 67.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 92 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.36% # Type of FU issued @@ -515,84 +514,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.36% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 153367544 23.05% 90.41% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 63769466 9.59% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 153378055 23.05% 90.41% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 63799818 9.59% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 665282495 # Type of FU issued -system.cpu.iq.rate 1.644664 # Inst issue rate -system.cpu.iq.fu_busy_cnt 9589100 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014414 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1735738010 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 946965616 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 646015342 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 223 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 298 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 665344412 # Type of FU issued +system.cpu.iq.rate 1.644046 # Inst issue rate +system.cpu.iq.fu_busy_cnt 9545893 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014347 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1735846081 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 946976022 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 646072801 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 219 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 292 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 674871482 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 113 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 8586210 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 674890194 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 111 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 8556478 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 44216159 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 41012 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 810921 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 16612925 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 44233466 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 41675 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 810117 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 16632703 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 19492 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 6939 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 19496 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 7207 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 27535899 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 5281663 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 386285 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 760357745 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1115007 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 170245714 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 73473402 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2286711 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 219038 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 12304 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 810921 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4337552 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4003513 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8341065 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 655860831 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 150086003 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 9421664 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 27538035 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 5291148 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 386655 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 760374882 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1114721 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 170263021 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 73493180 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2286851 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 219754 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 12032 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 810117 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4339015 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4002364 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8341379 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 655919187 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 150094220 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 9425225 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1558954 # number of nop insts executed -system.cpu.iew.exec_refs 212560295 # number of memory reference insts executed -system.cpu.iew.exec_branches 138490949 # Number of branches executed -system.cpu.iew.exec_stores 62474292 # Number of stores executed -system.cpu.iew.exec_rate 1.621373 # Inst execution rate -system.cpu.iew.wb_sent 650984327 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 646015358 # cumulative count of insts written-back -system.cpu.iew.wb_producers 374693412 # num instructions producing a value -system.cpu.iew.wb_consumers 646299598 # num instructions consuming a value +system.cpu.iew.exec_nop 1558904 # number of nop insts executed +system.cpu.iew.exec_refs 212597859 # number of memory reference insts executed +system.cpu.iew.exec_branches 138494490 # Number of branches executed +system.cpu.iew.exec_stores 62503639 # Number of stores executed +system.cpu.iew.exec_rate 1.620756 # Inst execution rate +system.cpu.iew.wb_sent 651040733 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 646072817 # cumulative count of insts written-back +system.cpu.iew.wb_producers 374723288 # num instructions producing a value +system.cpu.iew.wb_consumers 646307001 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.597033 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.579752 # average fanout of values written-back +system.cpu.iew.wb_rate 1.596426 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.579791 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 189415917 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 189435177 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 7190999 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 366671877 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.557164 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.230606 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 7191667 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 366695990 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.557061 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.231965 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 158948889 43.35% 43.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 98517703 26.87% 70.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 33831327 9.23% 79.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 18775088 5.12% 84.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 16222583 4.42% 88.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7456199 2.03% 91.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 6938304 1.89% 92.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3192877 0.87% 93.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 22788907 6.22% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 159030399 43.37% 43.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 98569557 26.88% 70.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 33781130 9.21% 79.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 18728324 5.11% 84.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 16185625 4.41% 88.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7417790 2.02% 91.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 6942685 1.89% 92.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3160022 0.86% 93.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 22880458 6.24% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 366671877 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 366695990 # Number of insts commited each cycle system.cpu.commit.committedInsts 506581607 # Number of instructions committed system.cpu.commit.committedOps 570968167 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -603,221 +602,221 @@ system.cpu.commit.branches 121548301 # Nu system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 470727693 # Number of committed integer instructions. system.cpu.commit.function_calls 9757362 # Number of function calls committed. -system.cpu.commit.bw_lim_events 22788907 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 22880458 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1104259916 # The number of ROB reads -system.cpu.rob.rob_writes 1548425259 # The number of ROB writes -system.cpu.timesIdled 328032 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 10301844 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 1104211738 # The number of ROB reads +system.cpu.rob.rob_writes 1548465628 # The number of ROB writes +system.cpu.timesIdled 328564 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 10465471 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 505237723 # Number of Instructions Simulated system.cpu.committedOps 569624283 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 505237723 # Number of Instructions Simulated -system.cpu.cpi 0.800632 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.800632 # CPI: Total CPI of All Threads -system.cpu.ipc 1.249013 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.249013 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3058504664 # number of integer regfile reads -system.cpu.int_regfile_writes 751970917 # number of integer regfile writes +system.cpu.cpi 0.801008 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.801008 # CPI: Total CPI of All Threads +system.cpu.ipc 1.248427 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.248427 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3058780194 # number of integer regfile reads +system.cpu.int_regfile_writes 751998753 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 210811449 # number of misc regfile reads +system.cpu.misc_regfile_reads 210849013 # number of misc regfile reads system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes -system.cpu.toL2Bus.throughput 735317990 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 864350 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 864349 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1110574 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 73 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 73 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 348852 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 348852 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 33690 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3503354 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 3537044 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 1075520 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 147641024 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 148716544 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 148716544 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 5056 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 2272504241 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 735301298 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 864913 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 864912 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1111058 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 69 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 69 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 348843 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 348843 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 33804 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3504826 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 3538630 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 1079232 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 147703872 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 148783104 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 148783104 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 4928 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 2273504243 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 25334982 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 26125731 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1794529465 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1828577727 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.cpu.icache.replacements 14954 # number of replacements -system.cpu.icache.tagsinuse 1101.424981 # Cycle average of tags in use -system.cpu.icache.total_refs 114501007 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 16812 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 6810.671366 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1101.424981 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.537805 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.537805 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 114501007 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 114501007 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 114501007 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 114501007 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 114501007 # number of overall hits -system.cpu.icache.overall_hits::total 114501007 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 21063 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 21063 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 21063 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 21063 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 21063 # number of overall misses -system.cpu.icache.overall_misses::total 21063 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 592520500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 592520500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 592520500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 592520500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 592520500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 592520500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 114522070 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 114522070 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 114522070 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 114522070 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 114522070 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 114522070 # number of overall (read+write) accesses +system.cpu.icache.tags.replacements 15008 # number of replacements +system.cpu.icache.tags.tagsinuse 1099.436561 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 114505770 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 16868 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 6788.343016 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1099.436561 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.536834 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.536834 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 114505770 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 114505770 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 114505770 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 114505770 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 114505770 # number of overall hits +system.cpu.icache.overall_hits::total 114505770 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 21115 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 21115 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 21115 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 21115 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 21115 # number of overall misses +system.cpu.icache.overall_misses::total 21115 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 590629979 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 590629979 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 590629979 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 590629979 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 590629979 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 590629979 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 114526885 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 114526885 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 114526885 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 114526885 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 114526885 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 114526885 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000184 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000184 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000184 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000184 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000184 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000184 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28130.869297 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 28130.869297 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 28130.869297 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 28130.869297 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 28130.869297 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 28130.869297 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 770 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27972.056784 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 27972.056784 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 27972.056784 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 27972.056784 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 27972.056784 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 27972.056784 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 633 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 10 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 64.166667 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 63.300000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4178 # 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number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -826,195 +825,195 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 97619 # number of writebacks -system.cpu.l2cache.writebacks::total 97619 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 4 # number of ReadReq MSHR hits +system.cpu.l2cache.writebacks::writebacks 97667 # number of writebacks +system.cpu.l2cache.writebacks::total 97667 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 5 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 24 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 28 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 29 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.data 24 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 28 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # number of overall MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 29 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 24 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 28 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3377 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 43512 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 46889 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 10 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 10 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101277 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 101277 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3377 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 144789 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 148166 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3377 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 144789 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 148166 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 233867750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3101136000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3335003750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 100010 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 100010 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5785341250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5785341250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 233867750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8886477250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 9120345000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 233867750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8886477250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 9120345000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.200940 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.051344 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.054253 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.136986 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.136986 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.290315 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.290315 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.200940 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.121029 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.122136 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.200940 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.121029 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.122136 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 69253.109269 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71270.821842 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 71125.503850 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57123.939789 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57123.939789 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69253.109269 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61375.361733 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61554.911383 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69253.109269 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61375.361733 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61554.911383 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_hits::total 29 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3390 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 43510 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 46900 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 6 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 6 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101307 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 101307 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3390 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 144817 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 148207 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3390 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 144817 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 148207 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 230113250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3119161250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3349274500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 63505 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 63505 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5794278751 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5794278751 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 230113250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8913440001 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 9143553251 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 230113250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8913440001 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9143553251 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.201020 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.051311 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.054230 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.086957 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.086957 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.290409 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.290409 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.201020 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.121002 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.122114 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.201020 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.121002 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.122114 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67880.014749 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71688.376235 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 71413.102345 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10584.166667 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10584.166667 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57195.245649 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57195.245649 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67880.014749 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61549.679948 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61694.476314 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67880.014749 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61549.679948 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61694.476314 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1192221 # number of replacements -system.cpu.dcache.tagsinuse 4057.785515 # Cycle average of tags in use -system.cpu.dcache.total_refs 190145872 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1196317 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 158.942715 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 4220492000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4057.785515 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.990670 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.990670 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 136179358 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 136179358 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 50988931 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 50988931 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488837 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 1488837 # number of LoadLockedReq hits +system.cpu.dcache.tags.replacements 1192719 # number of replacements +system.cpu.dcache.tags.tagsinuse 4057.784175 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 190184088 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1196815 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 158.908510 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 4223544250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4057.784175 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.990670 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.990670 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 136217061 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 136217061 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 50989456 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 50989456 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488807 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 1488807 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 187168289 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 187168289 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 187168289 # number of overall hits -system.cpu.dcache.overall_hits::total 187168289 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1699578 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1699578 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3250375 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3250375 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 37 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 37 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 4949953 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4949953 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 4949953 # number of overall misses -system.cpu.dcache.overall_misses::total 4949953 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 29584540500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 29584540500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 69108485945 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 69108485945 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 701500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 701500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 98693026445 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 98693026445 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 98693026445 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 98693026445 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 137878936 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 137878936 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 187206517 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 187206517 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 187206517 # number of overall hits +system.cpu.dcache.overall_hits::total 187206517 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1700496 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1700496 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3249850 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3249850 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 41 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 41 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 4950346 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4950346 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 4950346 # number of overall misses +system.cpu.dcache.overall_misses::total 4950346 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 29799414454 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 29799414454 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 69603685702 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 69603685702 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 646250 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 646250 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 99403100156 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 99403100156 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 99403100156 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 99403100156 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 137917557 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 137917557 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488874 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 1488874 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488848 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1488848 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 192118242 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 192118242 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 192118242 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 192118242 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012327 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.012327 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.059927 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.059927 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000025 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000025 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.025765 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.025765 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.025765 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.025765 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17406.991912 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17406.991912 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21261.696249 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 21261.696249 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 18959.459459 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 18959.459459 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 19938.174452 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 19938.174452 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 19938.174452 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 19938.174452 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 19233 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 40481 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1722 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 665 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.168990 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 60.873684 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 192156863 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 192156863 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 192156863 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 192156863 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012330 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.012330 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.059917 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.059917 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000028 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000028 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.025762 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.025762 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.025762 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.025762 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17523.954454 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17523.954454 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21417.507178 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 21417.507178 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15762.195122 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15762.195122 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 20080.030801 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 20080.030801 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 20080.030801 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 20080.030801 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 21739 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 43165 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1718 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 667 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.653667 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 64.715142 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1110574 # number of writebacks -system.cpu.dcache.writebacks::total 1110574 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 851549 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 851549 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2902014 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2902014 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 37 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 37 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3753563 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3753563 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3753563 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3753563 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 848029 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 848029 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348361 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 348361 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1196390 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1196390 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1196390 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1196390 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12568519034 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 12568519034 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9922118995 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 9922118995 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22490638029 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 22490638029 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22490638029 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 22490638029 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006151 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006151 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 1111058 # number of writebacks +system.cpu.dcache.writebacks::total 1111058 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 851983 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 851983 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2901479 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2901479 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 41 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 41 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3753462 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3753462 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3753462 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3753462 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 848513 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 848513 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348371 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 348371 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1196884 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1196884 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1196884 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1196884 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12602071778 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 12602071778 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9955936491 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 9955936491 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22558008269 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 22558008269 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22558008269 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 22558008269 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006152 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006152 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006423 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006423 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006227 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006227 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006227 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006227 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14820.859940 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14820.859940 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28482.289909 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28482.289909 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18798.751268 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 18798.751268 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18798.751268 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 18798.751268 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006229 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006229 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006229 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006229 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14851.948972 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14851.948972 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28578.545548 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28578.545548 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18847.280329 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 18847.280329 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18847.280329 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 18847.280329 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt index 0fce97b03..b28088e7d 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt @@ -115,15 +115,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 1434732024 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.replacements 9788 # number of replacements -system.cpu.icache.tagsinuse 982.663229 # Cycle average of tags in use -system.cpu.icache.total_refs 516599855 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 11521 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 44839.845066 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 982.663229 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.479816 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.479816 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 9788 # number of replacements +system.cpu.icache.tags.tagsinuse 982.663229 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 516599855 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 11521 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 44839.845066 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 982.663229 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.479816 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.479816 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 516599855 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 516599855 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 516599855 # number of demand (read+write) hits @@ -193,19 +193,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 21105.199201 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21105.199201 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 21105.199201 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 109895 # number of replacements -system.cpu.l2cache.tagsinuse 27243.192324 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1668833 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 141072 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 11.829654 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 343698539000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 23381.854289 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 287.865470 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 3573.472565 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.713558 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.008785 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.109054 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.831396 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 109895 # number of replacements +system.cpu.l2cache.tags.tagsinuse 27243.192324 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1668833 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 141072 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 11.829654 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 343698539000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 23381.854289 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 287.865470 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 3573.472565 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.713558 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008785 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.109054 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.831396 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 8751 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 743573 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 752324 # number of ReadReq hits @@ -331,15 +331,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40029.602888 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40009.472473 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40009.863371 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1134822 # number of replacements -system.cpu.dcache.tagsinuse 4065.297446 # Cycle average of tags in use -system.cpu.dcache.total_refs 179817786 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1138918 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 157.884752 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 11885124000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4065.297446 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.992504 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.992504 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 1134822 # number of replacements +system.cpu.dcache.tags.tagsinuse 4065.297446 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 179817786 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1138918 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 157.884752 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 11885124000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4065.297446 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.992504 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.992504 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 122957658 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 122957658 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 53883046 # number of WriteReq hits diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index d96ed8e27..d91a5905c 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,102 +1,102 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.458090 # Number of seconds simulated -sim_ticks 458090415000 # Number of ticks simulated -final_tick 458090415000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.458202 # Number of seconds simulated +sim_ticks 458201684000 # Number of ticks simulated +final_tick 458201684000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 88483 # Simulator instruction rate (inst/s) -host_op_rate 163615 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 49019747 # Simulator tick rate (ticks/s) -host_mem_usage 344468 # Number of bytes of host memory used -host_seconds 9345.02 # Real time elapsed on the host +host_inst_rate 111882 # Simulator instruction rate (inst/s) +host_op_rate 206882 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 61997502 # Simulator tick rate (ticks/s) +host_mem_usage 341328 # Number of bytes of host memory used +host_seconds 7390.65 # Real time elapsed on the host sim_insts 826877109 # Number of instructions simulated sim_ops 1528988701 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 202496 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24476544 # Number of bytes read from this memory -system.physmem.bytes_read::total 24679040 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 202496 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 202496 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18790272 # Number of bytes written to this memory -system.physmem.bytes_written::total 18790272 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3164 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 382446 # Number of read requests responded to by this memory -system.physmem.num_reads::total 385610 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 293598 # Number of write requests responded to by this memory -system.physmem.num_writes::total 293598 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 442044 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 53431688 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 53873731 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 442044 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 442044 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 41018697 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 41018697 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 41018697 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 442044 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 53431688 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 94892429 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 385610 # Total number of read requests seen -system.physmem.writeReqs 293598 # Total number of write requests seen -system.physmem.cpureqs 811581 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 24679040 # Total number of bytes read from memory -system.physmem.bytesWritten 18790272 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 24679040 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 18790272 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 158 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 132366 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 24064 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 26444 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 24671 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 24517 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 23227 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 23669 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 24418 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 24212 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 23609 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 23834 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 24778 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 24050 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 23243 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 22960 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 23768 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 23988 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 18530 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 19820 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 18950 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 18922 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 18033 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 18412 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 18983 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 18945 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 18535 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 18118 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 18807 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 17707 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 17351 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 16952 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 17709 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 17824 # Track writes on a per bank basis +system.physmem.bytes_read::cpu.inst 201408 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24476096 # Number of bytes read from this memory +system.physmem.bytes_read::total 24677504 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 201408 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 201408 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18788864 # Number of bytes written to this memory +system.physmem.bytes_written::total 18788864 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3147 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 382439 # Number of read requests responded to by this memory +system.physmem.num_reads::total 385586 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 293576 # Number of write requests responded to by this memory +system.physmem.num_writes::total 293576 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 439562 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 53417735 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 53857297 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 439562 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 439562 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 41005663 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 41005663 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 41005663 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 439562 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 53417735 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 94862960 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 385586 # Total number of read requests seen +system.physmem.writeReqs 293576 # Total number of write requests seen +system.physmem.cpureqs 810414 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 24677504 # Total number of bytes read from memory +system.physmem.bytesWritten 18788864 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 24677504 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 18788864 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 149 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 131239 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 24063 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 26436 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 24657 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 24489 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 23219 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 23674 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 24391 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 24210 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 23623 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 23844 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 24783 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 24073 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 23240 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 22943 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 23791 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 24001 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 18525 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 19821 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 18940 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 18905 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 18028 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 18411 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 18971 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 18943 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 18544 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 18119 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 18810 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 17724 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 17345 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 16945 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 17717 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 17828 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 7 # Number of times wr buffer was full causing retry -system.physmem.totGap 458090389000 # Total gap between requests +system.physmem.numWrRetry 13 # Number of times wr buffer was full causing retry +system.physmem.totGap 458201657000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 385610 # Categorize read packet sizes +system.physmem.readPktSize::6 385586 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 293598 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 380772 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4340 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 300 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 34 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see +system.physmem.writePktSize::6 293576 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 380883 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4226 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 288 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 33 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -124,347 +124,347 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 12721 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 12730 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 12723 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 12732 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 12733 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 12738 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 12746 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 12748 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 12751 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 12755 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 12756 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 12765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 12765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 12765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 12765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 12765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 12765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 12765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 12765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 12765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 12765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 12765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 12765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 12765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 12765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 33 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 9 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 126022 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 344.851534 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 161.962358 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 666.348366 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 54057 42.89% 42.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 23501 18.65% 61.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 10538 8.36% 69.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 6321 5.02% 74.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 4049 3.21% 78.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 2993 2.37% 80.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 2158 1.71% 82.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 1750 1.39% 83.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 1435 1.14% 84.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 1167 0.93% 85.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 1218 0.97% 86.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 1087 0.86% 87.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 749 0.59% 88.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 671 0.53% 88.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 595 0.47% 89.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 568 0.45% 89.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 568 0.45% 90.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 525 0.42% 90.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 573 0.45% 90.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 736 0.58% 91.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 592 0.47% 91.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 743 0.59% 92.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 6177 4.90% 97.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 481 0.38% 97.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 330 0.26% 98.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 288 0.23% 98.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 210 0.17% 98.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 190 0.15% 98.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 142 0.11% 98.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 147 0.12% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 96 0.08% 98.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 92 0.07% 98.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 69 0.05% 99.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 52 0.04% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 45 0.04% 99.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 44 0.03% 99.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 35 0.03% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 33 0.03% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 28 0.02% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 24 0.02% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 31 0.02% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 21 0.02% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 18 0.01% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 25 0.02% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 22 0.02% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 20 0.02% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 17 0.01% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 13 0.01% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 15 0.01% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 13 0.01% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 16 0.01% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 17 0.01% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 6 0.00% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 9 0.01% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 7 0.01% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 17 0.01% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3649 9 0.01% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 10 0.01% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 8 0.01% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3841 13 0.01% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 9 0.01% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 7 0.01% 99.51% # Bytes accessed per row activation +system.physmem.wrQLenPdf::3 12739 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 12740 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 12743 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 12746 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 12748 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 12750 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 12764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 12764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 12764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 12764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 12764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 12764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 12764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 12764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 12764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 12764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 12764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 12764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 12764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 12764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 33 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 14 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 125877 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 345.228437 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 161.863436 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 669.217085 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 54117 42.99% 42.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 23349 18.55% 61.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 10530 8.37% 69.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 6425 5.10% 75.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 4023 3.20% 78.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 2874 2.28% 80.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 2162 1.72% 82.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 1748 1.39% 83.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 1399 1.11% 84.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 1145 0.91% 85.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 1227 0.97% 86.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 1117 0.89% 87.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 747 0.59% 88.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 630 0.50% 88.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 615 0.49% 89.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 623 0.49% 89.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 541 0.43% 89.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 508 0.40% 90.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 588 0.47% 90.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 726 0.58% 91.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 627 0.50% 91.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 694 0.55% 92.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 6218 4.94% 97.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 497 0.39% 97.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 336 0.27% 98.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 279 0.22% 98.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 216 0.17% 98.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 162 0.13% 98.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 151 0.12% 98.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 121 0.10% 98.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 106 0.08% 98.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 85 0.07% 98.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 80 0.06% 99.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 63 0.05% 99.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 52 0.04% 99.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 41 0.03% 99.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 42 0.03% 99.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 32 0.03% 99.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 30 0.02% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 20 0.02% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 25 0.02% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 22 0.02% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 23 0.02% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 19 0.02% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 14 0.01% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 22 0.02% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 12 0.01% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 19 0.02% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 11 0.01% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 20 0.02% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 17 0.01% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 11 0.01% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 14 0.01% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 8 0.01% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 8 0.01% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 14 0.01% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3649 8 0.01% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 7 0.01% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3777 7 0.01% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3841 14 0.01% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3905 8 0.01% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3969 6 0.00% 99.51% # Bytes accessed per row activation system.physmem.bytesPerActivate::4032-4033 5 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 13 0.01% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 4 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 7 0.01% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 8 0.01% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 7 0.01% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 6 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 5 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 4 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 4 0.00% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4673 8 0.01% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4737 2 0.00% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 4 0.00% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 2 0.00% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4929 6 0.00% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 6 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 6 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 7 0.01% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4225 3 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4289 6 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4353 5 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 6 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 3 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 5 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 2 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4673 9 0.01% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4737 5 0.00% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4801 9 0.01% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 5 0.00% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4929 4 0.00% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 4 0.00% 99.57% # Bytes accessed per row activation system.physmem.bytesPerActivate::5056-5057 7 0.01% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5185 9 0.01% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5249 3 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 8 0.01% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 11 0.01% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5441 4 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5505 5 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5569 5 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5633 3 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5697 4 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5761 3 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5825 4 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5953 3 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6017 2 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6081 3 0.00% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 4 0.00% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6209 2 0.00% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6273 4 0.00% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6337 2 0.00% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6401 2 0.00% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6465 6 0.00% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6529 7 0.01% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6593 1 0.00% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 5 0.00% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6721 3 0.00% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6785 3 0.00% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6849 1 0.00% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 4 0.00% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6977 4 0.00% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7041 1 0.00% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7105 1 0.00% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 2 0.00% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7233 3 0.00% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7297 4 0.00% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7361 2 0.00% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7425 1 0.00% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7553 3 0.00% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7617 2 0.00% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7681 2 0.00% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7745 1 0.00% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7809 3 0.00% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7937 3 0.00% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8001 3 0.00% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8065 1 0.00% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5121 3 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5185 4 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5249 5 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 5 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5377 4 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5441 4 0.00% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5505 8 0.01% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5569 2 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5633 1 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5697 5 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5761 5 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5825 5 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 1 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5953 4 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6017 4 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6081 2 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 5 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6209 5 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6273 2 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6337 3 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6401 1 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6465 2 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6529 5 0.00% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6593 2 0.00% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6657 10 0.01% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 5 0.00% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6785 4 0.00% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6849 3 0.00% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 2 0.00% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6977 1 0.00% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7105 2 0.00% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7169 2 0.00% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7233 2 0.00% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7297 5 0.00% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7425 4 0.00% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7553 4 0.00% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7681 4 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7745 2 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7809 4 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7873 2 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7937 4 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8001 1 0.00% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8065 2 0.00% 99.70% # Bytes accessed per row activation system.physmem.bytesPerActivate::8128-8129 4 0.00% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 373 0.30% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 126022 # Bytes accessed per row activation -system.physmem.totQLat 3040953000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11219526750 # Sum of mem lat for all requests -system.physmem.totBusLat 1927260000 # Total cycles spent in databus access -system.physmem.totBankLat 6251313750 # Total cycles spent in bank access -system.physmem.avgQLat 7889.32 # Average queueing delay per request -system.physmem.avgBankLat 16218.14 # Average bank access latency per request +system.physmem.bytesPerActivate::8192-8193 377 0.30% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 125877 # Bytes accessed per row activation +system.physmem.totQLat 3046093750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 11221540000 # Sum of mem lat for all requests +system.physmem.totBusLat 1927185000 # Total cycles spent in databus access +system.physmem.totBankLat 6248261250 # Total cycles spent in bank access +system.physmem.avgQLat 7902.96 # Average queueing delay per request +system.physmem.avgBankLat 16210.85 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 29107.46 # Average memory access latency -system.physmem.avgRdBW 53.87 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 41.02 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 53.87 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 41.02 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 29113.81 # Average memory access latency +system.physmem.avgRdBW 53.86 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 41.01 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 53.86 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 41.01 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.74 # Data bus utilization in percentage system.physmem.avgRdQLen 0.02 # Average read queue length over time -system.physmem.avgWrQLen 10.25 # Average write queue length over time -system.physmem.readRowHits 346179 # Number of row buffer hits during reads -system.physmem.writeRowHits 206846 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.81 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 70.45 # Row buffer hit rate for writes -system.physmem.avgGap 674447.87 # Average gap between requests -system.membus.throughput 94892429 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 178764 # Transaction distribution -system.membus.trans_dist::ReadResp 178764 # Transaction distribution -system.membus.trans_dist::Writeback 293598 # Transaction distribution -system.membus.trans_dist::UpgradeReq 132366 # Transaction distribution -system.membus.trans_dist::UpgradeResp 132366 # Transaction distribution -system.membus.trans_dist::ReadExReq 206846 # Transaction distribution -system.membus.trans_dist::ReadExResp 206846 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1329550 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1329550 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 1329550 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1329550 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43469312 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 43469312 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 43469312 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 43469312 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 43469312 # Total data (bytes) +system.physmem.avgWrQLen 9.78 # Average write queue length over time +system.physmem.readRowHits 346233 # Number of row buffer hits during reads +system.physmem.writeRowHits 206899 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.83 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 70.48 # Row buffer hit rate for writes +system.physmem.avgGap 674657.38 # Average gap between requests +system.membus.throughput 94862960 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 178738 # Transaction distribution +system.membus.trans_dist::ReadResp 178738 # Transaction distribution +system.membus.trans_dist::Writeback 293576 # Transaction distribution +system.membus.trans_dist::UpgradeReq 131239 # Transaction distribution +system.membus.trans_dist::UpgradeResp 131239 # Transaction distribution +system.membus.trans_dist::ReadExReq 206848 # Transaction distribution +system.membus.trans_dist::ReadExResp 206848 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1327226 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1327226 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 1327226 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1327226 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43466368 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 43466368 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 43466368 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 43466368 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 43466368 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 3305392000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 3389530500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 3861844643 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.8 # Layer utilization (%) -system.cpu.branchPred.lookups 205596082 # Number of BP lookups -system.cpu.branchPred.condPredicted 205596082 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 9898225 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 117113450 # Number of BTB lookups -system.cpu.branchPred.BTBHits 114684719 # Number of BTB hits +system.membus.respLayer1.occupancy 3902075273 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.9 # Layer utilization (%) +system.cpu.branchPred.lookups 205568854 # Number of BP lookups +system.cpu.branchPred.condPredicted 205568854 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 9898045 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 117107860 # Number of BTB lookups +system.cpu.branchPred.BTBHits 114698140 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.926172 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 25065236 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1793499 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 97.942307 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 25050036 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1792384 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 916341755 # number of cpu cycles simulated +system.cpu.numCycles 916561947 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 167380851 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1131684299 # Number of instructions fetch has processed -system.cpu.fetch.Branches 205596082 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 139749955 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 352238514 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 71080243 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 303608780 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 49221 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 257762 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 41 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 162013900 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2533511 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 884463501 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.380571 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.325217 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 167337624 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1131632693 # Number of instructions fetch has processed +system.cpu.fetch.Branches 205568854 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 139748176 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 352252174 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 71070724 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 303559378 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 48756 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 256407 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 42 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 161987307 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2533545 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 884373851 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.380748 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.325183 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 536297540 60.64% 60.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 23375974 2.64% 63.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 25249823 2.85% 66.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 27885460 3.15% 69.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 17746776 2.01% 71.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 22912915 2.59% 73.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 29432713 3.33% 77.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 26649868 3.01% 80.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 174912432 19.78% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 536185326 60.63% 60.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 23385873 2.64% 63.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 25265986 2.86% 66.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 27892803 3.15% 69.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 17753666 2.01% 71.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 22918818 2.59% 73.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 29434810 3.33% 77.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 26635470 3.01% 80.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 174901099 19.78% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 884463501 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.224366 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.235002 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 222590662 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 258678079 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 295142458 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 47123970 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 60928332 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2071292159 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 60928332 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 256060013 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 114129471 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 17113 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 306672128 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 146656444 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2035150603 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 19208 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 24905685 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 106527720 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 191 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2137983705 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5150412052 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 5150294631 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 117421 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 884373851 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.224283 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.234649 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 222568980 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 258608644 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 295229836 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 47046921 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 60919470 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2071205121 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 60919470 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 255995647 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 114297250 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 16886 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 306709824 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 146434774 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2035062210 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 18307 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 24837229 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 106300367 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 277 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2137993094 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5150291705 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 5150182226 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 109479 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 523942851 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1169 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1101 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 347123881 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 495862419 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 194434977 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 195681210 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 55050050 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1975391803 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 13688 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1772107860 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 473436 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 441529176 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 734849750 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 13136 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 884463501 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.003596 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.883133 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 523952240 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1150 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1079 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 346047502 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 495816702 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 194427613 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 195309908 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 54766711 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1975264807 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 13440 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1772060023 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 484597 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 441400489 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 734643480 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 12888 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 884373851 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.003745 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.883277 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 267821241 30.28% 30.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 151877147 17.17% 47.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 137227346 15.52% 62.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 131884953 14.91% 77.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 91607169 10.36% 88.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 55986805 6.33% 94.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 34422638 3.89% 98.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 11866983 1.34% 99.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1769219 0.20% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 267848230 30.29% 30.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 151701849 17.15% 47.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 137335256 15.53% 62.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 131820581 14.91% 77.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 91575970 10.35% 88.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 56038061 6.34% 94.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 34420312 3.89% 98.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 11858874 1.34% 99.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1774718 0.20% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 884463501 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 884373851 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 4968361 32.63% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 7638299 50.16% 82.79% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2620527 17.21% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 4913366 32.39% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 7647346 50.41% 82.79% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2610757 17.21% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2623300 0.15% 0.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1165765153 65.78% 65.93% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 352884 0.02% 65.95% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 3880872 0.22% 66.17% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2623506 0.15% 0.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1165695577 65.78% 65.93% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 352860 0.02% 65.95% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 3880836 0.22% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.17% # Type of FU issued @@ -491,84 +491,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.17% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.17% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 429256529 24.22% 90.39% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 170229122 9.61% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 429278718 24.22% 90.39% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 170228526 9.61% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1772107860 # Type of FU issued -system.cpu.iq.rate 1.933894 # Inst issue rate -system.cpu.iq.fu_busy_cnt 15227187 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.008593 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4444363529 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2417156929 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1744871940 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 16315 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 34548 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 3820 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1784704039 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 7708 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 172523009 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1772060023 # Type of FU issued +system.cpu.iq.rate 1.933377 # Inst issue rate +system.cpu.iq.fu_busy_cnt 15171469 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.008561 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4444135081 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2416902562 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1744830840 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 14882 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 32680 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 3547 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1784600923 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 7063 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 172561564 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 111760262 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 384025 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 328721 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 45275855 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 111714545 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 391852 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 328370 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 45268501 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 15305 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 564 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 14755 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 580 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 60928332 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 66654454 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 7158115 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1975405491 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 788328 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 495862419 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 194436041 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 3451 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 4460839 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 82816 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 328721 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 5900080 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4426535 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 10326615 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1752972690 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 424121378 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 19135170 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 60919470 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 66677729 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 7180416 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1975278247 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 784703 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 495816702 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 194428687 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 3345 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 4482902 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 83440 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 328370 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 5898868 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4425517 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 10324385 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1752929949 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 424141217 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 19130074 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 590916604 # number of memory reference insts executed -system.cpu.iew.exec_branches 167471832 # Number of branches executed -system.cpu.iew.exec_stores 166795226 # Number of stores executed -system.cpu.iew.exec_rate 1.913012 # Inst execution rate -system.cpu.iew.wb_sent 1749734148 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1744875760 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1325266031 # num instructions producing a value -system.cpu.iew.wb_consumers 1946145137 # num instructions consuming a value +system.cpu.iew.exec_refs 590928526 # number of memory reference insts executed +system.cpu.iew.exec_branches 167466016 # Number of branches executed +system.cpu.iew.exec_stores 166787309 # Number of stores executed +system.cpu.iew.exec_rate 1.912506 # Inst execution rate +system.cpu.iew.wb_sent 1749673980 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1744834387 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1325007870 # num instructions producing a value +system.cpu.iew.wb_consumers 1945707966 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.904176 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.680970 # average fanout of values written-back +system.cpu.iew.wb_rate 1.903673 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.680990 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 446445392 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 446317369 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 9927956 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 823535169 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.856616 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.436023 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 9927482 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 823454381 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.856798 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.436978 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 331309797 40.23% 40.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 193436575 23.49% 63.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 63121599 7.66% 71.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 92647186 11.25% 82.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 25073312 3.04% 85.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 27553603 3.35% 89.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 9217324 1.12% 90.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 11404021 1.38% 91.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 69771752 8.47% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 331487662 40.26% 40.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 193224596 23.47% 63.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 63171510 7.67% 71.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 92561504 11.24% 82.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 24941236 3.03% 85.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 27475920 3.34% 89.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 9375370 1.14% 90.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 11392855 1.38% 91.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 69823728 8.48% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 823535169 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 823454381 # Number of insts commited each cycle system.cpu.commit.committedInsts 826877109 # Number of instructions committed system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -579,226 +579,226 @@ system.cpu.commit.branches 149758583 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 1528317561 # Number of committed integer instructions. system.cpu.commit.function_calls 17673145 # Number of function calls committed. -system.cpu.commit.bw_lim_events 69771752 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 69823728 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2729197510 # The number of ROB reads -system.cpu.rob.rob_writes 4011957603 # The number of ROB writes -system.cpu.timesIdled 3360338 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 31878254 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2728936723 # The number of ROB reads +system.cpu.rob.rob_writes 4011692646 # The number of ROB writes +system.cpu.timesIdled 3353511 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 32188096 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826877109 # Number of Instructions Simulated system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 826877109 # Number of Instructions Simulated -system.cpu.cpi 1.108196 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.108196 # CPI: Total CPI of All Threads -system.cpu.ipc 0.902368 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.902368 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3313525285 # number of integer regfile reads -system.cpu.int_regfile_writes 1825886137 # number of integer regfile writes -system.cpu.fp_regfile_reads 3803 # number of floating regfile reads -system.cpu.fp_regfile_writes 18 # number of floating regfile writes -system.cpu.misc_regfile_reads 964657168 # number of misc regfile reads +system.cpu.cpi 1.108462 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.108462 # CPI: Total CPI of All Threads +system.cpu.ipc 0.902151 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.902151 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3313440054 # number of integer regfile reads +system.cpu.int_regfile_writes 1825840966 # number of integer regfile writes +system.cpu.fp_regfile_reads 3533 # number of floating regfile reads +system.cpu.fp_regfile_writes 16 # number of floating regfile writes +system.cpu.misc_regfile_reads 964658774 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 699341277 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 1903111 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1903110 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2330801 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 133805 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 133805 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 771738 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 771738 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 147545 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 7666657 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 7814202 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 436416 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 311355136 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 311791552 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 311791552 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 8569984 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 4904454883 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 698991407 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 1901821 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1901820 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2330756 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 132628 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 132628 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 771784 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 771784 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 146337 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 7664164 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 7810501 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 435712 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 311349248 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 311784960 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 311784960 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 8494080 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 4903151186 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 211090494 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 209959241 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3868088996 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) -system.cpu.icache.replacements 5303 # number of replacements -system.cpu.icache.tagsinuse 1039.981291 # Cycle average of tags in use -system.cpu.icache.total_refs 161869191 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 6885 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 23510.412636 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1039.981291 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.507803 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.507803 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 161871216 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 161871216 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 161871216 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 161871216 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 161871216 # number of overall hits -system.cpu.icache.overall_hits::total 161871216 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 142683 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 142683 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 142683 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 142683 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 142683 # number of overall misses -system.cpu.icache.overall_misses::total 142683 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 931781000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 931781000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 931781000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 931781000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 931781000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 931781000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 162013899 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 162013899 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 162013899 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 162013899 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 162013899 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 162013899 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000881 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000881 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000881 # 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Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2534123 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 156.301277 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 1759751000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4088.382661 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.998140 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.998140 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 247356702 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 247356702 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148237858 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148237858 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 395594560 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 395594560 # 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Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1764467250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4088.352551 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.998133 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.998133 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 247340077 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 247340077 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148239061 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148239061 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 395579138 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 395579138 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 395579138 # number of overall hits +system.cpu.dcache.overall_hits::total 395579138 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2863342 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2863342 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 921141 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 921141 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3784483 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3784483 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3784483 # number of overall misses +system.cpu.dcache.overall_misses::total 3784483 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 57420164907 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 57420164907 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 25863644657 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 25863644657 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 83283809564 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 83283809564 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 83283809564 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 83283809564 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 250203419 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 250203419 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 399379708 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 399379708 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 399379708 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 399379708 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011441 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.011441 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006184 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.006184 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009478 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009478 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009478 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009478 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19914.627407 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 19914.627407 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27831.619220 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 27831.619220 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 21843.796332 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 21843.796332 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 21843.796332 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 21843.796332 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 6595 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 399363621 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 399363621 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 399363621 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 399363621 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011444 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.011444 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006176 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.006176 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.009476 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009476 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009476 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009476 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20053.547535 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 20053.547535 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28077.834617 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 28077.834617 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22006.654427 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22006.654427 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22006.654427 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22006.654427 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 7199 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 671 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 681 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.828614 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.571219 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2330801 # number of writebacks -system.cpu.dcache.writebacks::total 2330801 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1100153 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1100153 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 17067 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 17067 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1117220 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1117220 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1117220 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1117220 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762651 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1762651 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 905277 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 905277 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2667928 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2667928 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2667928 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2667928 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30822255503 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 30822255503 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 23648350501 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 23648350501 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 54470606004 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 54470606004 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 54470606004 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 54470606004 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 2330756 # number of writebacks +system.cpu.dcache.writebacks::total 2330756 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1100793 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1100793 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16986 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16986 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1117779 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1117779 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1117779 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1117779 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762549 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1762549 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 904155 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 904155 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2666704 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2666704 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2666704 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2666704 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30902624251 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 30902624251 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 23743181593 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 23743181593 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 54645805844 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 54645805844 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 54645805844 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 54645805844 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007044 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007044 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006069 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006069 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006680 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006680 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006680 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006680 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17486.306423 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17486.306423 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26122.778444 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26122.778444 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20416.820096 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20416.820096 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20416.820096 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20416.820096 # average overall mshr miss latency +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006062 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006062 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006677 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006677 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006677 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006677 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17532.916390 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17532.916390 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26260.078850 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26260.078850 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20491.890305 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20491.890305 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20491.890305 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20491.890305 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt index 3dc840346..5255bf68c 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt @@ -77,15 +77,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 3295745698 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.replacements 1253 # number of replacements -system.cpu.icache.tagsinuse 881.356491 # Cycle average of tags in use -system.cpu.icache.total_refs 1068344252 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 2814 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 379653.252310 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 881.356491 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.430350 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.430350 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 1253 # number of replacements +system.cpu.icache.tags.tagsinuse 881.356491 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1068344252 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 2814 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 379653.252310 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 881.356491 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.430350 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.430350 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1068344252 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1068344252 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1068344252 # number of demand (read+write) hits @@ -155,19 +155,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 39153.518124 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39153.518124 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 39153.518124 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 348459 # number of replacements -system.cpu.l2cache.tagsinuse 29286.402664 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3655011 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 380814 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 9.597890 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 755936431000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 21041.299337 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 139.758519 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 8105.344807 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.642129 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.004265 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.247355 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.893750 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 348459 # number of replacements +system.cpu.l2cache.tags.tagsinuse 29286.402664 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3655011 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 380814 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 9.597890 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 755936431000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 21041.299337 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 139.758519 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 8105.344807 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.642129 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004265 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.247355 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.893750 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 928 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1554848 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1555776 # number of ReadReq hits @@ -293,15 +293,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40006.362672 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.324318 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.354198 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 2514362 # number of replacements -system.cpu.dcache.tagsinuse 4086.415783 # Cycle average of tags in use -system.cpu.dcache.total_refs 530743930 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2518458 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 210.741624 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 8211724000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4086.415783 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.997660 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.997660 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 2514362 # number of replacements +system.cpu.dcache.tags.tagsinuse 4086.415783 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 530743930 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2518458 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 210.741624 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 8211724000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4086.415783 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997660 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997660 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 382374772 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 382374772 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 148369158 # number of WriteReq hits |