diff options
Diffstat (limited to 'tests/long/se/20.parser')
| -rw-r--r-- | tests/long/se/20.parser/ref/arm/linux/minor-timing/config.ini | 25 | ||||
| -rwxr-xr-x[-rw-r--r--] | tests/long/se/20.parser/ref/arm/linux/minor-timing/simerr | 1 | ||||
| -rwxr-xr-x[-rw-r--r--] | tests/long/se/20.parser/ref/arm/linux/minor-timing/simout | 14 | ||||
| -rw-r--r-- | tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt | 942 |
4 files changed, 502 insertions, 480 deletions
diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/minor-timing/config.ini index 452217687..e9edac26f 100644 --- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/config.ini +++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/config.ini @@ -23,6 +23,7 @@ load_offset=0 mem_mode=timing mem_ranges= memories=system.physmem +mmap_using_noreserve=false num_work_ids=16 readfile= symbolfile= @@ -167,6 +168,7 @@ type=ArmStage2MMU children=stage2_tlb eventq_index=0 stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +sys=system tlb=system.cpu.dtb [system.cpu.dstage2_mmu.stage2_tlb] @@ -184,7 +186,6 @@ eventq_index=0 is_stage2=true num_squash_per_cycle=2 sys=system -port=system.cpu.toL2Bus.slave[5] [system.cpu.dtb] type=ArmTLB @@ -661,6 +662,7 @@ type=ArmStage2MMU children=stage2_tlb eventq_index=0 stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +sys=system tlb=system.cpu.itb [system.cpu.istage2_mmu.stage2_tlb] @@ -678,7 +680,6 @@ eventq_index=0 is_stage2=true num_squash_per_cycle=2 sys=system -port=system.cpu.toL2Bus.slave[4] [system.cpu.itb] type=ArmTLB @@ -737,13 +738,16 @@ size=2097152 type=CoherentXBar clk_domain=system.cpu_clk_domain eventq_index=0 -header_cycles=1 +forward_latency=0 +frontend_latency=1 +response_latency=1 snoop_filter=Null +snoop_response_latency=1 system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.cpu.tracer] type=ExeTracer @@ -759,9 +763,9 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/parser +executable=/dist/m5/cpu2000/binaries/arm/linux/parser gid=100 -input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in +input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in kvmInSE=false max_stack_size=67108864 output=cout @@ -792,11 +796,14 @@ transition_latency=100000000 type=CoherentXBar clk_domain=system.clk_domain eventq_index=0 -header_cycles=1 +forward_latency=4 +frontend_latency=3 +response_latency=2 snoop_filter=Null +snoop_response_latency=4 system=system use_default_range=false -width=8 +width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side @@ -827,7 +834,7 @@ IDD62=0.000000 VDD=1.500000 VDD2=0.000000 activation_limit=4 -addr_mapping=RoRaBaChCo +addr_mapping=RoRaBaCoCh bank_groups_per_rank=0 banks_per_rank=8 burst_length=8 diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/simerr b/tests/long/se/20.parser/ref/arm/linux/minor-timing/simerr index 5d8946ede..be90b0340 100644..100755 --- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/simerr +++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/simerr @@ -1,2 +1,3 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) warn: Sockets disabled, not accepting gdb connections warn: CP14 unimplemented crn[8], opc1[2], crm[9], opc2[4] diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/simout b/tests/long/se/20.parser/ref/arm/linux/minor-timing/simout index 7e896fb1e..83790a04a 100644..100755 --- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/simout +++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/simout @@ -1,14 +1,12 @@ -Redirecting stdout to build/ARM/tests/opt/long/se/20.parser/arm/linux/minor-timing/simout -Redirecting stderr to build/ARM/tests/opt/long/se/20.parser/arm/linux/minor-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 7 2014 10:57:46 -gem5 started May 7 2014 15:30:22 -gem5 executing on cz3211bhr8 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/minor-timing -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/minor-timing +gem5 compiled Mar 15 2015 20:30:55 +gem5 started Mar 15 2015 20:31:14 +gem5 executing on zizzer2 +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/minor-timing -re /z/stever/hg/gem5/tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/minor-timing Global frequency set at 1000000000000 ticks per second - 0: system.cpu.isa: ISA system set to: 0 0x1e6be7a0 + 0: system.cpu.isa: ISA system set to: 0 0x3275620 info: Entering event queue @ 0. Starting simulation... Reading the dictionary files: ************************************************* @@ -70,4 +68,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 377875396500 because target called exit() +Exiting @ tick 366358475500 because target called exit() diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt index 8128561b2..409fcf8a5 100644 --- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt @@ -1,104 +1,104 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.366359 # Number of seconds simulated -sim_ticks 366358704500 # Number of ticks simulated -final_tick 366358704500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.366358 # Number of seconds simulated +sim_ticks 366358475500 # Number of ticks simulated +final_tick 366358475500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 242855 # Simulator instruction rate (inst/s) -host_op_rate 263044 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 175631724 # Simulator tick rate (ticks/s) -host_mem_usage 316616 # Number of bytes of host memory used -host_seconds 2085.95 # Real time elapsed on the host +host_inst_rate 156500 # Simulator instruction rate (inst/s) +host_op_rate 169511 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 113180486 # Simulator tick rate (ticks/s) +host_mem_usage 245616 # Number of bytes of host memory used +host_seconds 3236.94 # Real time elapsed on the host sim_insts 506582155 # Number of instructions simulated sim_ops 548695378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 221696 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9006016 # Number of bytes read from this memory -system.physmem.bytes_read::total 9227712 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9004224 # Number of bytes read from this memory +system.physmem.bytes_read::total 9225920 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 221696 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 221696 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6179648 # Number of bytes written to this memory -system.physmem.bytes_written::total 6179648 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 6180352 # Number of bytes written to this memory +system.physmem.bytes_written::total 6180352 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 3464 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 140719 # Number of read requests responded to by this memory -system.physmem.num_reads::total 144183 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 96557 # Number of write requests responded to by this memory -system.physmem.num_writes::total 96557 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.data 140691 # Number of read requests responded to by this memory +system.physmem.num_reads::total 144155 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 96568 # Number of write requests responded to by this memory +system.physmem.num_writes::total 96568 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.inst 605134 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 24582509 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 25187642 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 24577633 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 25182767 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 605134 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 605134 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 16867753 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 16867753 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 16867753 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::writebacks 16869685 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 16869685 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 16869685 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 605134 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 24582509 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 42055395 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 144183 # Number of read requests accepted -system.physmem.writeReqs 96557 # Number of write requests accepted -system.physmem.readBursts 144183 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 96557 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9220288 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7424 # Total number of bytes read from write queue -system.physmem.bytesWritten 6178496 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9227712 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6179648 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 116 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::cpu.data 24577633 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 42052451 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 144155 # Number of read requests accepted +system.physmem.writeReqs 96568 # Number of write requests accepted +system.physmem.readBursts 144155 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 96568 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9218240 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7680 # Total number of bytes read from write queue +system.physmem.bytesWritten 6178944 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9225920 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6180352 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 120 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9347 # Per bank write bursts -system.physmem.perBankRdBursts::1 9007 # Per bank write bursts -system.physmem.perBankRdBursts::2 8992 # Per bank write bursts -system.physmem.perBankRdBursts::3 8698 # Per bank write bursts -system.physmem.perBankRdBursts::4 9455 # Per bank write bursts +system.physmem.perBankRdBursts::0 9365 # Per bank write bursts +system.physmem.perBankRdBursts::1 8967 # Per bank write bursts +system.physmem.perBankRdBursts::2 8978 # Per bank write bursts +system.physmem.perBankRdBursts::3 8700 # Per bank write bursts +system.physmem.perBankRdBursts::4 9448 # Per bank write bursts system.physmem.perBankRdBursts::5 9342 # Per bank write bursts -system.physmem.perBankRdBursts::6 8946 # Per bank write bursts -system.physmem.perBankRdBursts::7 8102 # Per bank write bursts -system.physmem.perBankRdBursts::8 8570 # Per bank write bursts +system.physmem.perBankRdBursts::6 8938 # Per bank write bursts +system.physmem.perBankRdBursts::7 8105 # Per bank write bursts +system.physmem.perBankRdBursts::8 8575 # Per bank write bursts system.physmem.perBankRdBursts::9 8679 # Per bank write bursts -system.physmem.perBankRdBursts::10 8773 # Per bank write bursts -system.physmem.perBankRdBursts::11 9476 # Per bank write bursts -system.physmem.perBankRdBursts::12 9374 # Per bank write bursts -system.physmem.perBankRdBursts::13 9521 # Per bank write bursts -system.physmem.perBankRdBursts::14 8712 # Per bank write bursts -system.physmem.perBankRdBursts::15 9073 # Per bank write bursts -system.physmem.perBankWrBursts::0 6191 # Per bank write bursts -system.physmem.perBankWrBursts::1 6098 # Per bank write bursts +system.physmem.perBankRdBursts::10 8775 # Per bank write bursts +system.physmem.perBankRdBursts::11 9474 # Per bank write bursts +system.physmem.perBankRdBursts::12 9378 # Per bank write bursts +system.physmem.perBankRdBursts::13 9522 # Per bank write bursts +system.physmem.perBankRdBursts::14 8708 # Per bank write bursts +system.physmem.perBankRdBursts::15 9081 # Per bank write bursts +system.physmem.perBankWrBursts::0 6205 # Per bank write bursts +system.physmem.perBankWrBursts::1 6092 # Per bank write bursts system.physmem.perBankWrBursts::2 6005 # Per bank write bursts -system.physmem.perBankWrBursts::3 5815 # Per bank write bursts -system.physmem.perBankWrBursts::4 6163 # Per bank write bursts +system.physmem.perBankWrBursts::3 5814 # Per bank write bursts +system.physmem.perBankWrBursts::4 6161 # Per bank write bursts system.physmem.perBankWrBursts::5 6174 # Per bank write bursts -system.physmem.perBankWrBursts::6 6014 # Per bank write bursts -system.physmem.perBankWrBursts::7 5494 # Per bank write bursts -system.physmem.perBankWrBursts::8 5727 # Per bank write bursts +system.physmem.perBankWrBursts::6 6015 # Per bank write bursts +system.physmem.perBankWrBursts::7 5497 # Per bank write bursts +system.physmem.perBankWrBursts::8 5724 # Per bank write bursts system.physmem.perBankWrBursts::9 5822 # Per bank write bursts system.physmem.perBankWrBursts::10 5961 # Per bank write bursts -system.physmem.perBankWrBursts::11 6445 # Per bank write bursts -system.physmem.perBankWrBursts::12 6308 # Per bank write bursts +system.physmem.perBankWrBursts::11 6444 # Per bank write bursts +system.physmem.perBankWrBursts::12 6310 # Per bank write bursts system.physmem.perBankWrBursts::13 6277 # Per bank write bursts -system.physmem.perBankWrBursts::14 5998 # Per bank write bursts -system.physmem.perBankWrBursts::15 6047 # Per bank write bursts +system.physmem.perBankWrBursts::14 5996 # Per bank write bursts +system.physmem.perBankWrBursts::15 6049 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 366358675500 # Total gap between requests +system.physmem.totGap 366358446500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 144183 # Read request sizes (log2) +system.physmem.readPktSize::6 144155 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 96557 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 143693 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 352 # What read queue length does an incoming req see +system.physmem.writePktSize::6 96568 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 143662 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 351 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 22 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -144,26 +144,26 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2930 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5533 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5679 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5677 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5673 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5679 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5677 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5676 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5690 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5657 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2912 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3099 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5531 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5665 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5682 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5679 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5677 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5677 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5679 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5680 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5705 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5660 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 5642 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5648 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5587 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5575 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5653 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5593 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5579 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 9 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 8 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 5 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 3 # What write queue length does an incoming req see @@ -193,34 +193,34 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 65205 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 236.159558 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 156.546491 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 241.906067 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 24752 37.96% 37.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18185 27.89% 65.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 7019 10.76% 76.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7903 12.12% 88.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2061 3.16% 91.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1167 1.79% 93.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 745 1.14% 94.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 604 0.93% 95.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 2769 4.25% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 65205 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5568 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 25.873563 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 382.195910 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 5565 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 65262 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 235.919953 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 156.506308 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 241.385533 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 24794 37.99% 37.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18171 27.84% 65.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 7030 10.77% 76.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7953 12.19% 88.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2052 3.14% 91.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1171 1.79% 93.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 739 1.13% 94.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 589 0.90% 95.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 2763 4.23% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 65262 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5572 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 25.848887 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 382.035418 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 5569 99.95% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 2 0.04% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5568 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5568 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.338182 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.234627 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.449204 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-17 2631 47.25% 47.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18-19 2778 49.89% 97.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-21 61 1.10% 98.24% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 5572 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5572 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.326992 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.223724 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.446858 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-17 2657 47.68% 47.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18-19 2761 49.55% 97.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-21 56 1.01% 98.24% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::22-23 29 0.52% 98.76% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::24-25 20 0.36% 99.12% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::26-27 10 0.18% 99.30% # Writes before turning the bus around for reads @@ -239,66 +239,66 @@ system.physmem.wrPerTurnAround::58-59 1 0.02% 99.95% # Wr system.physmem.wrPerTurnAround::60-61 1 0.02% 99.96% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::72-73 1 0.02% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::78-79 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5568 # Writes before turning the bus around for reads -system.physmem.totQLat 1536843000 # Total ticks spent queuing -system.physmem.totMemAccLat 4238099250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 720335000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10667.56 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 5572 # Writes before turning the bus around for reads +system.physmem.totQLat 1537104750 # Total ticks spent queuing +system.physmem.totMemAccLat 4237761000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 720175000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10671.74 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29417.56 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 25.17 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 16.86 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 25.19 # Average system read bandwidth in MiByte/s +system.physmem.avgMemAccLat 29421.74 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 25.16 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 16.87 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 25.18 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 16.87 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.33 # Data bus utilization in percentage system.physmem.busUtilRead 0.20 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.13 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing -system.physmem.avgWrQLen 20.79 # Average write queue length when enqueuing -system.physmem.readRowHits 110982 # Number of row buffer hits during reads -system.physmem.writeRowHits 64419 # Number of row buffer hits during writes -system.physmem.readRowHitRate 77.03 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 66.72 # Row buffer hit rate for writes -system.physmem.avgGap 1521802.26 # Average gap between requests -system.physmem.pageHitRate 72.89 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 248111640 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 135378375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 560734200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 310741920 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 23928765120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 47516601060 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 178134108000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 250834440315 # Total energy per rank (pJ) -system.physmem_0.averagePower 684.668623 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 296034178750 # Time in different power states +system.physmem.avgWrQLen 20.57 # Average write queue length when enqueuing +system.physmem.readRowHits 110916 # Number of row buffer hits during reads +system.physmem.writeRowHits 64397 # Number of row buffer hits during writes +system.physmem.readRowHitRate 77.01 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 66.69 # Row buffer hit rate for writes +system.physmem.avgGap 1521908.78 # Average gap between requests +system.physmem.pageHitRate 72.86 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 248466960 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 135572250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 560157000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 310566960 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 23928256560 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 47486087820 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 178156194000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 250825301550 # Total energy per rank (pJ) +system.physmem_0.averagePower 684.658255 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 296072654000 # Time in different power states system.physmem_0.memoryStateTime::REF 12233260000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 58091210000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 58046909500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 244838160 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 133592250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 562988400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 314830800 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 23928765120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 46994125095 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 178592423250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 250771563075 # Total energy per rank (pJ) -system.physmem_1.averagePower 684.496987 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 296797282750 # Time in different power states +system.physmem_1.actEnergy 244634040 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 133480875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 562879200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 314740080 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 23928256560 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 47146698135 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 178453904250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 250784593140 # Total energy per rank (pJ) +system.physmem_1.averagePower 684.547137 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 296568978750 # Time in different power states system.physmem_1.memoryStateTime::REF 12233260000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 57328110000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 57550826250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 132587783 # Number of BP lookups -system.cpu.branchPred.condPredicted 98513206 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6558220 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 68845364 # Number of BTB lookups -system.cpu.branchPred.BTBHits 64852055 # Number of BTB hits +system.cpu.branchPred.lookups 132589371 # Number of BP lookups +system.cpu.branchPred.condPredicted 98514041 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6557944 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 68842060 # Number of BTB lookups +system.cpu.branchPred.BTBHits 64854431 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 94.199596 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 10016928 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 17846 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 94.207569 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 10017867 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 17926 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -417,24 +417,24 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 732717409 # number of cpu cycles simulated +system.cpu.numCycles 732716951 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 506582155 # Number of instructions committed system.cpu.committedOps 548695378 # Number of ops (including micro ops) committed -system.cpu.discardedOps 13466110 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 13466923 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.446394 # CPI: cycles per instruction +system.cpu.cpi 1.446393 # CPI: cycles per instruction system.cpu.ipc 0.691375 # IPC: instructions per cycle -system.cpu.tickCycles 695820940 # Number of cycles that the object actually ticked -system.cpu.idleCycles 36896469 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 1139887 # number of replacements -system.cpu.dcache.tags.tagsinuse 4070.954708 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 171283476 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1143983 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 149.725543 # Average number of references to valid blocks. +system.cpu.tickCycles 695825303 # Number of cycles that the object actually ticked +system.cpu.idleCycles 36891648 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 1139854 # number of replacements +system.cpu.dcache.tags.tagsinuse 4070.954710 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 171283379 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1143950 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 149.729778 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 4900143250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4070.954708 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 4070.954710 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.993885 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.993885 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -443,64 +443,72 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1 17 system.cpu.dcache.tags.age_task_id_blocks_1024::2 545 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 3507 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 346821767 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 346821767 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 114767712 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 114767712 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 53538682 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 53538682 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 346821558 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 346821558 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 114764882 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114764882 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 53538642 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 53538642 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 2773 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 2773 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 168306394 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168306394 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168306394 # number of overall hits -system.cpu.dcache.overall_hits::total 168306394 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 854792 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 854792 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 700624 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 700624 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1555416 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1555416 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1555416 # number of overall misses -system.cpu.dcache.overall_misses::total 1555416 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 14024046732 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 14024046732 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 22031424000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 22031424000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 36055470732 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 36055470732 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 36055470732 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 36055470732 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 115622504 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 115622504 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 168303524 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168303524 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168306297 # number of overall hits +system.cpu.dcache.overall_hits::total 168306297 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 854741 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 854741 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 700664 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 700664 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 20 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 20 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 1555405 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1555405 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1555425 # number of overall misses +system.cpu.dcache.overall_misses::total 1555425 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 14025846982 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 14025846982 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 22027401500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 22027401500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 36053248482 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 36053248482 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 36053248482 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 36053248482 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 115619623 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 115619623 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 2793 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 2793 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 169861810 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 169861810 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 169861810 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 169861810 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 169858929 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 169858929 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 169861722 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 169861722 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.007393 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.007393 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.012917 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.012917 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.012918 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.012918 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.007161 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.007161 # miss rate for SoftPFReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.009157 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.009157 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.009157 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.009157 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16406.385100 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16406.385100 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31445.431501 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31445.431501 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 23180.596530 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 23180.596530 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 23180.596530 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 23180.596530 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16409.470216 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16409.470216 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31437.895339 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31437.895339 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 23179.331738 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23179.331738 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 23179.033693 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 23179.033693 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -509,103 +517,111 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1068568 # number of writebacks -system.cpu.dcache.writebacks::total 1068568 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66956 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 66956 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 344477 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 344477 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 411433 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 411433 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 411433 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 411433 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 787836 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 787836 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356147 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 356147 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1143983 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1143983 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1143983 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1143983 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11930645015 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 11930645015 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10967643750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10967643750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22898288765 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 22898288765 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22898288765 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 22898288765 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006814 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006814 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006566 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006566 # mshr miss rate for WriteReq accesses +system.cpu.dcache.writebacks::writebacks 1068578 # number of writebacks +system.cpu.dcache.writebacks::total 1068578 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66974 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 66974 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 344497 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 344497 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 411471 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 411471 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 411471 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 411471 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 787767 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 787767 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356167 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 356167 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 16 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 16 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1143934 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1143934 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1143950 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1143950 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11930687015 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 11930687015 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10965407750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10965407750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1449000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1449000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22896094765 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 22896094765 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22897543765 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 22897543765 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006813 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006813 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006567 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006567 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.005729 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.005729 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006735 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.006735 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006735 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.006735 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15143.564162 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15143.564162 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30795.272037 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30795.272037 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20016.284127 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20016.284127 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20016.284127 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20016.284127 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15144.943892 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15144.943892 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30787.264822 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30787.264822 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 90562.500000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 90562.500000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20015.223575 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20015.223575 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20016.210293 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20016.210293 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 17670 # number of replacements -system.cpu.icache.tags.tagsinuse 1190.214047 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 200949213 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 19542 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 10282.939975 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 17681 # number of replacements +system.cpu.icache.tags.tagsinuse 1190.210021 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 200953825 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 19553 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 10277.390937 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1190.214047 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.581159 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.581159 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1190.210021 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.581157 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.581157 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1872 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 65 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 58 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 303 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1405 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 298 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1410 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.914062 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 401957052 # Number of tag accesses -system.cpu.icache.tags.data_accesses 401957052 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 200949213 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 200949213 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 200949213 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 200949213 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 200949213 # number of overall hits -system.cpu.icache.overall_hits::total 200949213 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 19542 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 19542 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 19542 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 19542 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 19542 # number of overall misses -system.cpu.icache.overall_misses::total 19542 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 494400997 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 494400997 # 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Number of tag accesses +system.cpu.icache.tags.data_accesses 401966309 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 200953825 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 200953825 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 200953825 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 200953825 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 200953825 # number of overall hits +system.cpu.icache.overall_hits::total 200953825 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 19553 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 19553 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 19553 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 19553 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 19553 # number of overall misses +system.cpu.icache.overall_misses::total 19553 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 493452495 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 493452495 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 493452495 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 493452495 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 493452495 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 493452495 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 200973378 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 200973378 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 200973378 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 200973378 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 200973378 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 200973378 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000097 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000097 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000097 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000097 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000097 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000097 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25299.406253 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 25299.406253 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 25299.406253 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 25299.406253 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 25299.406253 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 25299.406253 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25236.664195 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 25236.664195 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 25236.664195 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 25236.664195 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 25236.664195 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 25236.664195 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -614,122 +630,122 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 19542 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 19542 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 19542 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 19542 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 19542 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 19542 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 463701003 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 463701003 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 463701003 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 463701003 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 463701003 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 463701003 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 19553 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 19553 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 19553 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 19553 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 19553 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 19553 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 462727005 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 462727005 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 462727005 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 462727005 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 462727005 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 462727005 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000097 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000097 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000097 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000097 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000097 # 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average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 23665.269012 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23665.269012 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 23665.269012 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 111429 # number of replacements -system.cpu.l2cache.tags.tagsinuse 27648.762381 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1684764 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 142617 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 11.813206 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 111401 # number of replacements +system.cpu.l2cache.tags.tagsinuse 27648.660571 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1684556 # 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Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::writebacks 23520.663233 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 390.227273 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 3737.770065 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.717794 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.011909 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.114068 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.843770 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 31186 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 321 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4941 # 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average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67183.475579 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67175.561613 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66854.070439 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67183.475579 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67175.561613 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_misses::cpu.data 140691 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 144155 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 230478500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2786732250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3017210750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6666945750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6666945750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 230478500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9453678000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 9684156500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 230478500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9453678000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9684156500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.177160 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.050550 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.053618 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.283042 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.283042 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.177160 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.122987 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.123897 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.177160 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.122987 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.123897 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 66535.363741 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70000.810098 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69723.407820 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66087.229012 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66087.229012 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66535.363741 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67194.617993 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67178.776317 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66535.363741 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67194.617993 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67178.776317 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 807125 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 807125 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1068568 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 356400 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 356400 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 39084 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3356534 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3395618 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1250688 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141603264 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 142853952 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 807086 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 807086 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1068578 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 356417 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 356417 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 39106 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3356478 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 3395584 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1251392 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141601792 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 142853184 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 2232093 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 2232081 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 2232093 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 2232081 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2232093 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2184614500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2232081 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2184618500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 30006497 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 30027495 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1744748235 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1744688735 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.membus.trans_dist::ReadReq 43319 # Transaction distribution -system.membus.trans_dist::ReadResp 43319 # Transaction distribution -system.membus.trans_dist::Writeback 96557 # Transaction distribution -system.membus.trans_dist::ReadExReq 100864 # Transaction distribution -system.membus.trans_dist::ReadExResp 100864 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 384923 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 384923 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15407360 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 15407360 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 43274 # Transaction distribution +system.membus.trans_dist::ReadResp 43274 # Transaction distribution +system.membus.trans_dist::Writeback 96568 # Transaction distribution +system.membus.trans_dist::ReadExReq 100881 # Transaction distribution +system.membus.trans_dist::ReadExResp 100881 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 384878 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 384878 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15406272 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 15406272 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 240740 # Request fanout histogram +system.membus.snoop_fanout::samples 240723 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 240740 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 240723 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 240740 # Request fanout histogram -system.membus.reqLayer0.occupancy 679202000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 240723 # Request fanout histogram +system.membus.reqLayer0.occupancy 679184500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 765364000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 765222500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- |