diff options
Diffstat (limited to 'tests/long/se/20.parser')
26 files changed, 3859 insertions, 0 deletions
diff --git a/tests/long/se/20.parser/ref/alpha/tru64/NOTE b/tests/long/se/20.parser/ref/alpha/tru64/NOTE new file mode 100644 index 000000000..5e7d8c358 --- /dev/null +++ b/tests/long/se/20.parser/ref/alpha/tru64/NOTE @@ -0,0 +1,6 @@ +I removed the reference outputs for this program because it's taking +way too long... over an hour for simple-atomic and over 19 hrs for +o3-timing. We need to find a shorter input if we want to keep this +in the regressions. + +Steve diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini new file mode 100644 index 000000000..e2c071016 --- /dev/null +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini @@ -0,0 +1,535 @@ +[root] +type=Root +children=system +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +memories=system.physmem +num_work_ids=16 +physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.port[0] + +[system.cpu] +type=DerivO3CPU +children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload +BTBEntries=4096 +BTBTagSize=16 +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +RASSize=16 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +cachePorts=200 +checker=Null +choiceCtrBits=2 +choicePredictorSize=8192 +clock=500 +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +defer_registration=false +dispatchWidth=8 +do_checkpoint_insts=true +do_statistics_insts=true +dtb=system.cpu.dtb +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +globalCtrBits=2 +globalHistoryBits=13 +globalPredictorSize=8192 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +instShiftAmt=2 +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +localCtrBits=2 +localHistoryBits=11 +localHistoryTableSize=2048 +localPredictorSize=2048 +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numIQEntries=64 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +phase=0 +predType=tournament +progress_interval=0 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +squashWidth=8 +store_set_clear_period=250000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wbDepth=1 +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=10 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=262144 +subblock_size=0 +tgts_per_mshr=20 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.port[1] + +[system.cpu.dtb] +type=ArmTLB +size=64 + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList +count=6 +opList=system.cpu.fuPool.FUList0.opList + +[system.cpu.fuPool.FUList0.opList] +type=OpDesc +issueLat=1 +opClass=IntAlu +opLat=1 + +[system.cpu.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +issueLat=1 +opClass=IntMult +opLat=3 + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +issueLat=19 +opClass=IntDiv +opLat=20 + +[system.cpu.fuPool.FUList2] +type=FUDesc +children=opList0 opList1 opList2 +count=4 +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 + +[system.cpu.fuPool.FUList2.opList0] +type=OpDesc +issueLat=1 +opClass=FloatAdd +opLat=2 + +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +issueLat=1 +opClass=FloatCmp +opLat=2 + +[system.cpu.fuPool.FUList2.opList2] +type=OpDesc +issueLat=1 +opClass=FloatCvt +opLat=2 + +[system.cpu.fuPool.FUList3] +type=FUDesc +children=opList0 opList1 opList2 +count=2 +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 + +[system.cpu.fuPool.FUList3.opList0] +type=OpDesc +issueLat=1 +opClass=FloatMult +opLat=4 + +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +issueLat=12 +opClass=FloatDiv +opLat=12 + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +issueLat=24 +opClass=FloatSqrt +opLat=24 + +[system.cpu.fuPool.FUList4] +type=FUDesc +children=opList +count=0 +opList=system.cpu.fuPool.FUList4.opList + +[system.cpu.fuPool.FUList4.opList] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu.fuPool.FUList5] +type=FUDesc +children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 +count=4 +opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 + +[system.cpu.fuPool.FUList5.opList00] +type=OpDesc +issueLat=1 +opClass=SimdAdd +opLat=1 + +[system.cpu.fuPool.FUList5.opList01] +type=OpDesc +issueLat=1 +opClass=SimdAddAcc +opLat=1 + +[system.cpu.fuPool.FUList5.opList02] +type=OpDesc +issueLat=1 +opClass=SimdAlu +opLat=1 + +[system.cpu.fuPool.FUList5.opList03] +type=OpDesc +issueLat=1 +opClass=SimdCmp +opLat=1 + +[system.cpu.fuPool.FUList5.opList04] +type=OpDesc +issueLat=1 +opClass=SimdCvt +opLat=1 + +[system.cpu.fuPool.FUList5.opList05] +type=OpDesc +issueLat=1 +opClass=SimdMisc +opLat=1 + +[system.cpu.fuPool.FUList5.opList06] +type=OpDesc +issueLat=1 +opClass=SimdMult +opLat=1 + +[system.cpu.fuPool.FUList5.opList07] +type=OpDesc +issueLat=1 +opClass=SimdMultAcc +opLat=1 + +[system.cpu.fuPool.FUList5.opList08] +type=OpDesc +issueLat=1 +opClass=SimdShift +opLat=1 + +[system.cpu.fuPool.FUList5.opList09] +type=OpDesc +issueLat=1 +opClass=SimdShiftAcc +opLat=1 + +[system.cpu.fuPool.FUList5.opList10] +type=OpDesc +issueLat=1 +opClass=SimdSqrt +opLat=1 + +[system.cpu.fuPool.FUList5.opList11] +type=OpDesc +issueLat=1 +opClass=SimdFloatAdd +opLat=1 + +[system.cpu.fuPool.FUList5.opList12] +type=OpDesc +issueLat=1 +opClass=SimdFloatAlu +opLat=1 + +[system.cpu.fuPool.FUList5.opList13] +type=OpDesc +issueLat=1 +opClass=SimdFloatCmp +opLat=1 + +[system.cpu.fuPool.FUList5.opList14] +type=OpDesc +issueLat=1 +opClass=SimdFloatCvt +opLat=1 + +[system.cpu.fuPool.FUList5.opList15] +type=OpDesc +issueLat=1 +opClass=SimdFloatDiv +opLat=1 + +[system.cpu.fuPool.FUList5.opList16] +type=OpDesc +issueLat=1 +opClass=SimdFloatMisc +opLat=1 + +[system.cpu.fuPool.FUList5.opList17] +type=OpDesc +issueLat=1 +opClass=SimdFloatMult +opLat=1 + +[system.cpu.fuPool.FUList5.opList18] +type=OpDesc +issueLat=1 +opClass=SimdFloatMultAcc +opLat=1 + +[system.cpu.fuPool.FUList5.opList19] +type=OpDesc +issueLat=1 +opClass=SimdFloatSqrt +opLat=1 + +[system.cpu.fuPool.FUList6] +type=FUDesc +children=opList +count=0 +opList=system.cpu.fuPool.FUList6.opList + +[system.cpu.fuPool.FUList6.opList] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu.fuPool.FUList7] +type=FUDesc +children=opList0 opList1 +count=4 +opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 + +[system.cpu.fuPool.FUList7.opList0] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu.fuPool.FUList7.opList1] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu.fuPool.FUList8] +type=FUDesc +children=opList +count=1 +opList=system.cpu.fuPool.FUList8.opList + +[system.cpu.fuPool.FUList8.opList] +type=OpDesc +issueLat=3 +opClass=IprAccess +opLat=3 + +[system.cpu.icache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=10 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=131072 +subblock_size=0 +tgts_per_mshr=20 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.port[0] + +[system.cpu.itb] +type=ArmTLB +size=64 + +[system.cpu.l2cache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=false +latency=1000 +max_miss_count=0 +mshrs=10 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=2097152 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.port[2] +mem_side=system.membus.port[2] + +[system.cpu.toL2Bus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +use_default_range=false +width=64 +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side + +[system.cpu.tracer] +type=ExeTracer + +[system.cpu.workload] +type=LiveProcess +cmd=parser 2.1.dict -batch +cwd=build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing +egid=100 +env= +errout=cerr +euid=100 +executable=/dist/m5/cpu2000/binaries/arm/linux/parser +gid=100 +input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=114600000000 +system=system +uid=100 + +[system.membus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +use_default_range=false +width=64 +port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side + +[system.physmem] +type=PhysicalMemory +file= +latency=30000 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.membus.port[1] + diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr new file mode 100755 index 000000000..e45cd058f --- /dev/null +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr @@ -0,0 +1,2 @@ +warn: Sockets disabled, not accepting gdb connections +hack: be nice to actually delete the event here diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout new file mode 100755 index 000000000..c61c0591a --- /dev/null +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout @@ -0,0 +1,70 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Jan 23 2012 04:16:21 +gem5 started Jan 23 2012 08:49:36 +gem5 executing on zizzer +command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... + + Reading the dictionary files: ************************************************* + + +Welcome to the Link Parser -- Version 2.1 + + Copyright (C) 1991-1995 Daniel Sleator and Davy Temperley + +Processing sentences in batch mode + +info: Increasing stack size by one page. +Echoing of input sentence turned on. +* as had expected the party to be a success , it was a success +* do you know where John 's +* he said that , finding that it was impossible to get work as a waiter , he would work as a janitor +info: Increasing stack size by one page. +* how fast the program is it +* I am wondering whether to invite to the party +* I gave him for his birthday it +* I thought terrible after our discussion +* I wonder how much money have you earned +* Janet who is an expert on dogs helped me choose one +* she interviewed more programmers than was hired +* such flowers are found chiefly particularly in Europe +* the dogs some of which were very large ran after the man +* the man whom I play tennis is here +* there is going to be an important meeting January +* to pretend that our program is usable in its current form would be happy +* we're thinking about going to a movie this theater +* which dog you said you chased +- also invited to the meeting were several prominent scientists +- he ran home so quickly that his mother could hardly believe he had called from school +- so many people attended that they spilled over into several neighboring fields +- voting in favor of the bill were 36 Republicans and 4 moderate Democrats +: Grace may not be possible to fix the problem + any program as good as ours should be useful + biochemically , I think the experiment has a lot of problems + Fred has had five years of experience as a programmer + he is looking for another job + how did John do it + how many more people do you think will come + how much more spilled + I have more money than John has time + I made it clear that I was angry + I wonder how John did it + I wonder how much more quickly he ran + invite John and whoever else you want to invite + it is easier to ignore the problem than it is to solve it + many who initially supported Thomas later changed their minds + neither Mary nor Louise are coming to the party + she interviewed more programmers than were hired + telling Joe that Sue was coming to the party would create a real problem + the man with whom I play tennis is here + there is a dog in the park + this is not the man we know and love + we like to eat at restaurants , usually on weekends + what did John say he thought you should do + about 2 million people attended + the five best costumes got prizes +No errors! +Exiting @ tick 274198757500 because target called exit() diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt new file mode 100644 index 000000000..0cc2b2b8d --- /dev/null +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -0,0 +1,545 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.274199 # Number of seconds simulated +sim_ticks 274198757500 # Number of ticks simulated +final_tick 274198757500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 114096 # Simulator instruction rate (inst/s) +host_tick_rate 54566255 # Simulator tick rate (ticks/s) +host_mem_usage 225172 # Number of bytes of host memory used +host_seconds 5025.06 # Real time elapsed on the host +sim_insts 573341162 # Number of instructions simulated +system.physmem.bytes_read 15248640 # Number of bytes read from this memory +system.physmem.bytes_inst_read 230400 # Number of instructions bytes read from this memory +system.physmem.bytes_written 10960192 # Number of bytes written to this memory +system.physmem.num_reads 238260 # Number of read requests responded to by this memory +system.physmem.num_writes 171253 # Number of write requests responded to by this memory +system.physmem.num_other 0 # Number of other requests responded to by this memory +system.physmem.bw_read 55611631 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 840266 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 39971706 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 95583336 # Total bandwidth to/from this memory (bytes/s) +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 548 # Number of system calls +system.cpu.numCycles 548397516 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.BPredUnit.lookups 225101784 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 179007547 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 18307036 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 189868979 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 156087931 # Number of BTB hits +system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.BPredUnit.usedRAS 11743928 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 2589266 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 154237973 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 996342059 # Number of instructions fetch has processed +system.cpu.fetch.Branches 225101784 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 167831859 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 251951083 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 70115496 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 88916227 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 76 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 27190 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 141601056 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 4591339 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 544609039 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.120756 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.818747 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 292670234 53.74% 53.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 22602609 4.15% 57.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 39324759 7.22% 65.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 38673680 7.10% 72.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 44132407 8.10% 80.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 15219761 2.79% 83.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 18468380 3.39% 86.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 13866800 2.55% 89.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 59650409 10.95% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 544609039 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.410472 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.816825 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 173360184 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 84631968 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 232819510 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 4407510 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 49389867 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 33096702 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 88546 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 1070717063 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 220828 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 49389867 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 189439670 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 6246457 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 67211324 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 221002512 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 11319209 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 984442373 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1013 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2966416 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 5236155 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 73 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1176369692 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 4273292331 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 4273289228 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 3103 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 672199296 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 504170396 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 6164964 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 6164681 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 63358237 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 196378247 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 77986326 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 17967729 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 12612066 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 870602735 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 7830625 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 735457773 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1536942 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 302215535 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 751654986 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 3952431 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 544609039 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.350433 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.595771 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 241479375 44.34% 44.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 95418106 17.52% 61.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 86231703 15.83% 77.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 59231990 10.88% 88.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 36938301 6.78% 95.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 14710122 2.70% 98.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 6373652 1.17% 99.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3471755 0.64% 99.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 754035 0.14% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 544609039 # Number of insts issued each cycle +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 133367 1.38% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 6658147 68.82% 70.20% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2883419 29.80% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 497367446 67.63% 67.63% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 380524 0.05% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 142 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 170820646 23.23% 90.91% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 66889012 9.09% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 735457773 # Type of FU issued +system.cpu.iq.rate 1.341103 # Inst issue rate +system.cpu.iq.fu_busy_cnt 9674933 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.013155 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2026736140 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1180706061 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 693772826 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 320 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 454 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 745132544 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 162 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 8466293 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.squashedLoads 69605317 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 50613 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 61790 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 20382475 # Number of stores squashed +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.rescheduledLoads 28472 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 334 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewSquashCycles 49389867 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2700739 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 121924 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 887765924 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 12225511 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 196378247 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 77986326 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 6083275 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 46564 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 7422 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 61790 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 18530018 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 5460534 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 23990552 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 711163338 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 161856987 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 24294435 # Number of squashed instructions skipped in execute +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.exec_nop 9332564 # number of nop insts executed +system.cpu.iew.exec_refs 226770071 # number of memory reference insts executed +system.cpu.iew.exec_branches 147519559 # Number of branches executed +system.cpu.iew.exec_stores 64913084 # Number of stores executed +system.cpu.iew.exec_rate 1.296803 # Inst execution rate +system.cpu.iew.wb_sent 699318417 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 693772842 # cumulative count of insts written-back +system.cpu.iew.wb_producers 395045304 # num instructions producing a value +system.cpu.iew.wb_consumers 663504976 # num instructions consuming a value +system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.wb_rate 1.265091 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.595392 # average fanout of values written-back +system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.commit.commitCommittedInsts 574685046 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 313100037 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 3878194 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 20503761 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 495219173 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.160466 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.863525 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 259975062 52.50% 52.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 116222276 23.47% 75.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 44533135 8.99% 84.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 21295357 4.30% 89.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 19840150 4.01% 93.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7283820 1.47% 94.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7518006 1.52% 96.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3788243 0.76% 97.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 14763124 2.98% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 495219173 # Number of insts commited each cycle +system.cpu.commit.count 574685046 # Number of instructions committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.refs 184376781 # Number of memory references committed +system.cpu.commit.loads 126772930 # Number of loads committed +system.cpu.commit.membars 1488542 # Number of memory barriers committed +system.cpu.commit.branches 120192115 # Number of branches committed +system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. +system.cpu.commit.int_insts 473701197 # Number of committed integer instructions. +system.cpu.commit.function_calls 9757362 # Number of function calls committed. +system.cpu.commit.bw_lim_events 14763124 # number cycles where commit BW limit reached +system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits +system.cpu.rob.rob_reads 1368233994 # The number of ROB reads +system.cpu.rob.rob_writes 1825140894 # The number of ROB writes +system.cpu.timesIdled 96084 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 3788477 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 573341162 # Number of Instructions Simulated +system.cpu.committedInsts_total 573341162 # Number of Instructions Simulated +system.cpu.cpi 0.956494 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.956494 # CPI: Total CPI of All Threads +system.cpu.ipc 1.045485 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.045485 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3291621496 # number of integer regfile reads +system.cpu.int_regfile_writes 815258640 # number of integer regfile writes +system.cpu.fp_regfile_reads 16 # number of floating regfile reads +system.cpu.misc_regfile_reads 1231509968 # number of misc regfile reads +system.cpu.misc_regfile_writes 4463832 # number of misc regfile writes +system.cpu.icache.replacements 12844 # number of replacements +system.cpu.icache.tagsinuse 1060.855578 # Cycle average of tags in use +system.cpu.icache.total_refs 141584558 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 14688 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 9639.471541 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 1060.855578 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.517996 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 141584561 # number of ReadReq hits +system.cpu.icache.demand_hits 141584561 # number of demand (read+write) hits +system.cpu.icache.overall_hits 141584561 # number of overall hits +system.cpu.icache.ReadReq_misses 16495 # number of ReadReq misses +system.cpu.icache.demand_misses 16495 # number of demand (read+write) misses +system.cpu.icache.overall_misses 16495 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 235861500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 235861500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 235861500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 141601056 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 141601056 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 141601056 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.000116 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.000116 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000116 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 14298.969385 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 14298.969385 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 14298.969385 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks 1 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits 1651 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 1651 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 1651 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 14844 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 14844 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 14844 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.ReadReq_mshr_miss_latency 154845500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 154845500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 154845500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000105 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.000105 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.000105 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 10431.521153 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 10431.521153 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 10431.521153 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 1212341 # number of replacements +system.cpu.dcache.tagsinuse 4058.230538 # Cycle average of tags in use +system.cpu.dcache.total_refs 204314278 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1216437 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 167.961249 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 5623770000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4058.230538 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.990779 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 146820758 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 52766592 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits 2494784 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits 2231915 # number of StoreCondReq hits +system.cpu.dcache.demand_hits 199587350 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 199587350 # number of overall hits +system.cpu.dcache.ReadReq_misses 1243424 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 1472714 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses 59 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses 2716138 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 2716138 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 14347379500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 25015184497 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency 557000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency 39362563997 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 39362563997 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 148064182 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses 54239306 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses 2494843 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses 2231915 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 202303488 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 202303488 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.008398 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.027152 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate 0.000024 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate 0.013426 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.013426 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 11538.605898 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 16985.772185 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency 9440.677966 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency 14492.107543 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 14492.107543 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 502000 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 64 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 7843.750000 # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks 1079461 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 367349 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 1132203 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits 59 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits 1499552 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 1499552 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 876075 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 340511 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 1216586 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 1216586 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency 6316165000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 4359865500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 10676030500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 10676030500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.005917 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.006278 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.006014 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.006014 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7209.616757 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12803.890330 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 8775.401410 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 8775.401410 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.replacements 219133 # number of replacements +system.cpu.l2cache.tagsinuse 21061.116186 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1567440 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 239478 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 6.545236 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 204357736000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::0 7517.812526 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 13543.303660 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.229425 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.413309 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 760340 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 1079462 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits 116 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits 232507 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 992847 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 992847 # number of overall hits +system.cpu.l2cache.ReadReq_misses 130056 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses 33 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses 108226 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 238282 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 238282 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 4448635000 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency 68000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 3706374500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 8155009500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 8155009500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 890396 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 1079462 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses 149 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 340733 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 1231129 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 1231129 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.146065 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate 0.221477 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.317627 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.193548 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.193548 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34205.534539 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency 2060.606061 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34246.618188 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34224.194442 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34224.194442 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.writebacks 171253 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits 19 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits 19 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits 19 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses 130037 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses 33 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 108226 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 238263 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 238263 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 4037689500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1023000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 3355622000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 7393311500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 7393311500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.146044 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.221477 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.317627 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.193532 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.193532 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31050.312603 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31005.691793 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31030.044531 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31030.044531 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate + +---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini new file mode 100644 index 000000000..cbe7d05b4 --- /dev/null +++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini @@ -0,0 +1,102 @@ +[root] +type=Root +children=system +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +memories=system.physmem +num_work_ids=16 +physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.port[0] + +[system.cpu] +type=AtomicSimpleCPU +children=dtb itb tracer workload +checker=Null +clock=500 +cpu_id=0 +defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true +dtb=system.cpu.dtb +function_trace=false +function_trace_start=0 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +progress_interval=0 +simulate_data_stalls=false +simulate_inst_stalls=false +system=system +tracer=system.cpu.tracer +width=1 +workload=system.cpu.workload +dcache_port=system.membus.port[3] +icache_port=system.membus.port[2] + +[system.cpu.dtb] +type=ArmTLB +size=64 + +[system.cpu.itb] +type=ArmTLB +size=64 + +[system.cpu.tracer] +type=ExeTracer + +[system.cpu.workload] +type=LiveProcess +cmd=parser 2.1.dict -batch +cwd=build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-atomic +egid=100 +env= +errout=cerr +euid=100 +executable=/dist/m5/cpu2000/binaries/arm/linux/parser +gid=100 +input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=114600000000 +system=system +uid=100 + +[system.membus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +use_default_range=false +width=64 +port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port + +[system.physmem] +type=PhysicalMemory +file= +latency=30000 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.membus.port[1] + diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simerr b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simerr new file mode 100755 index 000000000..e45cd058f --- /dev/null +++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simerr @@ -0,0 +1,2 @@ +warn: Sockets disabled, not accepting gdb connections +hack: be nice to actually delete the event here diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout new file mode 100755 index 000000000..e26a927e8 --- /dev/null +++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout @@ -0,0 +1,70 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Jan 23 2012 04:16:21 +gem5 started Jan 23 2012 08:54:41 +gem5 executing on zizzer +command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-atomic +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... + + Reading the dictionary files: ************************************************* + + +Welcome to the Link Parser -- Version 2.1 + + Copyright (C) 1991-1995 Daniel Sleator and Davy Temperley + +Processing sentences in batch mode + +info: Increasing stack size by one page. +Echoing of input sentence turned on. +* as had expected the party to be a success , it was a success +* do you know where John 's +* he said that , finding that it was impossible to get work as a waiter , he would work as a janitor +info: Increasing stack size by one page. +* how fast the program is it +* I am wondering whether to invite to the party +* I gave him for his birthday it +* I thought terrible after our discussion +* I wonder how much money have you earned +* Janet who is an expert on dogs helped me choose one +* she interviewed more programmers than was hired +* such flowers are found chiefly particularly in Europe +* the dogs some of which were very large ran after the man +* the man whom I play tennis is here +* there is going to be an important meeting January +* to pretend that our program is usable in its current form would be happy +* we're thinking about going to a movie this theater +* which dog you said you chased +- also invited to the meeting were several prominent scientists +- he ran home so quickly that his mother could hardly believe he had called from school +- so many people attended that they spilled over into several neighboring fields +- voting in favor of the bill were 36 Republicans and 4 moderate Democrats +: Grace may not be possible to fix the problem + any program as good as ours should be useful + biochemically , I think the experiment has a lot of problems + Fred has had five years of experience as a programmer + he is looking for another job + how did John do it + how many more people do you think will come + how much more spilled + I have more money than John has time + I made it clear that I was angry + I wonder how John did it + I wonder how much more quickly he ran + invite John and whoever else you want to invite + it is easier to ignore the problem than it is to solve it + many who initially supported Thomas later changed their minds + neither Mary nor Louise are coming to the party + she interviewed more programmers than were hired + telling Joe that Sue was coming to the party would create a real problem + the man with whom I play tennis is here + there is a dog in the park + this is not the man we know and love + we like to eat at restaurants , usually on weekends + what did John say he thought you should do + about 2 million people attended + the five best costumes got prizes +No errors! +Exiting @ tick 290498972000 because target called exit() diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt new file mode 100644 index 000000000..12a51d6fd --- /dev/null +++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt @@ -0,0 +1,87 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.290499 # Number of seconds simulated +sim_ticks 290498972000 # Number of ticks simulated +final_tick 290498972000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 3123764 # Simulator instruction rate (inst/s) +host_tick_rate 1589318228 # Simulator tick rate (ticks/s) +host_mem_usage 213568 # Number of bytes of host memory used +host_seconds 182.78 # Real time elapsed on the host +sim_insts 570968176 # Number of instructions simulated +system.physmem.bytes_read 2489298238 # Number of bytes read from this memory +system.physmem.bytes_inst_read 2066445536 # Number of instructions bytes read from this memory +system.physmem.bytes_written 216067624 # Number of bytes written to this memory +system.physmem.num_reads 641840242 # Number of read requests responded to by this memory +system.physmem.num_writes 55727847 # Number of write requests responded to by this memory +system.physmem.num_other 0 # Number of other requests responded to by this memory +system.physmem.bw_read 8569043191 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 7113434935 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 743781028 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 9312824219 # Total bandwidth to/from this memory (bytes/s) +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 548 # Number of system calls +system.cpu.numCycles 580997945 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.num_insts 570968176 # Number of instructions executed +system.cpu.num_int_alu_accesses 470727703 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses +system.cpu.num_func_calls 15725605 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 95872736 # number of instructions that are conditional controls +system.cpu.num_int_insts 470727703 # number of integer instructions +system.cpu.num_fp_insts 16 # number of float instructions +system.cpu.num_int_register_reads 2465023721 # number of times the integer registers were read +system.cpu.num_int_register_writes 646169365 # number of times the integer registers were written +system.cpu.num_fp_register_reads 16 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_mem_refs 182890035 # number of memory refs +system.cpu.num_load_insts 126029556 # Number of load instructions +system.cpu.num_store_insts 56860479 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 580997945 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles + +---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini new file mode 100644 index 000000000..5a2d86232 --- /dev/null +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini @@ -0,0 +1,205 @@ +[root] +type=Root +children=system +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +memories=system.physmem +num_work_ids=16 +physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.port[0] + +[system.cpu] +type=TimingSimpleCPU +children=dcache dtb icache itb l2cache toL2Bus tracer workload +checker=Null +clock=500 +cpu_id=0 +defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true +dtb=system.cpu.dtb +function_trace=false +function_trace_start=0 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +progress_interval=0 +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=10 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=262144 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.port[1] + +[system.cpu.dtb] +type=ArmTLB +size=64 + +[system.cpu.icache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=10 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=131072 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.port[0] + +[system.cpu.itb] +type=ArmTLB +size=64 + +[system.cpu.l2cache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=false +latency=10000 +max_miss_count=0 +mshrs=10 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=100000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=2097152 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.port[2] +mem_side=system.membus.port[2] + +[system.cpu.toL2Bus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +use_default_range=false +width=64 +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side + +[system.cpu.tracer] +type=ExeTracer + +[system.cpu.workload] +type=LiveProcess +cmd=parser 2.1.dict -batch +cwd=build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-timing +egid=100 +env= +errout=cerr +euid=100 +executable=/dist/m5/cpu2000/binaries/arm/linux/parser +gid=100 +input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=114600000000 +system=system +uid=100 + +[system.membus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +use_default_range=false +width=64 +port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side + +[system.physmem] +type=PhysicalMemory +file= +latency=30000 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.membus.port[1] + diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/simerr b/tests/long/se/20.parser/ref/arm/linux/simple-timing/simerr new file mode 100755 index 000000000..e45cd058f --- /dev/null +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/simerr @@ -0,0 +1,2 @@ +warn: Sockets disabled, not accepting gdb connections +hack: be nice to actually delete the event here diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout b/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout new file mode 100755 index 000000000..8c1353073 --- /dev/null +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout @@ -0,0 +1,70 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Jan 23 2012 04:16:21 +gem5 started Jan 23 2012 08:54:55 +gem5 executing on zizzer +command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... + + Reading the dictionary files: ************************************************* + + +Welcome to the Link Parser -- Version 2.1 + + Copyright (C) 1991-1995 Daniel Sleator and Davy Temperley + +Processing sentences in batch mode + +info: Increasing stack size by one page. +Echoing of input sentence turned on. +* as had expected the party to be a success , it was a success +* do you know where John 's +* he said that , finding that it was impossible to get work as a waiter , he would work as a janitor +info: Increasing stack size by one page. +* how fast the program is it +* I am wondering whether to invite to the party +* I gave him for his birthday it +* I thought terrible after our discussion +* I wonder how much money have you earned +* Janet who is an expert on dogs helped me choose one +* she interviewed more programmers than was hired +* such flowers are found chiefly particularly in Europe +* the dogs some of which were very large ran after the man +* the man whom I play tennis is here +* there is going to be an important meeting January +* to pretend that our program is usable in its current form would be happy +* we're thinking about going to a movie this theater +* which dog you said you chased +- also invited to the meeting were several prominent scientists +- he ran home so quickly that his mother could hardly believe he had called from school +- so many people attended that they spilled over into several neighboring fields +- voting in favor of the bill were 36 Republicans and 4 moderate Democrats +: Grace may not be possible to fix the problem + any program as good as ours should be useful + biochemically , I think the experiment has a lot of problems + Fred has had five years of experience as a programmer + he is looking for another job + how did John do it + how many more people do you think will come + how much more spilled + I have more money than John has time + I made it clear that I was angry + I wonder how John did it + I wonder how much more quickly he ran + invite John and whoever else you want to invite + it is easier to ignore the problem than it is to solve it + many who initially supported Thomas later changed their minds + neither Mary nor Louise are coming to the party + she interviewed more programmers than were hired + telling Joe that Sue was coming to the party would create a real problem + the man with whom I play tennis is here + there is a dog in the park + this is not the man we know and love + we like to eat at restaurants , usually on weekends + what did John say he thought you should do + about 2 million people attended + the five best costumes got prizes +No errors! +Exiting @ tick 722234364000 because target called exit() diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt new file mode 100644 index 000000000..f9d747bd5 --- /dev/null +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt @@ -0,0 +1,280 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.722234 # Number of seconds simulated +sim_ticks 722234364000 # Number of ticks simulated +final_tick 722234364000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 1518630 # Simulator instruction rate (inst/s) +host_tick_rate 1927485562 # Simulator tick rate (ticks/s) +host_mem_usage 222536 # Number of bytes of host memory used +host_seconds 374.70 # Real time elapsed on the host +sim_insts 569034848 # Number of instructions simulated +system.physmem.bytes_read 14797056 # Number of bytes read from this memory +system.physmem.bytes_inst_read 188608 # Number of instructions bytes read from this memory +system.physmem.bytes_written 11027328 # Number of bytes written to this memory +system.physmem.num_reads 231204 # Number of read requests responded to by this memory +system.physmem.num_writes 172302 # Number of write requests responded to by this memory +system.physmem.num_other 0 # Number of other requests responded to by this memory +system.physmem.bw_read 20487887 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 261145 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 15268351 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 35756238 # Total bandwidth to/from this memory (bytes/s) +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 548 # Number of system calls +system.cpu.numCycles 1444468728 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.num_insts 569034848 # Number of instructions executed +system.cpu.num_int_alu_accesses 470727703 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses +system.cpu.num_func_calls 15725605 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 95872736 # number of instructions that are conditional controls +system.cpu.num_int_insts 470727703 # number of integer instructions +system.cpu.num_fp_insts 16 # number of float instructions +system.cpu.num_int_register_reads 2844375220 # number of times the integer registers were read +system.cpu.num_int_register_writes 646169365 # number of times the integer registers were written +system.cpu.num_fp_register_reads 16 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_mem_refs 182890035 # number of memory refs +system.cpu.num_load_insts 126029556 # Number of load instructions +system.cpu.num_store_insts 56860479 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 1444468728 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.icache.replacements 9788 # number of replacements +system.cpu.icache.tagsinuse 984.426148 # Cycle average of tags in use +system.cpu.icache.total_refs 516599864 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 11521 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 44839.845847 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 984.426148 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.480677 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 516599864 # number of ReadReq hits +system.cpu.icache.demand_hits 516599864 # number of demand (read+write) hits +system.cpu.icache.overall_hits 516599864 # number of overall hits +system.cpu.icache.ReadReq_misses 11521 # number of ReadReq misses +system.cpu.icache.demand_misses 11521 # number of demand (read+write) misses +system.cpu.icache.overall_misses 11521 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 285068000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 285068000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 285068000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 516611385 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 516611385 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 516611385 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.000022 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.000022 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000022 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 24743.338252 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 24743.338252 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 24743.338252 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 11521 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 11521 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 11521 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.ReadReq_mshr_miss_latency 250505000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 250505000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 250505000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000022 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.000022 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.000022 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 21743.338252 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 21743.338252 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 21743.338252 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 1134822 # number of replacements +system.cpu.dcache.tagsinuse 4065.490059 # Cycle average of tags in use +system.cpu.dcache.total_refs 179817787 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1138918 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 157.884753 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 11889987000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4065.490059 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.992551 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 122957659 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 53883046 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits 1488541 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits 1488541 # number of StoreCondReq hits +system.cpu.dcache.demand_hits 176840705 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 176840705 # number of overall hits +system.cpu.dcache.ReadReq_misses 782658 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 356260 # number of WriteReq misses +system.cpu.dcache.demand_misses 1138918 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 1138918 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 15502704000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 10028942000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 25531646000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 25531646000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 123740317 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses 54239306 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses 1488541 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses 1488541 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 177979623 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 177979623 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.006325 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.006568 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate 0.006399 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.006399 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 19807.762778 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 28150.625947 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 22417.457622 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 22417.457622 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks 1025440 # number of writebacks +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 782658 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 356260 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 1138918 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 1138918 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency 13154730000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 8960162000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 22114892000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 22114892000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.006325 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.006568 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.006399 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.006399 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 16807.762778 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 25150.625947 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 19417.457622 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 19417.457622 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.replacements 212089 # number of replacements +system.cpu.l2cache.tagsinuse 20443.163614 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1426644 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 232128 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 6.145937 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 513135223000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::0 5849.157602 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 14594.006011 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.178502 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.445374 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 683006 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 1025440 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits 236229 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 919235 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 919235 # number of overall hits +system.cpu.l2cache.ReadReq_misses 111173 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 120031 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 231204 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 231204 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 5780996000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 6241612000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 12022608000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 12022608000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 794179 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 1025440 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 356260 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 1150439 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 1150439 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.139985 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.336920 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.200970 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.200970 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.writebacks 172302 # number of writebacks +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses 111173 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 120031 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 231204 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 231204 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 4446920000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 4801240000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 9248160000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 9248160000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.139985 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.336920 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.200970 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.200970 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate + +---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini new file mode 100644 index 000000000..9cc27361f --- /dev/null +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini @@ -0,0 +1,535 @@ +[root] +type=Root +children=system +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +memories=system.physmem +num_work_ids=16 +physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.port[0] + +[system.cpu] +type=DerivO3CPU +children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload +BTBEntries=4096 +BTBTagSize=16 +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +RASSize=16 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +cachePorts=200 +checker=Null +choiceCtrBits=2 +choicePredictorSize=8192 +clock=500 +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +defer_registration=false +dispatchWidth=8 +do_checkpoint_insts=true +do_statistics_insts=true +dtb=system.cpu.dtb +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +globalCtrBits=2 +globalHistoryBits=13 +globalPredictorSize=8192 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +instShiftAmt=2 +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +localCtrBits=2 +localHistoryBits=11 +localHistoryTableSize=2048 +localPredictorSize=2048 +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numIQEntries=64 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +phase=0 +predType=tournament +progress_interval=0 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +squashWidth=8 +store_set_clear_period=250000 +system=system +tracer=system.cpu.tracer +trapLatency=13 +wbDepth=1 +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=10 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=262144 +subblock_size=0 +tgts_per_mshr=20 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.port[1] + +[system.cpu.dtb] +type=X86TLB +size=64 + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 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+opLat=2 + +[system.cpu.fuPool.FUList3] +type=FUDesc +children=opList0 opList1 opList2 +count=2 +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 + +[system.cpu.fuPool.FUList3.opList0] +type=OpDesc +issueLat=1 +opClass=FloatMult +opLat=4 + +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +issueLat=12 +opClass=FloatDiv +opLat=12 + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +issueLat=24 +opClass=FloatSqrt +opLat=24 + +[system.cpu.fuPool.FUList4] +type=FUDesc +children=opList +count=0 +opList=system.cpu.fuPool.FUList4.opList + +[system.cpu.fuPool.FUList4.opList] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu.fuPool.FUList5] +type=FUDesc +children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 +count=4 +opList=system.cpu.fuPool.FUList5.opList00 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+issueLat=1 +opClass=SimdCmp +opLat=1 + +[system.cpu.fuPool.FUList5.opList04] +type=OpDesc +issueLat=1 +opClass=SimdCvt +opLat=1 + +[system.cpu.fuPool.FUList5.opList05] +type=OpDesc +issueLat=1 +opClass=SimdMisc +opLat=1 + +[system.cpu.fuPool.FUList5.opList06] +type=OpDesc +issueLat=1 +opClass=SimdMult +opLat=1 + +[system.cpu.fuPool.FUList5.opList07] +type=OpDesc +issueLat=1 +opClass=SimdMultAcc +opLat=1 + +[system.cpu.fuPool.FUList5.opList08] +type=OpDesc +issueLat=1 +opClass=SimdShift +opLat=1 + +[system.cpu.fuPool.FUList5.opList09] +type=OpDesc +issueLat=1 +opClass=SimdShiftAcc +opLat=1 + +[system.cpu.fuPool.FUList5.opList10] +type=OpDesc +issueLat=1 +opClass=SimdSqrt +opLat=1 + +[system.cpu.fuPool.FUList5.opList11] +type=OpDesc +issueLat=1 +opClass=SimdFloatAdd +opLat=1 + +[system.cpu.fuPool.FUList5.opList12] +type=OpDesc +issueLat=1 +opClass=SimdFloatAlu +opLat=1 + +[system.cpu.fuPool.FUList5.opList13] +type=OpDesc +issueLat=1 +opClass=SimdFloatCmp +opLat=1 + +[system.cpu.fuPool.FUList5.opList14] +type=OpDesc +issueLat=1 +opClass=SimdFloatCvt +opLat=1 + +[system.cpu.fuPool.FUList5.opList15] +type=OpDesc +issueLat=1 +opClass=SimdFloatDiv +opLat=1 + +[system.cpu.fuPool.FUList5.opList16] +type=OpDesc +issueLat=1 +opClass=SimdFloatMisc +opLat=1 + +[system.cpu.fuPool.FUList5.opList17] +type=OpDesc +issueLat=1 +opClass=SimdFloatMult +opLat=1 + +[system.cpu.fuPool.FUList5.opList18] +type=OpDesc +issueLat=1 +opClass=SimdFloatMultAcc +opLat=1 + +[system.cpu.fuPool.FUList5.opList19] +type=OpDesc +issueLat=1 +opClass=SimdFloatSqrt +opLat=1 + +[system.cpu.fuPool.FUList6] +type=FUDesc +children=opList +count=0 +opList=system.cpu.fuPool.FUList6.opList + +[system.cpu.fuPool.FUList6.opList] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu.fuPool.FUList7] +type=FUDesc +children=opList0 opList1 +count=4 +opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 + +[system.cpu.fuPool.FUList7.opList0] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu.fuPool.FUList7.opList1] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu.fuPool.FUList8] +type=FUDesc +children=opList +count=1 +opList=system.cpu.fuPool.FUList8.opList + +[system.cpu.fuPool.FUList8.opList] +type=OpDesc +issueLat=3 +opClass=IprAccess +opLat=3 + +[system.cpu.icache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=10 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=131072 +subblock_size=0 +tgts_per_mshr=20 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.port[0] + +[system.cpu.itb] +type=X86TLB +size=64 + +[system.cpu.l2cache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=false +latency=1000 +max_miss_count=0 +mshrs=10 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=2097152 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.port[2] +mem_side=system.membus.port[2] + +[system.cpu.toL2Bus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +use_default_range=false +width=64 +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side + +[system.cpu.tracer] +type=ExeTracer + +[system.cpu.workload] +type=LiveProcess +cmd=parser 2.1.dict -batch +cwd=build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing +egid=100 +env= +errout=cerr +euid=100 +executable=/dist/m5/cpu2000/binaries/x86/linux/parser +gid=100 +input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=114600000000 +system=system +uid=100 + +[system.membus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +use_default_range=false +width=64 +port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side + +[system.physmem] +type=PhysicalMemory +file= +latency=30000 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.membus.port[1] + diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simerr b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simerr new file mode 100755 index 000000000..ac4ad20a5 --- /dev/null +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simerr @@ -0,0 +1,4 @@ +warn: Sockets disabled, not accepting gdb connections +warn: instruction 'fnstcw_Mw' unimplemented +warn: instruction 'fldcw_Mw' unimplemented +hack: be nice to actually delete the event here diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout new file mode 100755 index 000000000..de72d963a --- /dev/null +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout @@ -0,0 +1,82 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Jan 23 2012 04:08:34 +gem5 started Jan 23 2012 06:58:28 +gem5 executing on zizzer +command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... + + Reading the dictionary files: ***********************info: Increasing stack size by one page. +************************** + 58924 words stored in 3784810 bytes + + +Welcome to the Link Parser -- Version 2.1 + + Copyright (C) 1991-1995 Daniel Sleator and Davy Temperley + +Processing sentences in batch mode + +Echoing of input sentence turned on. +* as had expected the party to be a success , it was a success +info: Increasing stack size by one page. +* do you know where John 's +* he said that , finding that it was impossible to get work as a waiter , he would work as a janitor +info: Increasing stack size by one page. +* how fast the program is it +* I am wondering whether to invite to the party +* I gave him for his birthday it +* I thought terrible after our discussion +* I wonder how much money have you earned +* Janet who is an expert on dogs helped me choose one +* she interviewed more programmers than was hired +* such flowers are found chiefly particularly in Europe +* the dogs some of which were very large ran after the man +* the man whom I play tennis is here +* there is going to be an important meeting January +* to pretend that our program is usable in its current form would be happy +* we're thinking about going to a movie this theater +* which dog you said you chased +- also invited to the meeting were several prominent scientists +- he ran home so quickly that his mother could hardly believe he had called from school +- so many people attended that they spilled over into several neighboring fields +- voting in favor of the bill were 36 Republicans and 4 moderate Democrats +: Grace may not be possible to fix the problem + any program as good as ours should be useful + biochemically , I think the experiment has a lot of problems + Fred has had five years of experience as a programmer + he is looking for another job + how did John do it + how many more people do you think will come + how much more spilled + I have more money than John has time + I made it clear that I was angry + I wonder how John did it + I wonder how much more quickly he ran + invite John and whoever else you want to invite + it is easier to ignore the problem than it is to solve it + many who initially supported Thomas later changed their minds + neither Mary nor Louise are coming to the party + she interviewed more programmers than were hired + telling Joe that Sue was coming to the party would create a real problem + the man with whom I play tennis is here + there is a dog in the park + this is not the man we know and love +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. + we like to eat at restaurants , usually on weekends + what did John say he thought you should do + about 2 million people attended + the five best costumes got prizes +No errors! +Exiting @ tick 493912286000 because target called exit() diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt new file mode 100644 index 000000000..92ece0bed --- /dev/null +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -0,0 +1,491 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.493912 # Number of seconds simulated +sim_ticks 493912286000 # Number of ticks simulated +final_tick 493912286000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 145271 # Simulator instruction rate (inst/s) +host_tick_rate 46927205 # Simulator tick rate (ticks/s) +host_mem_usage 251468 # Number of bytes of host memory used +host_seconds 10525.07 # Real time elapsed on the host +sim_insts 1528988756 # Number of instructions simulated +system.physmem.bytes_read 37487424 # Number of bytes read from this memory +system.physmem.bytes_inst_read 347584 # Number of instructions bytes read from this memory +system.physmem.bytes_written 26320960 # Number of bytes written to this memory +system.physmem.num_reads 585741 # Number of read requests responded to by this memory +system.physmem.num_writes 411265 # Number of write requests responded to by this memory +system.physmem.num_other 0 # Number of other requests responded to by this memory +system.physmem.bw_read 75898950 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 703736 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 53290758 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 129189708 # Total bandwidth to/from this memory (bytes/s) +system.cpu.workload.num_syscalls 551 # Number of system calls +system.cpu.numCycles 987824573 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.BPredUnit.lookups 245766486 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 245766486 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 16576996 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 236474058 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 218464201 # Number of BTB hits +system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 205503020 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1343384866 # Number of instructions fetch has processed +system.cpu.fetch.Branches 245766486 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 218464201 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 436676837 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 119986236 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 218554807 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 32387 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 341323 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 194710374 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 4099618 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 964252463 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.599701 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.317490 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 531629837 55.13% 55.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 32377332 3.36% 58.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 38827894 4.03% 62.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 32536894 3.37% 65.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 21844251 2.27% 68.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 36448993 3.78% 71.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 49128972 5.10% 77.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 36937786 3.83% 80.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 184520504 19.14% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 964252463 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.248796 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.359943 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 264509435 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 174554141 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 373011587 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 49033211 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 103144089 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2445932072 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 103144089 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 301738657 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 40282868 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 12225 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 383467875 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 135606749 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2393375507 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 2559 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 25131978 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 92224846 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 8 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2227188673 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5629907069 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 5629667957 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 239112 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1427299027 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 799889646 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1309 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1288 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 318947403 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 577879232 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 226530900 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 227222440 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 65937432 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2286709085 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 12489 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1922370305 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1306641 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 755226802 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1190125426 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 11936 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 964252463 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.993638 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.811521 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 282911384 29.34% 29.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 160280603 16.62% 45.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 162550496 16.86% 62.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 148847741 15.44% 78.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 109081156 11.31% 89.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 60080329 6.23% 95.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 30822605 3.20% 99.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 8641604 0.90% 99.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1036545 0.11% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 964252463 # Number of insts issued each cycle +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2246339 14.60% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 14.60% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 10026447 65.19% 79.79% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3108042 20.21% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.FU_type_0::No_OpClass 2420122 0.13% 0.13% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1274712167 66.31% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 5 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 463703127 24.12% 90.56% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 181534884 9.44% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 1922370305 # Type of FU issued +system.cpu.iq.rate 1.946064 # Inst issue rate +system.cpu.iq.fu_busy_cnt 15380828 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.008001 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4825675637 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3042139517 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1874661917 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 4905 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 81824 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 136 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1935329448 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1563 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 158391521 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.squashedLoads 193777072 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 372742 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 283642 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 77371112 # Number of stores squashed +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.rescheduledLoads 2379 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 25 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewSquashCycles 103144089 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 9045659 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1404502 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2286721574 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1118432 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 577879232 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 226531297 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 6081 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1006586 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 29974 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 283642 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 15693422 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 2344063 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 18037485 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1889150749 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 454748002 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 33219556 # Number of squashed instructions skipped in execute +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.exec_nop 0 # number of nop insts executed +system.cpu.iew.exec_refs 629271939 # number of memory reference insts executed +system.cpu.iew.exec_branches 176719729 # Number of branches executed +system.cpu.iew.exec_stores 174523937 # Number of stores executed +system.cpu.iew.exec_rate 1.912435 # Inst execution rate +system.cpu.iew.wb_sent 1882531239 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1874662053 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1440606287 # num instructions producing a value +system.cpu.iew.wb_consumers 2134778201 # num instructions consuming a value +system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.wb_rate 1.897768 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.674827 # average fanout of values written-back +system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.commit.commitCommittedInsts 1528988756 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 757743569 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 553 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 16604349 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 861108374 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.775605 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.288022 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 338327816 39.29% 39.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 210551706 24.45% 63.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 75360819 8.75% 72.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 92562974 10.75% 83.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 34054041 3.95% 87.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 27955182 3.25% 90.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 16032820 1.86% 92.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 12266632 1.42% 93.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 53996384 6.27% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 861108374 # Number of insts commited each cycle +system.cpu.commit.count 1528988756 # Number of instructions committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.refs 533262345 # Number of memory references committed +system.cpu.commit.loads 384102160 # Number of loads committed +system.cpu.commit.membars 0 # Number of memory barriers committed +system.cpu.commit.branches 149758588 # Number of branches committed +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.int_insts 1528317614 # Number of committed integer instructions. +system.cpu.commit.function_calls 0 # Number of function calls committed. +system.cpu.commit.bw_lim_events 53996384 # number cycles where commit BW limit reached +system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits +system.cpu.rob.rob_reads 3093844315 # The number of ROB reads +system.cpu.rob.rob_writes 4676786954 # The number of ROB writes +system.cpu.timesIdled 606516 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 23572110 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 1528988756 # Number of Instructions Simulated +system.cpu.committedInsts_total 1528988756 # Number of Instructions Simulated +system.cpu.cpi 0.646064 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.646064 # CPI: Total CPI of All Threads +system.cpu.ipc 1.547834 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.547834 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3179044858 # number of integer regfile reads +system.cpu.int_regfile_writes 1744829680 # number of integer regfile writes +system.cpu.fp_regfile_reads 145 # number of floating regfile reads +system.cpu.fp_regfile_writes 5 # number of floating regfile writes +system.cpu.misc_regfile_reads 1039286160 # number of misc regfile reads +system.cpu.icache.replacements 10045 # number of replacements +system.cpu.icache.tagsinuse 976.337758 # Cycle average of tags in use +system.cpu.icache.total_refs 194480398 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 11548 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 16841.045895 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 976.337758 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.476727 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 194486608 # number of ReadReq hits +system.cpu.icache.demand_hits 194486608 # number of demand (read+write) hits +system.cpu.icache.overall_hits 194486608 # number of overall hits +system.cpu.icache.ReadReq_misses 223766 # number of ReadReq misses +system.cpu.icache.demand_misses 223766 # number of demand (read+write) misses +system.cpu.icache.overall_misses 223766 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 1539723000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 1539723000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 1539723000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 194710374 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 194710374 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 194710374 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.001149 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.001149 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.001149 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 6880.951530 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 6880.951530 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 6880.951530 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks 6 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits 2071 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 2071 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 2071 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 221695 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 221695 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 221695 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.ReadReq_mshr_miss_latency 824417000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 824417000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 824417000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.001139 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.001139 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.001139 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 3718.699114 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 3718.699114 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 3718.699114 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 2527930 # number of replacements +system.cpu.dcache.tagsinuse 4087.566272 # Cycle average of tags in use +system.cpu.dcache.total_refs 440586260 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2532026 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 174.005425 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 2135798000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4087.566272 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.997941 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 291836002 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 147579227 # number of WriteReq hits +system.cpu.dcache.demand_hits 439415229 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 439415229 # number of overall hits +system.cpu.dcache.ReadReq_misses 3119681 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 1580974 # number of WriteReq misses +system.cpu.dcache.demand_misses 4700655 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 4700655 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 52079313500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 37355392500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 89434706000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 89434706000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 294955683 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses 149160201 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 444115884 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 444115884 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.010577 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.010599 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate 0.010584 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.010584 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 16693.794494 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 23628.087812 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 19026.009354 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 19026.009354 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 29000 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 14500 # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks 2229595 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 1359154 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 607660 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 1966814 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 1966814 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 1760527 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 973314 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 2733841 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 2733841 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency 14908482500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 17169522000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 32078004500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 32078004500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.005969 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.006525 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.006156 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.006156 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8468.193047 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 17640.270252 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 11733.675989 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 11733.675989 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.replacements 574945 # number of replacements +system.cpu.l2cache.tagsinuse 21597.257673 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3194359 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 594122 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 5.376604 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 271429089000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::0 7797.131828 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 13800.125845 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.237950 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.421146 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 1433279 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 2229601 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits 1240 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits 524400 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 1957679 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 1957679 # number of overall hits +system.cpu.l2cache.ReadReq_misses 338611 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses 208876 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses 247152 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 585763 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 585763 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 11564612500 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency 9756500 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 8478074500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 20042687000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 20042687000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 1771890 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 2229601 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses 210116 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 771552 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 2543442 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 2543442 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.191102 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate 0.994098 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.320331 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.230303 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.230303 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34153.091601 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency 46.709531 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34303.078672 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34216.375906 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34216.375906 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.writebacks 411265 # number of writebacks +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses 338611 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses 208876 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 247152 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 585763 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 585763 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 10503665500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 6475353000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 7666739500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 18170405000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 18170405000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.191102 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.994098 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.320331 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.230303 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.230303 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31019.859071 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000.943143 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31020.341733 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31020.062722 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31020.062722 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate + +---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini new file mode 100644 index 000000000..b1057156b --- /dev/null +++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini @@ -0,0 +1,102 @@ +[root] +type=Root +children=system +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +memories=system.physmem +num_work_ids=16 +physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.port[0] + +[system.cpu] +type=AtomicSimpleCPU +children=dtb itb tracer workload +checker=Null +clock=500 +cpu_id=0 +defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true +dtb=system.cpu.dtb +function_trace=false +function_trace_start=0 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +progress_interval=0 +simulate_data_stalls=false +simulate_inst_stalls=false +system=system +tracer=system.cpu.tracer +width=1 +workload=system.cpu.workload +dcache_port=system.membus.port[3] +icache_port=system.membus.port[2] + +[system.cpu.dtb] +type=X86TLB +size=64 + +[system.cpu.itb] +type=X86TLB +size=64 + +[system.cpu.tracer] +type=ExeTracer + +[system.cpu.workload] +type=LiveProcess +cmd=parser 2.1.dict -batch +cwd=build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-atomic +egid=100 +env= +errout=cerr +euid=100 +executable=/dist/m5/cpu2000/binaries/x86/linux/parser +gid=100 +input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=114600000000 +system=system +uid=100 + +[system.membus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +use_default_range=false +width=64 +port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port + +[system.physmem] +type=PhysicalMemory +file= +latency=30000 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.membus.port[1] + diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simerr b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simerr new file mode 100755 index 000000000..ac4ad20a5 --- /dev/null +++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simerr @@ -0,0 +1,4 @@ +warn: Sockets disabled, not accepting gdb connections +warn: instruction 'fnstcw_Mw' unimplemented +warn: instruction 'fldcw_Mw' unimplemented +hack: be nice to actually delete the event here diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout new file mode 100755 index 000000000..b86175ab2 --- /dev/null +++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout @@ -0,0 +1,72 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Jan 23 2012 04:08:34 +gem5 started Jan 23 2012 06:59:28 +gem5 executing on zizzer +command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-atomic +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... + + Reading the dictionary files: *****************************info: Increasing stack size by one page. +******************** + 58924 words stored in 3784810 bytes + + +Welcome to the Link Parser -- Version 2.1 + + Copyright (C) 1991-1995 Daniel Sleator and Davy Temperley + +Processing sentences in batch mode + +Echoing of input sentence turned on. +* as had expected the party to be a success , it was a success +* do you know where John 's +* he said that , finding that it was impossible to get work as a waiter , he would work as a janitor +info: Increasing stack size by one page. +info: Increasing stack size by one page. +* how fast the program is it +* I am wondering whether to invite to the party +* I gave him for his birthday it +* I thought terrible after our discussion +* I wonder how much money have you earned +* Janet who is an expert on dogs helped me choose one +* she interviewed more programmers than was hired +* such flowers are found chiefly particularly in Europe +* the dogs some of which were very large ran after the man +* the man whom I play tennis is here +* there is going to be an important meeting January +* to pretend that our program is usable in its current form would be happy +* we're thinking about going to a movie this theater +* which dog you said you chased +- also invited to the meeting were several prominent scientists +- he ran home so quickly that his mother could hardly believe he had called from school +- so many people attended that they spilled over into several neighboring fields +- voting in favor of the bill were 36 Republicans and 4 moderate Democrats +: Grace may not be possible to fix the problem + any program as good as ours should be useful + biochemically , I think the experiment has a lot of problems + Fred has had five years of experience as a programmer + he is looking for another job + how did John do it + how many more people do you think will come + how much more spilled + I have more money than John has time + I made it clear that I was angry + I wonder how John did it + I wonder how much more quickly he ran + invite John and whoever else you want to invite + it is easier to ignore the problem than it is to solve it + many who initially supported Thomas later changed their minds + neither Mary nor Louise are coming to the party + she interviewed more programmers than were hired + telling Joe that Sue was coming to the party would create a real problem + the man with whom I play tennis is here + there is a dog in the park + this is not the man we know and love + we like to eat at restaurants , usually on weekends + what did John say he thought you should do + about 2 million people attended + the five best costumes got prizes +No errors! +Exiting @ tick 885229360000 because target called exit() diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt new file mode 100644 index 000000000..4e0a10e13 --- /dev/null +++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt @@ -0,0 +1,45 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.885229 # Number of seconds simulated +sim_ticks 885229360000 # Number of ticks simulated +final_tick 885229360000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 2258239 # Simulator instruction rate (inst/s) +host_tick_rate 1307438877 # Simulator tick rate (ticks/s) +host_mem_usage 208528 # Number of bytes of host memory used +host_seconds 677.07 # Real time elapsed on the host +sim_insts 1528988757 # Number of instructions simulated +system.physmem.bytes_read 10832432532 # Number of bytes read from this memory +system.physmem.bytes_inst_read 8546776872 # Number of instructions bytes read from this memory +system.physmem.bytes_written 991849460 # Number of bytes written to this memory +system.physmem.num_reads 1452449298 # Number of read requests responded to by this memory +system.physmem.num_writes 149160201 # Number of write requests responded to by this memory +system.physmem.num_other 0 # Number of other requests responded to by this memory +system.physmem.bw_read 12236865406 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 9654872803 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 1120443475 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 13357308881 # Total bandwidth to/from this memory (bytes/s) +system.cpu.workload.num_syscalls 551 # Number of system calls +system.cpu.numCycles 1770458721 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.num_insts 1528988757 # Number of instructions executed +system.cpu.num_int_alu_accesses 1528317615 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 92658800 # number of instructions that are conditional controls +system.cpu.num_int_insts 1528317615 # number of integer instructions +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_int_register_reads 3581460239 # number of times the integer registers were read +system.cpu.num_int_register_writes 1427299027 # number of times the integer registers were written +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_mem_refs 533262345 # number of memory refs +system.cpu.num_load_insts 384102160 # Number of load instructions +system.cpu.num_store_insts 149160185 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 1770458721 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles + +---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini b/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini new file mode 100644 index 000000000..c570a48d2 --- /dev/null +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini @@ -0,0 +1,205 @@ +[root] +type=Root +children=system +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +memories=system.physmem +num_work_ids=16 +physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.port[0] + +[system.cpu] +type=TimingSimpleCPU +children=dcache dtb icache itb l2cache toL2Bus tracer workload +checker=Null +clock=500 +cpu_id=0 +defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true +dtb=system.cpu.dtb +function_trace=false +function_trace_start=0 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +progress_interval=0 +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=10 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=262144 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.port[1] + +[system.cpu.dtb] +type=X86TLB +size=64 + +[system.cpu.icache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=10 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=131072 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.port[0] + +[system.cpu.itb] +type=X86TLB +size=64 + +[system.cpu.l2cache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=false +latency=10000 +max_miss_count=0 +mshrs=10 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=100000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=2097152 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.port[2] +mem_side=system.membus.port[2] + +[system.cpu.toL2Bus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +use_default_range=false +width=64 +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side + +[system.cpu.tracer] +type=ExeTracer + +[system.cpu.workload] +type=LiveProcess +cmd=parser 2.1.dict -batch +cwd=build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing +egid=100 +env= +errout=cerr +euid=100 +executable=/dist/m5/cpu2000/binaries/x86/linux/parser +gid=100 +input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=114600000000 +system=system +uid=100 + +[system.membus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +use_default_range=false +width=64 +port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side + +[system.physmem] +type=PhysicalMemory +file= +latency=30000 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.membus.port[1] + diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simerr b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simerr new file mode 100755 index 000000000..ac4ad20a5 --- /dev/null +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simerr @@ -0,0 +1,4 @@ +warn: Sockets disabled, not accepting gdb connections +warn: instruction 'fnstcw_Mw' unimplemented +warn: instruction 'fldcw_Mw' unimplemented +hack: be nice to actually delete the event here diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout new file mode 100755 index 000000000..a297c4bc8 --- /dev/null +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout @@ -0,0 +1,72 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Jan 23 2012 04:08:34 +gem5 started Jan 23 2012 07:10:56 +gem5 executing on zizzer +command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... + + Reading the dictionary files: *****************************info: Increasing stack size by one page. +******************** + 58924 words stored in 3784810 bytes + + +Welcome to the Link Parser -- Version 2.1 + + Copyright (C) 1991-1995 Daniel Sleator and Davy Temperley + +Processing sentences in batch mode + +Echoing of input sentence turned on. +* as had expected the party to be a success , it was a success +* do you know where John 's +* he said that , finding that it was impossible to get work as a waiter , he would work as a janitor +info: Increasing stack size by one page. +info: Increasing stack size by one page. +* how fast the program is it +* I am wondering whether to invite to the party +* I gave him for his birthday it +* I thought terrible after our discussion +* I wonder how much money have you earned +* Janet who is an expert on dogs helped me choose one +* she interviewed more programmers than was hired +* such flowers are found chiefly particularly in Europe +* the dogs some of which were very large ran after the man +* the man whom I play tennis is here +* there is going to be an important meeting January +* to pretend that our program is usable in its current form would be happy +* we're thinking about going to a movie this theater +* which dog you said you chased +- also invited to the meeting were several prominent scientists +- he ran home so quickly that his mother could hardly believe he had called from school +- so many people attended that they spilled over into several neighboring fields +- voting in favor of the bill were 36 Republicans and 4 moderate Democrats +: Grace may not be possible to fix the problem + any program as good as ours should be useful + biochemically , I think the experiment has a lot of problems + Fred has had five years of experience as a programmer + he is looking for another job + how did John do it + how many more people do you think will come + how much more spilled + I have more money than John has time + I made it clear that I was angry + I wonder how John did it + I wonder how much more quickly he ran + invite John and whoever else you want to invite + it is easier to ignore the problem than it is to solve it + many who initially supported Thomas later changed their minds + neither Mary nor Louise are coming to the party + she interviewed more programmers than were hired + telling Joe that Sue was coming to the party would create a real problem + the man with whom I play tennis is here + there is a dog in the park + this is not the man we know and love + we like to eat at restaurants , usually on weekends + what did John say he thought you should do + about 2 million people attended + the five best costumes got prizes +No errors! +Exiting @ tick 1658729604000 because target called exit() diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt new file mode 100644 index 000000000..28d09902a --- /dev/null +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt @@ -0,0 +1,234 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 1.658730 # Number of seconds simulated +sim_ticks 1658729604000 # Number of ticks simulated +final_tick 1658729604000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 1326745 # Simulator instruction rate (inst/s) +host_tick_rate 1439324936 # Simulator tick rate (ticks/s) +host_mem_usage 217512 # Number of bytes of host memory used +host_seconds 1152.44 # Real time elapsed on the host +sim_insts 1528988757 # Number of instructions simulated +system.physmem.bytes_read 37094976 # Number of bytes read from this memory +system.physmem.bytes_inst_read 148544 # Number of instructions bytes read from this memory +system.physmem.bytes_written 26349376 # Number of bytes written to this memory +system.physmem.num_reads 579609 # Number of read requests responded to by this memory +system.physmem.num_writes 411709 # Number of write requests responded to by this memory +system.physmem.num_other 0 # Number of other requests responded to by this memory +system.physmem.bw_read 22363486 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 89553 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 15885275 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 38248761 # Total bandwidth to/from this memory (bytes/s) +system.cpu.workload.num_syscalls 551 # Number of system calls +system.cpu.numCycles 3317459208 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.num_insts 1528988757 # Number of instructions executed +system.cpu.num_int_alu_accesses 1528317615 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 92658800 # 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number of ReadExReq misses +system.cpu.l2cache.demand_misses 579609 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 579609 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 17241952000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 12897722000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 30139674000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 30139674000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 1730228 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 2223170 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 791044 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 2521272 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 2521272 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.191637 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.313551 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.229888 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.229888 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000.024190 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 52000.010352 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 52000.010352 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.writebacks 411709 # number of writebacks +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses 331576 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 248033 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 579609 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 579609 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 13263040000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 9921320000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 23184360000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 23184360000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.191637 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.313551 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.229888 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.229888 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate + +---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/test.py b/tests/long/se/20.parser/test.py new file mode 100644 index 000000000..c96a46e60 --- /dev/null +++ b/tests/long/se/20.parser/test.py @@ -0,0 +1,33 @@ +# Copyright (c) 2006-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Korey Sewell + +m5.util.addToPath('../configs/common') +from cpu2000 import parser + +workload = parser(isa, opsys, 'mdred') +root.system.cpu.workload = workload.makeLiveProcess() |