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-rw-r--r--tests/long/se/20.parser/ref/alpha/tru64/minor-timing/config.ini6
-rwxr-xr-x[-rw-r--r--]tests/long/se/20.parser/ref/alpha/tru64/minor-timing/simerr6
-rwxr-xr-x[-rw-r--r--]tests/long/se/20.parser/ref/alpha/tru64/minor-timing/simout11
-rw-r--r--tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt1112
-rw-r--r--tests/long/se/20.parser/ref/arm/linux/minor-timing/config.ini10
-rwxr-xr-xtests/long/se/20.parser/ref/arm/linux/minor-timing/simout14
-rw-r--r--tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt1177
-rw-r--r--tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini10
-rw-r--r--tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini6
-rw-r--r--tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini10
-rwxr-xr-xtests/long/se/20.parser/ref/x86/linux/o3-timing/simout22
-rw-r--r--tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt1698
-rw-r--r--tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini6
13 files changed, 2052 insertions, 2036 deletions
diff --git a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/config.ini b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/config.ini
index 9aa92cf18..9e17532ff 100644
--- a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/config.ini
+++ b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/config.ini
@@ -125,7 +125,7 @@ localPredictorSize=2048
numThreads=1
[system.cpu.dcache]
-type=BaseCache
+type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=2
@@ -548,7 +548,7 @@ eventq_index=0
opClass=InstPrefetch
[system.cpu.icache]
-type=BaseCache
+type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=2
@@ -597,7 +597,7 @@ eventq_index=0
size=48
[system.cpu.l2cache]
-type=BaseCache
+type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=8
diff --git a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/simerr b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/simerr
index 354ea5068..f0a9a7c93 100644..100755
--- a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/simerr
+++ b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/simerr
@@ -1,10 +1,6 @@
+warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Sockets disabled, not accepting gdb connections
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
-warn: system.cpu.execute.inFlightInsts: No space to push data into queue of capacity 26, pushing anyway
-warn: system.cpu.execute.inFlightInsts: No space to push data into queue of capacity 26, pushing anyway
-warn: system.cpu.execute.inFlightInsts: No space to push data into queue of capacity 26, pushing anyway
-warn: system.cpu.execute.inFlightInsts: No space to push data into queue of capacity 26, pushing anyway
-warn: system.cpu.execute.inFlightInsts: No space to push data into queue of capacity 26, pushing anyway
warn: ignoring syscall sigprocmask(1, ...)
diff --git a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/simout b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/simout
index 6e5c2e80e..f3df2a37b 100644..100755
--- a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/simout
+++ b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/simout
@@ -3,10 +3,11 @@ Redirecting stderr to build/ALPHA/tests/opt/long/se/20.parser/alpha/tru64/minor-
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled May 7 2014 10:41:53
-gem5 started May 7 2014 16:13:15
-gem5 executing on cz3212c2d7
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/20.parser/alpha/tru64/minor-timing -re tests/run.py build/ALPHA/tests/opt/long/se/20.parser/alpha/tru64/minor-timing
+gem5 compiled Sep 14 2015 20:54:01
+gem5 started Sep 14 2015 21:15:04
+gem5 executing on ribera.cs.wisc.edu
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/20.parser/alpha/tru64/minor-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA/tests/opt/long/se/20.parser/alpha/tru64/minor-timing
+
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
@@ -68,4 +69,4 @@ Echoing of input sentence turned on.
about 2 million people attended
the five best costumes got prizes
No errors!
-Exiting @ tick 409513954500 because target called exit()
+Exiting @ tick 412080064500 because target called exit()
diff --git a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt
index 721b096f0..0819be4e4 100644
--- a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt
@@ -1,95 +1,95 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.412968 # Number of seconds simulated
-sim_ticks 412968287500 # Number of ticks simulated
-final_tick 412968287500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.412080 # Number of seconds simulated
+sim_ticks 412080064500 # Number of ticks simulated
+final_tick 412080064500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 309752 # Simulator instruction rate (inst/s)
-host_op_rate 309752 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 209049423 # Simulator tick rate (ticks/s)
-host_mem_usage 299216 # Number of bytes of host memory used
-host_seconds 1975.46 # Real time elapsed on the host
+host_inst_rate 229857 # Simulator instruction rate (inst/s)
+host_op_rate 229857 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 154795079 # Simulator tick rate (ticks/s)
+host_mem_usage 293864 # Number of bytes of host memory used
+host_seconds 2662.10 # Real time elapsed on the host
sim_insts 611901617 # Number of instructions simulated
sim_ops 611901617 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 171008 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 24125568 # Number of bytes read from this memory
-system.physmem.bytes_read::total 24296576 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 171008 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 171008 # Number of instructions bytes read from this memory
+system.physmem.bytes_read::cpu.inst 170880 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 24123968 # Number of bytes read from this memory
+system.physmem.bytes_read::total 24294848 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 170880 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 170880 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 18781376 # Number of bytes written to this memory
system.physmem.bytes_written::total 18781376 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 2672 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 376962 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 379634 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 2670 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 376937 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 379607 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 293459 # Number of write requests responded to by this memory
system.physmem.num_writes::total 293459 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 414095 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 58419905 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 58833999 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 414095 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 414095 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 45478979 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 45478979 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 45478979 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 414095 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 58419905 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 104312978 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 379634 # Number of read requests accepted
+system.physmem.bw_read::cpu.inst 414677 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 58541944 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 58956621 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 414677 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 414677 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 45577007 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 45577007 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 45577007 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 414677 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 58541944 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 104533628 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 379607 # Number of read requests accepted
system.physmem.writeReqs 293459 # Number of write requests accepted
-system.physmem.readBursts 379634 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts 379607 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 293459 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 24275200 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 21376 # Total number of bytes read from write queue
+system.physmem.bytesReadDRAM 24271744 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 23104 # Total number of bytes read from write queue
system.physmem.bytesWritten 18779968 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 24296576 # Total read bytes from the system interface side
+system.physmem.bytesReadSys 24294848 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 18781376 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 334 # Number of DRAM read bursts serviced by the write queue
+system.physmem.servicedByWrQ 361 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 23720 # Per bank write bursts
-system.physmem.perBankRdBursts::1 23189 # Per bank write bursts
-system.physmem.perBankRdBursts::2 23443 # Per bank write bursts
-system.physmem.perBankRdBursts::3 24493 # Per bank write bursts
-system.physmem.perBankRdBursts::4 25427 # Per bank write bursts
-system.physmem.perBankRdBursts::5 23582 # Per bank write bursts
-system.physmem.perBankRdBursts::6 23638 # Per bank write bursts
-system.physmem.perBankRdBursts::7 23957 # Per bank write bursts
-system.physmem.perBankRdBursts::8 23144 # Per bank write bursts
-system.physmem.perBankRdBursts::9 23961 # Per bank write bursts
-system.physmem.perBankRdBursts::10 24713 # Per bank write bursts
-system.physmem.perBankRdBursts::11 22767 # Per bank write bursts
-system.physmem.perBankRdBursts::12 23721 # Per bank write bursts
-system.physmem.perBankRdBursts::13 24378 # Per bank write bursts
-system.physmem.perBankRdBursts::14 22727 # Per bank write bursts
+system.physmem.perBankRdBursts::0 23711 # Per bank write bursts
+system.physmem.perBankRdBursts::1 23184 # Per bank write bursts
+system.physmem.perBankRdBursts::2 23442 # Per bank write bursts
+system.physmem.perBankRdBursts::3 24496 # Per bank write bursts
+system.physmem.perBankRdBursts::4 25435 # Per bank write bursts
+system.physmem.perBankRdBursts::5 23571 # Per bank write bursts
+system.physmem.perBankRdBursts::6 23637 # Per bank write bursts
+system.physmem.perBankRdBursts::7 23952 # Per bank write bursts
+system.physmem.perBankRdBursts::8 23149 # Per bank write bursts
+system.physmem.perBankRdBursts::9 23951 # Per bank write bursts
+system.physmem.perBankRdBursts::10 24706 # Per bank write bursts
+system.physmem.perBankRdBursts::11 22760 # Per bank write bursts
+system.physmem.perBankRdBursts::12 23713 # Per bank write bursts
+system.physmem.perBankRdBursts::13 24379 # Per bank write bursts
+system.physmem.perBankRdBursts::14 22720 # Per bank write bursts
system.physmem.perBankRdBursts::15 22440 # Per bank write bursts
-system.physmem.perBankWrBursts::0 17784 # Per bank write bursts
-system.physmem.perBankWrBursts::1 17460 # Per bank write bursts
-system.physmem.perBankWrBursts::2 17942 # Per bank write bursts
-system.physmem.perBankWrBursts::3 18842 # Per bank write bursts
-system.physmem.perBankWrBursts::4 19508 # Per bank write bursts
-system.physmem.perBankWrBursts::5 18590 # Per bank write bursts
-system.physmem.perBankWrBursts::6 18730 # Per bank write bursts
-system.physmem.perBankWrBursts::7 18662 # Per bank write bursts
-system.physmem.perBankWrBursts::8 18408 # Per bank write bursts
-system.physmem.perBankWrBursts::9 18932 # Per bank write bursts
-system.physmem.perBankWrBursts::10 19251 # Per bank write bursts
-system.physmem.perBankWrBursts::11 18034 # Per bank write bursts
+system.physmem.perBankWrBursts::0 17781 # Per bank write bursts
+system.physmem.perBankWrBursts::1 17456 # Per bank write bursts
+system.physmem.perBankWrBursts::2 17945 # Per bank write bursts
+system.physmem.perBankWrBursts::3 18847 # Per bank write bursts
+system.physmem.perBankWrBursts::4 19513 # Per bank write bursts
+system.physmem.perBankWrBursts::5 18587 # Per bank write bursts
+system.physmem.perBankWrBursts::6 18727 # Per bank write bursts
+system.physmem.perBankWrBursts::7 18653 # Per bank write bursts
+system.physmem.perBankWrBursts::8 18413 # Per bank write bursts
+system.physmem.perBankWrBursts::9 18933 # Per bank write bursts
+system.physmem.perBankWrBursts::10 19255 # Per bank write bursts
+system.physmem.perBankWrBursts::11 18037 # Per bank write bursts
system.physmem.perBankWrBursts::12 18264 # Per bank write bursts
-system.physmem.perBankWrBursts::13 18730 # Per bank write bursts
-system.physmem.perBankWrBursts::14 17177 # Per bank write bursts
-system.physmem.perBankWrBursts::15 17123 # Per bank write bursts
+system.physmem.perBankWrBursts::13 18729 # Per bank write bursts
+system.physmem.perBankWrBursts::14 17175 # Per bank write bursts
+system.physmem.perBankWrBursts::15 17122 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 412968199500 # Total gap between requests
+system.physmem.totGap 412079976500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 379634 # Read request sizes (log2)
+system.physmem.readPktSize::6 379607 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
@@ -97,9 +97,9 @@ system.physmem.writePktSize::3 0 # Wr
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 293459 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 377911 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 1373 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 16 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 377839 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 1392 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 15 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
@@ -144,46 +144,46 @@ system.physmem.wrQLenPdf::11 1 # Wh
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 6948 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 7299 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 17007 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 17386 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 17473 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 17478 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 17451 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 17472 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 17456 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 17464 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 17487 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 17459 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 17522 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 17527 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 17491 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 17667 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 17395 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 17350 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 31 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 16 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 10 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 11 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37 4 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38 3 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39 3 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41 4 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 6883 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 7241 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 17014 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 17383 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 17434 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 17476 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 17467 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 17484 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 17484 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 17482 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 17524 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 17475 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 17543 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 17538 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 17498 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 17632 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 17387 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 17353 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33 39 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34 28 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35 23 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36 17 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37 11 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38 9 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39 8 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40 5 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41 2 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 2 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43 3 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44 2 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45 2 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46 3 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48 2 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50 2 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51 2 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52 3 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53 2 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54 3 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43 2 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
@@ -193,125 +193,129 @@ system.physmem.wrQLenPdf::60 0 # Wh
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 142181 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 302.814019 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 179.682339 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 324.904056 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 50781 35.72% 35.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 38739 27.25% 62.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 13305 9.36% 72.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 8117 5.71% 78.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 5703 4.01% 82.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 3753 2.64% 84.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 3029 2.13% 86.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 2502 1.76% 88.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 16252 11.43% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 142181 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 17324 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 21.893847 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 236.830288 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023 17315 99.95% 99.95% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047 4 0.02% 99.97% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples 142258 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 302.629870 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 179.695929 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 324.359961 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 50814 35.72% 35.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 38804 27.28% 63.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 13098 9.21% 72.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 8314 5.84% 78.05% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 5760 4.05% 82.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 3818 2.68% 84.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 2956 2.08% 86.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 2613 1.84% 88.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 16081 11.30% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 142258 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 17331 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 21.881888 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 237.076982 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023 17323 99.95% 99.95% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047 3 0.02% 99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-3071 2 0.01% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::3072-4095 1 0.01% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::8192-9215 1 0.01% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::28672-29695 1 0.01% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 17324 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 17324 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 16.938178 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 16.866265 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 3.087562 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-23 17274 99.71% 99.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-31 36 0.21% 99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-39 4 0.02% 99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-47 3 0.02% 99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-63 1 0.01% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-79 2 0.01% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-87 1 0.01% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-111 1 0.01% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-159 1 0.01% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::328-335 1 0.01% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 17324 # Writes before turning the bus around for reads
-system.physmem.totQLat 4037980750 # Total ticks spent queuing
-system.physmem.totMemAccLat 11149855750 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 1896500000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 10645.88 # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total 17331 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 17331 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 16.931337 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 16.860812 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 2.636907 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19 17131 98.85% 98.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23 149 0.86% 99.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27 30 0.17% 99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31 5 0.03% 99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35 5 0.03% 99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39 1 0.01% 99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55 1 0.01% 99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59 1 0.01% 99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63 2 0.01% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91 2 0.01% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103 1 0.01% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107 1 0.01% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159 1 0.01% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-227 1 0.01% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 17331 # Writes before turning the bus around for reads
+system.physmem.totQLat 4068932250 # Total ticks spent queuing
+system.physmem.totMemAccLat 11179794750 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 1896230000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 10729.01 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 29395.88 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 58.78 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 45.48 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 58.83 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 45.48 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 29479.01 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 58.90 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 45.57 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 58.96 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 45.58 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 0.81 # Data bus utilization in percentage
+system.physmem.busUtil 0.82 # Data bus utilization in percentage
system.physmem.busUtilRead 0.46 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.36 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 20.84 # Average write queue length when enqueuing
-system.physmem.readRowHits 314187 # Number of row buffer hits during reads
-system.physmem.writeRowHits 216366 # Number of row buffer hits during writes
+system.physmem.avgWrQLen 20.54 # Average write queue length when enqueuing
+system.physmem.readRowHits 314133 # Number of row buffer hits during reads
+system.physmem.writeRowHits 216290 # Number of row buffer hits during writes
system.physmem.readRowHitRate 82.83 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 73.73 # Row buffer hit rate for writes
-system.physmem.avgGap 613538.10 # Average gap between requests
-system.physmem.pageHitRate 78.86 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 547268400 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 298608750 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 1493302200 # Energy for read commands per rank (pJ)
+system.physmem.writeRowHitRate 73.70 # Row buffer hit rate for writes
+system.physmem.avgGap 612243.04 # Average gap between requests
+system.physmem.pageHitRate 78.85 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 548364600 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 299206875 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 1493138400 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 955858320 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 26973005280 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 62129952405 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 193280474250 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 285678469605 # Total energy per rank (pJ)
-system.physmem_0.averagePower 691.770048 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 320991140250 # Time in different power states
-system.physmem_0.memoryStateTime::REF 13789880000 # Time in different power states
+system.physmem_0.refreshEnergy 26915029440 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 62103866355 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 192770777250 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 285086241240 # Total energy per rank (pJ)
+system.physmem_0.averagePower 691.822973 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 320142846250 # Time in different power states
+system.physmem_0.memoryStateTime::REF 13760240000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 78186381000 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 78176682500 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 527582160 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 287867250 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 1465152000 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 945535680 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 26973005280 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 59078125665 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 195957550500 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 285234818535 # Total energy per rank (pJ)
-system.physmem_1.averagePower 690.695650 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 325462585000 # Time in different power states
-system.physmem_1.memoryStateTime::REF 13789880000 # Time in different power states
+system.physmem_1.actEnergy 527105880 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 287607375 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 1464957000 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 945613440 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 26915029440 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 59197387905 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 195320319750 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 284658020790 # Total energy per rank (pJ)
+system.physmem_1.averagePower 690.783804 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 324404039000 # Time in different power states
+system.physmem_1.memoryStateTime::REF 13760240000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 73715009750 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 73915489750 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.cpu.branchPred.lookups 124207922 # Number of BP lookups
-system.cpu.branchPred.condPredicted 87898525 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 6402854 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 71417252 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 67405039 # Number of BTB hits
+system.cpu.branchPred.lookups 123917174 # Number of BP lookups
+system.cpu.branchPred.condPredicted 87658941 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 6214604 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 71577859 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 67272092 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 94.382012 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 15056477 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 1126637 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 93.984499 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 15041850 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 1126019 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 149440392 # DTB read hits
-system.cpu.dtb.read_misses 563754 # DTB read misses
+system.cpu.dtb.read_hits 149344667 # DTB read hits
+system.cpu.dtb.read_misses 549014 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 150004146 # DTB read accesses
-system.cpu.dtb.write_hits 57327101 # DTB write hits
-system.cpu.dtb.write_misses 66835 # DTB write misses
+system.cpu.dtb.read_accesses 149893681 # DTB read accesses
+system.cpu.dtb.write_hits 57319597 # DTB write hits
+system.cpu.dtb.write_misses 63704 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 57393936 # DTB write accesses
-system.cpu.dtb.data_hits 206767493 # DTB hits
-system.cpu.dtb.data_misses 630589 # DTB misses
+system.cpu.dtb.write_accesses 57383301 # DTB write accesses
+system.cpu.dtb.data_hits 206664264 # DTB hits
+system.cpu.dtb.data_misses 612718 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 207398082 # DTB accesses
-system.cpu.itb.fetch_hits 226564860 # ITB hits
+system.cpu.dtb.data_accesses 207276982 # DTB accesses
+system.cpu.itb.fetch_hits 226051197 # ITB hits
system.cpu.itb.fetch_misses 48 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 226564908 # ITB accesses
+system.cpu.itb.fetch_accesses 226051245 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@@ -325,82 +329,82 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 485 # Number of system calls
-system.cpu.numCycles 825936575 # number of cpu cycles simulated
+system.cpu.numCycles 824160129 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 611901617 # Number of instructions committed
system.cpu.committedOps 611901617 # Number of ops (including micro ops) committed
-system.cpu.discardedOps 13262650 # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps 12834592 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
-system.cpu.cpi 1.349787 # CPI: cycles per instruction
-system.cpu.ipc 0.740858 # IPC: instructions per cycle
-system.cpu.tickCycles 740975160 # Number of cycles that the object actually ticked
-system.cpu.idleCycles 84961415 # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.replacements 2535462 # number of replacements
-system.cpu.dcache.tags.tagsinuse 4087.659006 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 202664910 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 2539558 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 79.803222 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 1636438500 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 4087.659006 # Average occupied blocks per requestor
+system.cpu.cpi 1.346883 # CPI: cycles per instruction
+system.cpu.ipc 0.742455 # IPC: instructions per cycle
+system.cpu.tickCycles 739333640 # Number of cycles that the object actually ticked
+system.cpu.idleCycles 84826489 # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.replacements 2535265 # number of replacements
+system.cpu.dcache.tags.tagsinuse 4087.660702 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 202570424 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 2539361 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 79.772204 # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle 1635033500 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data 4087.660702 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.997964 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.997964 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 74 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 830 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3 3144 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 73 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2 829 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3 3145 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 414773666 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 414773666 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 146998717 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 146998717 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 55666193 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 55666193 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 202664910 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 202664910 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 202664910 # number of overall hits
-system.cpu.dcache.overall_hits::total 202664910 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 1908303 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 1908303 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 1543841 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 1543841 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 3452144 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 3452144 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 3452144 # number of overall misses
-system.cpu.dcache.overall_misses::total 3452144 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 37694000500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 37694000500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 47697864000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 47697864000 # number of WriteReq miss cycles
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system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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@@ -409,103 +413,103 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79564.106203 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 79554.365436 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78179.213483 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79564.106203 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 79554.365436 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -647,114 +651,114 @@ system.cpu.l2cache.fast_writes 0 # nu
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 293459 # number of writebacks
system.cpu.l2cache.writebacks::total 293459 # number of writebacks
-system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 739 # number of CleanEvict MSHR misses
-system.cpu.l2cache.CleanEvict_mshr_misses::total 739 # number of CleanEvict MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206263 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 206263 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2672 # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2672 # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 170699 # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total 170699 # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 2672 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 376962 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 379634 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 2672 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 376962 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 379634 # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 14142949000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 14142949000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 179822500 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 179822500 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 12051969500 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 12051969500 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 179822500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26194918500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 26374741000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 179822500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26194918500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 26374741000 # number of overall MSHR miss cycles
+system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 738 # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::total 738 # number of CleanEvict MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206261 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 206261 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2670 # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2670 # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 170676 # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total 170676 # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 2670 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 376937 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 379607 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 2670 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 376937 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 379607 # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 14156868500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 14156868500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 182038500 # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 182038500 # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 12064417000 # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 12064417000 # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 182038500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26221285500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 26403324000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 182038500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26221285500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 26403324000 # number of overall MSHR miss cycles
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.265073 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.265073 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.535578 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.535578 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.096910 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.096910 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.535578 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.148436 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.149195 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.535578 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.148436 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.149195 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68567.552106 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68567.552106 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67298.839820 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67298.839820 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70603.632710 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70603.632710 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67298.839820 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69489.546692 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69474.127712 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67298.839820 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69489.546692 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69474.127712 # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.265062 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.265062 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.536037 # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.536037 # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.096909 # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.096909 # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.536037 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.148438 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.149197 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.536037 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.148438 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.149197 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68635.701853 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68635.701853 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68179.213483 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68179.213483 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70686.077714 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70686.077714 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68179.213483 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69564.106203 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69554.365436 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68179.213483 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69564.106203 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69554.365436 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadResp 1766410 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 2633253 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict 252293 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 778137 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 778137 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq 4989 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq 1761421 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 13138 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7614578 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 7627716 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 319296 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312278528 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 312597824 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 346924 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 5430093 # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadResp 1766182 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 2633081 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict 252234 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 778160 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 778160 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq 4981 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq 1761201 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 13115 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7613987 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 7627102 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 318784 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312254912 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 312573696 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 346897 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 5429657 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 1.063889 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.244555 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.244556 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 5083169 93.61% 93.61% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 346924 6.39% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 5082760 93.61% 93.61% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 346897 6.39% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 5430093 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 4881378500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total 5429657 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 4881002000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 7483500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 7471500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 3809337000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 3809041500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%)
-system.membus.trans_dist::ReadResp 173371 # Transaction distribution
+system.membus.trans_dist::ReadResp 173346 # Transaction distribution
system.membus.trans_dist::Writeback 293459 # Transaction distribution
-system.membus.trans_dist::CleanEvict 51814 # Transaction distribution
-system.membus.trans_dist::ReadExReq 206263 # Transaction distribution
-system.membus.trans_dist::ReadExResp 206263 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 173371 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1104541 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 1104541 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43077952 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 43077952 # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::CleanEvict 51785 # Transaction distribution
+system.membus.trans_dist::ReadExReq 206261 # Transaction distribution
+system.membus.trans_dist::ReadExResp 206261 # Transaction distribution
+system.membus.trans_dist::ReadSharedReq 173346 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1104458 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 1104458 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43076224 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 43076224 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 724907 # Request fanout histogram
+system.membus.snoop_fanout::samples 724851 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 724907 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 724851 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 724907 # Request fanout histogram
-system.membus.reqLayer0.occupancy 2020096000 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 724851 # Request fanout histogram
+system.membus.reqLayer0.occupancy 2020156500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.5 # Layer utilization (%)
-system.membus.respLayer1.occupancy 2009057000 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 2008875000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.5 # Layer utilization (%)
---------- End Simulation Statistics ----------
diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/minor-timing/config.ini
index 482664dec..a401ada34 100644
--- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/config.ini
+++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/config.ini
@@ -127,7 +127,7 @@ localPredictorSize=2048
numThreads=1
[system.cpu.dcache]
-type=BaseCache
+type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=2
@@ -586,7 +586,7 @@ eventq_index=0
opClass=InstPrefetch
[system.cpu.icache]
-type=BaseCache
+type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=2
@@ -696,7 +696,7 @@ sys=system
port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
-type=BaseCache
+type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=8
@@ -759,9 +759,9 @@ env=
errout=cerr
euid=100
eventq_index=0
-executable=/dist/m5/cpu2000/binaries/arm/linux/parser
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/parser
gid=100
-input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
+input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
kvmInSE=false
max_stack_size=67108864
output=cout
diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/simout b/tests/long/se/20.parser/ref/arm/linux/minor-timing/simout
index 83790a04a..984c172ad 100755
--- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/simout
+++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/simout
@@ -1,12 +1,14 @@
+Redirecting stdout to build/ARM/tests/opt/long/se/20.parser/arm/linux/minor-timing/simout
+Redirecting stderr to build/ARM/tests/opt/long/se/20.parser/arm/linux/minor-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Mar 15 2015 20:30:55
-gem5 started Mar 15 2015 20:31:14
-gem5 executing on zizzer2
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/minor-timing -re /z/stever/hg/gem5/tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/minor-timing
+gem5 compiled Sep 14 2015 23:29:19
+gem5 started Sep 15 2015 03:04:52
+gem5 executing on ribera.cs.wisc.edu
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/minor-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/minor-timing
+
Global frequency set at 1000000000000 ticks per second
- 0: system.cpu.isa: ISA system set to: 0 0x3275620
info: Entering event queue @ 0. Starting simulation...
Reading the dictionary files: *************************************************
@@ -68,4 +70,4 @@ info: Increasing stack size by one page.
about 2 million people attended
the five best costumes got prizes
No errors!
-Exiting @ tick 366358475500 because target called exit()
+Exiting @ tick 363605295500 because target called exit()
diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt
index 9049068c3..0b95ee278 100644
--- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt
@@ -1,105 +1,105 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.365934 # Number of seconds simulated
-sim_ticks 365934171500 # Number of ticks simulated
-final_tick 365934171500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.363605 # Number of seconds simulated
+sim_ticks 363605295500 # Number of ticks simulated
+final_tick 363605295500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 236242 # Simulator instruction rate (inst/s)
-host_op_rate 255881 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 170651382 # Simulator tick rate (ticks/s)
-host_mem_usage 317968 # Number of bytes of host memory used
-host_seconds 2144.34 # Real time elapsed on the host
+host_inst_rate 163495 # Simulator instruction rate (inst/s)
+host_op_rate 177087 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 117350463 # Simulator tick rate (ticks/s)
+host_mem_usage 312624 # Number of bytes of host memory used
+host_seconds 3098.46 # Real time elapsed on the host
sim_insts 506582156 # Number of instructions simulated
sim_ops 548695379 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 218560 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 8996480 # Number of bytes read from this memory
-system.physmem.bytes_read::total 9215040 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 218560 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 218560 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 6186432 # Number of bytes written to this memory
-system.physmem.bytes_written::total 6186432 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 3415 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 140570 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 143985 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 96663 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 96663 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 597266 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 24584968 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 25182234 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 597266 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 597266 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 16905860 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 16905860 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 16905860 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 597266 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 24584968 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 42088095 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 143985 # Number of read requests accepted
-system.physmem.writeReqs 96663 # Number of write requests accepted
-system.physmem.readBursts 143985 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 96663 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 9208192 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 6848 # Total number of bytes read from write queue
-system.physmem.bytesWritten 6184704 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 9215040 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 6186432 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 107 # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst 219264 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 9004480 # Number of bytes read from this memory
+system.physmem.bytes_read::total 9223744 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 219264 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 219264 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 6189056 # Number of bytes written to this memory
+system.physmem.bytes_written::total 6189056 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 3426 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 140695 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 144121 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 96704 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 96704 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 603028 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 24764436 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 25367463 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 603028 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 603028 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 17021358 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 17021358 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 17021358 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 603028 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 24764436 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 42388822 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 144121 # Number of read requests accepted
+system.physmem.writeReqs 96704 # Number of write requests accepted
+system.physmem.readBursts 144121 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 96704 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 9217792 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 5952 # Total number of bytes read from write queue
+system.physmem.bytesWritten 6187328 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 9223744 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 6189056 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 93 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 9335 # Per bank write bursts
-system.physmem.perBankRdBursts::1 8992 # Per bank write bursts
-system.physmem.perBankRdBursts::2 8932 # Per bank write bursts
-system.physmem.perBankRdBursts::3 8655 # Per bank write bursts
+system.physmem.perBankRdBursts::0 9327 # Per bank write bursts
+system.physmem.perBankRdBursts::1 8969 # Per bank write bursts
+system.physmem.perBankRdBursts::2 9002 # Per bank write bursts
+system.physmem.perBankRdBursts::3 8675 # Per bank write bursts
system.physmem.perBankRdBursts::4 9455 # Per bank write bursts
-system.physmem.perBankRdBursts::5 9355 # Per bank write bursts
-system.physmem.perBankRdBursts::6 8940 # Per bank write bursts
-system.physmem.perBankRdBursts::7 8097 # Per bank write bursts
-system.physmem.perBankRdBursts::8 8569 # Per bank write bursts
-system.physmem.perBankRdBursts::9 8673 # Per bank write bursts
-system.physmem.perBankRdBursts::10 8766 # Per bank write bursts
-system.physmem.perBankRdBursts::11 9474 # Per bank write bursts
-system.physmem.perBankRdBursts::12 9347 # Per bank write bursts
-system.physmem.perBankRdBursts::13 9510 # Per bank write bursts
-system.physmem.perBankRdBursts::14 8717 # Per bank write bursts
-system.physmem.perBankRdBursts::15 9061 # Per bank write bursts
-system.physmem.perBankWrBursts::0 6192 # Per bank write bursts
-system.physmem.perBankWrBursts::1 6097 # Per bank write bursts
-system.physmem.perBankWrBursts::2 6005 # Per bank write bursts
-system.physmem.perBankWrBursts::3 5812 # Per bank write bursts
-system.physmem.perBankWrBursts::4 6185 # Per bank write bursts
-system.physmem.perBankWrBursts::5 6187 # Per bank write bursts
-system.physmem.perBankWrBursts::6 6017 # Per bank write bursts
-system.physmem.perBankWrBursts::7 5496 # Per bank write bursts
-system.physmem.perBankWrBursts::8 5731 # Per bank write bursts
+system.physmem.perBankRdBursts::5 9352 # Per bank write bursts
+system.physmem.perBankRdBursts::6 8946 # Per bank write bursts
+system.physmem.perBankRdBursts::7 8102 # Per bank write bursts
+system.physmem.perBankRdBursts::8 8582 # Per bank write bursts
+system.physmem.perBankRdBursts::9 8671 # Per bank write bursts
+system.physmem.perBankRdBursts::10 8765 # Per bank write bursts
+system.physmem.perBankRdBursts::11 9475 # Per bank write bursts
+system.physmem.perBankRdBursts::12 9349 # Per bank write bursts
+system.physmem.perBankRdBursts::13 9515 # Per bank write bursts
+system.physmem.perBankRdBursts::14 8723 # Per bank write bursts
+system.physmem.perBankRdBursts::15 9120 # Per bank write bursts
+system.physmem.perBankWrBursts::0 6189 # Per bank write bursts
+system.physmem.perBankWrBursts::1 6094 # Per bank write bursts
+system.physmem.perBankWrBursts::2 6010 # Per bank write bursts
+system.physmem.perBankWrBursts::3 5821 # Per bank write bursts
+system.physmem.perBankWrBursts::4 6183 # Per bank write bursts
+system.physmem.perBankWrBursts::5 6186 # Per bank write bursts
+system.physmem.perBankWrBursts::6 6015 # Per bank write bursts
+system.physmem.perBankWrBursts::7 5498 # Per bank write bursts
+system.physmem.perBankWrBursts::8 5738 # Per bank write bursts
system.physmem.perBankWrBursts::9 5829 # Per bank write bursts
system.physmem.perBankWrBursts::10 5965 # Per bank write bursts
-system.physmem.perBankWrBursts::11 6464 # Per bank write bursts
+system.physmem.perBankWrBursts::11 6463 # Per bank write bursts
system.physmem.perBankWrBursts::12 6313 # Per bank write bursts
-system.physmem.perBankWrBursts::13 6284 # Per bank write bursts
-system.physmem.perBankWrBursts::14 6001 # Per bank write bursts
-system.physmem.perBankWrBursts::15 6058 # Per bank write bursts
+system.physmem.perBankWrBursts::13 6285 # Per bank write bursts
+system.physmem.perBankWrBursts::14 6005 # Per bank write bursts
+system.physmem.perBankWrBursts::15 6083 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 365934145500 # Total gap between requests
+system.physmem.totGap 363605269500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 143985 # Read request sizes (log2)
+system.physmem.readPktSize::6 144121 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 96663 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 143524 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 334 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 20 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 96704 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 143663 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 343 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 22 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
@@ -144,41 +144,41 @@ system.physmem.wrQLenPdf::11 1 # Wh
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 2938 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 3097 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 5547 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 5683 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 5699 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 5674 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 5666 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 5660 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 5674 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 5679 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 5704 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 5683 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 5702 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 5694 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 5642 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 5663 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 5606 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 5586 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 15 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 9 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 4 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 2 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 2949 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 3103 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 5548 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 5659 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 5682 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 5668 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 5673 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 5677 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 5682 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 5670 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 5674 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 5686 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 5701 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 5716 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 5669 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 5677 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 5614 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 5594 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33 18 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34 11 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35 7 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36 4 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40 3 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43 3 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44 3 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46 2 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
@@ -193,107 +193,122 @@ system.physmem.wrQLenPdf::60 0 # Wh
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 65249 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 235.897316 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 156.545884 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 241.443874 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 24707 37.87% 37.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 18339 28.11% 65.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 7015 10.75% 76.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 7835 12.01% 88.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 2110 3.23% 91.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 1145 1.75% 93.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 725 1.11% 94.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 601 0.92% 95.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 2772 4.25% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 65249 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 5581 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 25.778176 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 381.924168 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023 5576 99.91% 99.91% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047 4 0.07% 99.98% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples 65251 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 236.074482 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 156.620272 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 241.651300 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 24697 37.85% 37.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 18374 28.16% 66.01% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 6917 10.60% 76.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 7938 12.17% 88.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 2038 3.12% 91.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 1147 1.76% 93.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 769 1.18% 94.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 621 0.95% 95.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 2750 4.21% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 65251 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 5585 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 25.786571 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 381.841879 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023 5581 99.93% 99.93% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047 3 0.05% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 5581 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 5581 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 17.315176 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 17.217549 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 2.442698 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-17 2634 47.20% 47.20% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18-19 2799 50.15% 97.35% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-21 58 1.04% 98.39% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22-23 24 0.43% 98.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-25 19 0.34% 99.16% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26-27 10 0.18% 99.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-29 9 0.16% 99.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::30-31 9 0.16% 99.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-33 3 0.05% 99.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::34-35 4 0.07% 99.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-37 3 0.05% 99.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-41 4 0.07% 99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-49 1 0.02% 99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-73 1 0.02% 99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::74-75 2 0.04% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-93 1 0.02% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 5581 # Writes before turning the bus around for reads
-system.physmem.totQLat 1559327000 # Total ticks spent queuing
-system.physmem.totMemAccLat 4257039500 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 719390000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 10837.84 # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total 5585 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 5585 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 17.310116 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 17.217866 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 2.213646 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16 2534 45.37% 45.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17 92 1.65% 47.02% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18 2660 47.63% 94.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19 156 2.79% 97.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20 36 0.64% 98.08% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21 18 0.32% 98.41% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22 16 0.29% 98.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23 9 0.16% 98.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24 7 0.13% 98.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25 10 0.18% 99.16% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26 4 0.07% 99.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::27 4 0.07% 99.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28 4 0.07% 99.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::29 6 0.11% 99.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::30 2 0.04% 99.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::31 4 0.07% 99.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32 3 0.05% 99.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::33 4 0.07% 99.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::35 2 0.04% 99.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::37 2 0.04% 99.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::39 1 0.02% 99.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40 1 0.02% 99.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::43 1 0.02% 99.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44 1 0.02% 99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::47 1 0.02% 99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::50 2 0.04% 99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52 1 0.02% 99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::53 1 0.02% 99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::55 1 0.02% 99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::61 1 0.02% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::62 1 0.02% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 5585 # Writes before turning the bus around for reads
+system.physmem.totQLat 1541292750 # Total ticks spent queuing
+system.physmem.totMemAccLat 4241817750 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 720140000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 10701.34 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 29587.84 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 25.16 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 16.90 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 25.18 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 16.91 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 29451.34 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 25.35 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 17.02 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 25.37 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 17.02 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.33 # Data bus utilization in percentage
system.physmem.busUtilRead 0.20 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.13 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 20.48 # Average write queue length when enqueuing
-system.physmem.readRowHits 110804 # Number of row buffer hits during reads
-system.physmem.writeRowHits 64456 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 77.01 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 66.68 # Row buffer hit rate for writes
-system.physmem.avgGap 1520619.93 # Average gap between requests
-system.physmem.pageHitRate 72.86 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 248300640 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 135481500 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 559572000 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 310819680 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 23900794320 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 47511748935 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 177881418000 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 250548135075 # Total energy per rank (pJ)
-system.physmem_0.averagePower 684.687479 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 295615195000 # Time in different power states
-system.physmem_0.memoryStateTime::REF 12219220000 # Time in different power states
+system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 19.51 # Average write queue length when enqueuing
+system.physmem.readRowHits 110876 # Number of row buffer hits during reads
+system.physmem.writeRowHits 64571 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 76.98 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 66.77 # Row buffer hit rate for writes
+system.physmem.avgGap 1509831.91 # Average gap between requests
+system.physmem.pageHitRate 72.88 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 248028480 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 135333000 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 560164800 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 310884480 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 23748734880 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 47382783300 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 176597692500 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 248983621440 # Total energy per rank (pJ)
+system.physmem_0.averagePower 684.768610 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 293478926000 # Time in different power states
+system.physmem_0.memoryStateTime::REF 12141480000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 58096250000 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 57982170250 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 244785240 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 133563375 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 562356600 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 315174240 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 23900794320 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 46698412230 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 178594871250 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 250449957255 # Total energy per rank (pJ)
-system.physmem_1.averagePower 684.419183 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 296806540250 # Time in different power states
-system.physmem_1.memoryStateTime::REF 12219220000 # Time in different power states
+system.physmem_1.actEnergy 245080080 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 133724250 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 563004000 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 315375120 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 23748734880 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 46983341835 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 176948079750 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 248937339915 # Total energy per rank (pJ)
+system.physmem_1.averagePower 684.641324 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 294063578500 # Time in different power states
+system.physmem_1.memoryStateTime::REF 12141480000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 56906569250 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 57397836750 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.cpu.branchPred.lookups 132492243 # Number of BP lookups
-system.cpu.branchPred.condPredicted 98438822 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 6555205 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 68897926 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 64816869 # Number of BTB hits
+system.cpu.branchPred.lookups 131896308 # Number of BP lookups
+system.cpu.branchPred.condPredicted 98031712 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 6139352 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 68410049 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 64397752 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 94.076662 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 10008233 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 17907 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 94.134930 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 9981293 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 18014 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
@@ -412,98 +427,98 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 548 # Number of system calls
-system.cpu.numCycles 731868343 # number of cpu cycles simulated
+system.cpu.numCycles 727210591 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 506582156 # Number of instructions committed
system.cpu.committedOps 548695379 # Number of ops (including micro ops) committed
-system.cpu.discardedOps 13915585 # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps 13199856 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
-system.cpu.cpi 1.444718 # CPI: cycles per instruction
-system.cpu.ipc 0.692177 # IPC: instructions per cycle
-system.cpu.tickCycles 695013398 # Number of cycles that the object actually ticked
-system.cpu.idleCycles 36854945 # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.replacements 1139741 # number of replacements
-system.cpu.dcache.tags.tagsinuse 4070.950270 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 171285752 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 1143837 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 149.746644 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 4896340500 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 4070.950270 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.993884 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.993884 # Average percentage of cache occupancy
+system.cpu.cpi 1.435524 # CPI: cycles per instruction
+system.cpu.ipc 0.696610 # IPC: instructions per cycle
+system.cpu.tickCycles 690727435 # Number of cycles that the object actually ticked
+system.cpu.idleCycles 36483156 # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.replacements 1139971 # number of replacements
+system.cpu.dcache.tags.tagsinuse 4070.789837 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 171168979 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 1144067 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 149.614471 # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle 4896334500 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data 4070.789837 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.993845 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.993845 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 549 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3 3503 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2 551 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3 3500 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 346825855 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 346825855 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 114767186 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 114767186 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 53538711 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 53538711 # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data 2773 # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total 2773 # number of SoftPFReq hits
+system.cpu.dcache.tags.tag_accesses 346593001 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 346593001 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 114650515 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 114650515 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 53538628 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 53538628 # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data 2754 # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total 2754 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 168305897 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 168305897 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 168308670 # number of overall hits
-system.cpu.dcache.overall_hits::total 168308670 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 854648 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 854648 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 700595 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 700595 # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data 14 # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total 14 # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data 1555243 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 1555243 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 1555257 # number of overall misses
-system.cpu.dcache.overall_misses::total 1555257 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 14022869000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 14022869000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 21909880500 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 21909880500 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 35932749500 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 35932749500 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 35932749500 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 35932749500 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 115621834 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 115621834 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_hits::cpu.data 168189143 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 168189143 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 168191897 # number of overall hits
+system.cpu.dcache.overall_hits::total 168191897 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 854793 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 854793 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 700678 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 700678 # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data 17 # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total 17 # number of SoftPFReq misses
+system.cpu.dcache.demand_misses::cpu.data 1555471 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 1555471 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 1555488 # number of overall misses
+system.cpu.dcache.overall_misses::total 1555488 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 14024452000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 14024452000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 21892214000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 21892214000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 35916666000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 35916666000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 35916666000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 35916666000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 115505308 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 115505308 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data 2787 # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total 2787 # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data 2771 # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total 2771 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 169861140 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 169861140 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 169863927 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 169863927 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.007392 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.007392 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.012917 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.012917 # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.005023 # miss rate for SoftPFReq accesses
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system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -512,111 +527,111 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -625,128 +640,128 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 2 # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 15 # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::total 15 # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 14 # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::total 14 # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data 15 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total 17 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data 14 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total 16 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data 15 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total 17 # number of overall MSHR hits
-system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1183 # number of CleanEvict MSHR misses
-system.cpu.l2cache.CleanEvict_mshr_misses::total 1183 # number of CleanEvict MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100813 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 100813 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3415 # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3415 # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 39757 # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total 39757 # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 3415 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 140570 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 143985 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 3415 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 140570 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 143985 # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6905945500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6905945500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 235984000 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 235984000 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2887628500 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2887628500 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 235984000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9793574000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 10029558000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 235984000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9793574000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 10029558000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_hits::cpu.data 14 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total 16 # number of overall MSHR hits
+system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1193 # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::total 1193 # number of CleanEvict MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100829 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 100829 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3426 # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3426 # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 39866 # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total 39866 # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 3426 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 140695 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 144121 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 3426 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 140695 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 144121 # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6896262500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6896262500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 237598000 # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 237598000 # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2886048500 # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2886048500 # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 237598000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9782311000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 10019909000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 237598000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9782311000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 10019909000 # number of overall MSHR miss cycles
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.282885 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.282885 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.174529 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.174529 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.050487 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.050487 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.174529 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.122893 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.123762 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.174529 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.122893 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.123762 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68502.529436 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68502.529436 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69102.196193 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69102.196193 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72631.951606 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72631.951606 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69102.196193 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69670.441773 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69656.964267 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69102.196193 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69670.441773 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69656.964267 # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.282896 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.282896 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.174876 # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.174876 # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.050614 # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.050614 # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.174876 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.122978 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.123852 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.174876 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.122978 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.123852 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68395.625267 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68395.625267 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69351.430239 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69351.430239 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72393.731501 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72393.731501 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69351.430239 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69528.490707 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69524.281680 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69351.430239 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69528.490707 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69524.281680 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadResp 807030 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 1165155 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict 98658 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 356374 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 356374 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq 19567 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq 787463 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 56593 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3422797 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 3479390 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1252288 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141589056 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 142841344 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 111231 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 2432071 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 1.045735 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.208910 # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadResp 807241 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 1165278 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict 98858 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 356417 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 356417 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq 19591 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq 787650 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 56664 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3423421 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 3480085 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1253824 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141609024 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 142862848 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 111367 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 2432715 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1.045779 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.209005 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 2320840 95.43% 95.43% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 111231 4.57% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 2321348 95.42% 95.42% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 111367 4.58% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 2432071 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 2228912000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total 2432715 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 2229248000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 29351498 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 29387997 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 1715762985 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 1716107486 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%)
-system.membus.trans_dist::ReadResp 43172 # Transaction distribution
-system.membus.trans_dist::Writeback 96663 # Transaction distribution
-system.membus.trans_dist::CleanEvict 13165 # Transaction distribution
-system.membus.trans_dist::ReadExReq 100813 # Transaction distribution
-system.membus.trans_dist::ReadExResp 100813 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 43172 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 397798 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 397798 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15401472 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 15401472 # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadResp 43292 # Transaction distribution
+system.membus.trans_dist::Writeback 96704 # Transaction distribution
+system.membus.trans_dist::CleanEvict 13244 # Transaction distribution
+system.membus.trans_dist::ReadExReq 100829 # Transaction distribution
+system.membus.trans_dist::ReadExResp 100829 # Transaction distribution
+system.membus.trans_dist::ReadSharedReq 43292 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 398190 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 398190 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15412800 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 15412800 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 253813 # Request fanout histogram
+system.membus.snoop_fanout::samples 254069 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 253813 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 254069 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 253813 # Request fanout histogram
-system.membus.reqLayer0.occupancy 683218000 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 254069 # Request fanout histogram
+system.membus.reqLayer0.occupancy 683631500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.2 # Layer utilization (%)
-system.membus.respLayer1.occupancy 764295250 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 765040250 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
---------- End Simulation Statistics ----------
diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini
index 8909daba1..2ccb6f3ec 100644
--- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini
@@ -149,7 +149,7 @@ instShiftAmt=2
numThreads=1
[system.cpu.dcache]
-type=BaseCache
+type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=2
@@ -490,7 +490,7 @@ opLat=4
pipelined=true
[system.cpu.icache]
-type=BaseCache
+type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=2
@@ -600,7 +600,7 @@ sys=system
port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
-type=BaseCache
+type=Cache
children=prefetcher tags
addr_ranges=0:18446744073709551615
assoc=16
@@ -688,9 +688,9 @@ env=
errout=cerr
euid=100
eventq_index=0
-executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/parser
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/parser
gid=100
-input=/home/stever/m5/dist/cpu2000/data/parser/mdred/input/parser.in
+input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
kvmInSE=false
max_stack_size=67108864
output=cout
diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini
index 0b92236c6..bc3661e7a 100644
--- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini
@@ -80,7 +80,7 @@ dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
-type=BaseCache
+type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=2
@@ -156,7 +156,7 @@ sys=system
port=system.cpu.toL2Bus.slave[3]
[system.cpu.icache]
-type=BaseCache
+type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=2
@@ -266,7 +266,7 @@ sys=system
port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
-type=BaseCache
+type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=8
diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini
index 0db544c43..0416dfaa7 100644
--- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini
+++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini
@@ -156,7 +156,7 @@ localPredictorSize=2048
numThreads=1
[system.cpu.dcache]
-type=BaseCache
+type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=2
@@ -513,7 +513,7 @@ opLat=3
pipelined=false
[system.cpu.icache]
-type=BaseCache
+type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=2
@@ -579,7 +579,7 @@ system=system
port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
-type=BaseCache
+type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=8
@@ -642,9 +642,9 @@ env=
errout=cerr
euid=100
eventq_index=0
-executable=/home/stever/m5/dist/cpu2000/binaries/x86/linux/parser
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/parser
gid=100
-input=/home/stever/m5/dist/cpu2000/data/parser/mdred/input/parser.in
+input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
kvmInSE=false
max_stack_size=67108864
output=cout
diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout
index 67a40aa52..bfd9de2ec 100755
--- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout
+++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout
@@ -3,17 +3,18 @@ Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing/
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jul 5 2015 17:24:59
-gem5 started Jul 5 2015 17:25:16
+gem5 compiled Sep 14 2015 22:13:36
+gem5 started Sep 14 2015 22:14:29
gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
- Reading the dictionary files: *********info: Increasing stack size by one page.
+ Reading the dictionary files: **info: Increasing stack size by one page.
+*******info: Increasing stack size by one page.
+******************************info: Increasing stack size by one page.
info: Increasing stack size by one page.
-**********************************info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
@@ -24,8 +25,7 @@ info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-******
+**********
58924 words stored in 3784810 bytes
@@ -37,6 +37,10 @@ Processing sentences in batch mode
Echoing of input sentence turned on.
* as had expected the party to be a success , it was a success
+* do you know where John 's
+* he said that , finding that it was impossible to get work as a waiter , he would work as a janitor
+* how fast the program is it
+* I am wondering whether to invite to the party
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
@@ -45,10 +49,6 @@ info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
-* do you know where John 's
-* he said that , finding that it was impossible to get work as a waiter , he would work as a janitor
-* how fast the program is it
-* I am wondering whether to invite to the party
* I gave him for his birthday it
* I thought terrible after our discussion
* I wonder how much money have you earned
@@ -91,4 +91,4 @@ info: Increasing stack size by one page.
about 2 million people attended
the five best costumes got prizes
No errors!
-Exiting @ tick 417250627500 because target called exit()
+Exiting @ tick 403706643500 because target called exit()
diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
index 0dda4ffb8..c2ca7f71b 100644
--- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
@@ -1,107 +1,107 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.417316 # Number of seconds simulated
-sim_ticks 417315805000 # Number of ticks simulated
-final_tick 417315805000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.403707 # Number of seconds simulated
+sim_ticks 403706643500 # Number of ticks simulated
+final_tick 403706643500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 92447 # Simulator instruction rate (inst/s)
-host_op_rate 170945 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 46657066 # Simulator tick rate (ticks/s)
-host_mem_usage 432180 # Number of bytes of host memory used
-host_seconds 8944.32 # Real time elapsed on the host
+host_inst_rate 76271 # Simulator instruction rate (inst/s)
+host_op_rate 141034 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 37237827 # Simulator tick rate (ticks/s)
+host_mem_usage 423672 # Number of bytes of host memory used
+host_seconds 10841.31 # Real time elapsed on the host
sim_insts 826877109 # Number of instructions simulated
sim_ops 1528988701 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 223744 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 24530944 # Number of bytes read from this memory
-system.physmem.bytes_read::total 24754688 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 223744 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 223744 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 18881856 # Number of bytes written to this memory
-system.physmem.bytes_written::total 18881856 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 3496 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 383296 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 386792 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 295029 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 295029 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 536150 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 58782686 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 59318836 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 536150 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 536150 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 45245964 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 45245964 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 45245964 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 536150 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 58782686 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 104564801 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 386792 # Number of read requests accepted
-system.physmem.writeReqs 295029 # Number of write requests accepted
-system.physmem.readBursts 386792 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 295029 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 24733440 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 21248 # Total number of bytes read from write queue
-system.physmem.bytesWritten 18880128 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 24754688 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 18881856 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 332 # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst 216320 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 24497408 # Number of bytes read from this memory
+system.physmem.bytes_read::total 24713728 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 216320 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 216320 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 18869312 # Number of bytes written to this memory
+system.physmem.bytes_written::total 18869312 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 3380 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 382772 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 386152 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 294833 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 294833 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 535835 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 60681211 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 61217046 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 535835 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 535835 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 46740157 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 46740157 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 46740157 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 535835 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 60681211 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 107957203 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 386152 # Number of read requests accepted
+system.physmem.writeReqs 294833 # Number of write requests accepted
+system.physmem.readBursts 386152 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 294833 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 24695616 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 18112 # Total number of bytes read from write queue
+system.physmem.bytesWritten 18867776 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 24713728 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 18869312 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 283 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 179000 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 24059 # Per bank write bursts
-system.physmem.perBankRdBursts::1 26401 # Per bank write bursts
-system.physmem.perBankRdBursts::2 24741 # Per bank write bursts
-system.physmem.perBankRdBursts::3 24611 # Per bank write bursts
-system.physmem.perBankRdBursts::4 23500 # Per bank write bursts
-system.physmem.perBankRdBursts::5 23770 # Per bank write bursts
-system.physmem.perBankRdBursts::6 24546 # Per bank write bursts
-system.physmem.perBankRdBursts::7 24382 # Per bank write bursts
-system.physmem.perBankRdBursts::8 23722 # Per bank write bursts
-system.physmem.perBankRdBursts::9 23975 # Per bank write bursts
-system.physmem.perBankRdBursts::10 24786 # Per bank write bursts
-system.physmem.perBankRdBursts::11 24066 # Per bank write bursts
-system.physmem.perBankRdBursts::12 23221 # Per bank write bursts
-system.physmem.perBankRdBursts::13 22949 # Per bank write bursts
-system.physmem.perBankRdBursts::14 23843 # Per bank write bursts
-system.physmem.perBankRdBursts::15 23888 # Per bank write bursts
-system.physmem.perBankWrBursts::0 18612 # Per bank write bursts
-system.physmem.perBankWrBursts::1 19924 # Per bank write bursts
-system.physmem.perBankWrBursts::2 18985 # Per bank write bursts
-system.physmem.perBankWrBursts::3 19009 # Per bank write bursts
-system.physmem.perBankWrBursts::4 18161 # Per bank write bursts
-system.physmem.perBankWrBursts::5 18506 # Per bank write bursts
-system.physmem.perBankWrBursts::6 19135 # Per bank write bursts
-system.physmem.perBankWrBursts::7 19090 # Per bank write bursts
-system.physmem.perBankWrBursts::8 18676 # Per bank write bursts
-system.physmem.perBankWrBursts::9 18214 # Per bank write bursts
-system.physmem.perBankWrBursts::10 18884 # Per bank write bursts
-system.physmem.perBankWrBursts::11 17768 # Per bank write bursts
-system.physmem.perBankWrBursts::12 17389 # Per bank write bursts
-system.physmem.perBankWrBursts::13 16996 # Per bank write bursts
-system.physmem.perBankWrBursts::14 17798 # Per bank write bursts
-system.physmem.perBankWrBursts::15 17855 # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs 195189 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 24028 # Per bank write bursts
+system.physmem.perBankRdBursts::1 26400 # Per bank write bursts
+system.physmem.perBankRdBursts::2 24980 # Per bank write bursts
+system.physmem.perBankRdBursts::3 24600 # Per bank write bursts
+system.physmem.perBankRdBursts::4 23395 # Per bank write bursts
+system.physmem.perBankRdBursts::5 23728 # Per bank write bursts
+system.physmem.perBankRdBursts::6 24595 # Per bank write bursts
+system.physmem.perBankRdBursts::7 24357 # Per bank write bursts
+system.physmem.perBankRdBursts::8 23707 # Per bank write bursts
+system.physmem.perBankRdBursts::9 23543 # Per bank write bursts
+system.physmem.perBankRdBursts::10 24760 # Per bank write bursts
+system.physmem.perBankRdBursts::11 23969 # Per bank write bursts
+system.physmem.perBankRdBursts::12 23156 # Per bank write bursts
+system.physmem.perBankRdBursts::13 22899 # Per bank write bursts
+system.physmem.perBankRdBursts::14 23872 # Per bank write bursts
+system.physmem.perBankRdBursts::15 23880 # Per bank write bursts
+system.physmem.perBankWrBursts::0 18605 # Per bank write bursts
+system.physmem.perBankWrBursts::1 19929 # Per bank write bursts
+system.physmem.perBankWrBursts::2 19196 # Per bank write bursts
+system.physmem.perBankWrBursts::3 18982 # Per bank write bursts
+system.physmem.perBankWrBursts::4 18144 # Per bank write bursts
+system.physmem.perBankWrBursts::5 18488 # Per bank write bursts
+system.physmem.perBankWrBursts::6 19136 # Per bank write bursts
+system.physmem.perBankWrBursts::7 19077 # Per bank write bursts
+system.physmem.perBankWrBursts::8 18672 # Per bank write bursts
+system.physmem.perBankWrBursts::9 17940 # Per bank write bursts
+system.physmem.perBankWrBursts::10 18886 # Per bank write bursts
+system.physmem.perBankWrBursts::11 17736 # Per bank write bursts
+system.physmem.perBankWrBursts::12 17372 # Per bank write bursts
+system.physmem.perBankWrBursts::13 16987 # Per bank write bursts
+system.physmem.perBankWrBursts::14 17811 # Per bank write bursts
+system.physmem.perBankWrBursts::15 17848 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 417315698500 # Total gap between requests
+system.physmem.totGap 403706602500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 386792 # Read request sizes (log2)
+system.physmem.readPktSize::6 386152 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 295029 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 381444 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 4617 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 346 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 42 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 294833 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 380965 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 4554 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 304 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 37 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
@@ -144,46 +144,46 @@ system.physmem.wrQLenPdf::11 1 # Wh
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 6179 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 6585 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 16949 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 17533 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 17607 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 17642 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 17652 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 17664 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 17717 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 17682 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 17732 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 17672 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 17725 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 17728 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 17715 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 17888 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 17610 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 17539 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 36 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 21 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 19 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 18 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37 8 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38 10 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39 8 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40 9 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41 9 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42 11 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43 8 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44 8 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45 6 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46 6 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47 5 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48 4 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49 3 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51 2 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 6120 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::36 8 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37 4 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38 4 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40 3 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41 2 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42 2 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
@@ -193,347 +193,345 @@ system.physmem.wrQLenPdf::60 0 # Wh
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 147495 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 295.684816 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 174.392327 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 323.222401 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 54844 37.18% 37.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 40100 27.19% 64.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 13710 9.30% 73.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 7409 5.02% 78.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 5412 3.67% 82.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 3888 2.64% 84.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 3038 2.06% 87.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 2781 1.89% 88.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 16313 11.06% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 147495 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 17511 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 22.068928 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 218.794243 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023 17500 99.94% 99.94% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047 6 0.03% 99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-3071 1 0.01% 99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::3072-4095 2 0.01% 99.99% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples 146765 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 296.814963 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 175.408246 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 322.979648 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 54126 36.88% 36.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 39824 27.13% 64.01% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 13787 9.39% 73.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 7512 5.12% 78.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 5608 3.82% 82.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 3872 2.64% 84.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 3087 2.10% 87.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 2794 1.90% 88.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 16155 11.01% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 146765 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 17509 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 22.037923 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 218.270562 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023 17499 99.94% 99.94% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047 5 0.03% 99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::3072-4095 3 0.02% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::8192-9215 1 0.01% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 17511 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 17511 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 16.846668 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 16.775279 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 2.561224 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19 17315 98.88% 98.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23 151 0.86% 99.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27 21 0.12% 99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31 5 0.03% 99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35 3 0.02% 99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39 1 0.01% 99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43 1 0.01% 99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47 2 0.01% 99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51 1 0.01% 99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59 1 0.01% 99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63 1 0.01% 99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67 1 0.01% 99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79 3 0.02% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91 1 0.01% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103 1 0.01% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107 1 0.01% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131 1 0.01% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::212-215 1 0.01% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 17511 # Writes before turning the bus around for reads
-system.physmem.totQLat 4302860250 # Total ticks spent queuing
-system.physmem.totMemAccLat 11548985250 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 1932300000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 11134.04 # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total 17509 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 17509 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 16.837569 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 16.769084 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 2.527211 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19 17319 98.91% 98.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23 139 0.79% 99.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27 19 0.11% 99.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31 11 0.06% 99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35 2 0.01% 99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39 2 0.01% 99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43 2 0.01% 99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47 5 0.03% 99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51 1 0.01% 99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55 1 0.01% 99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59 1 0.01% 99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67 1 0.01% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71 1 0.01% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79 2 0.01% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83 1 0.01% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139 1 0.01% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::232-235 1 0.01% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 17509 # Writes before turning the bus around for reads
+system.physmem.totQLat 4289653250 # Total ticks spent queuing
+system.physmem.totMemAccLat 11524697000 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 1929345000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 11116.86 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 29884.04 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 59.27 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 45.24 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 59.32 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 45.25 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 29866.86 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 61.17 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 46.74 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 61.22 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 46.74 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 0.82 # Data bus utilization in percentage
-system.physmem.busUtilRead 0.46 # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite 0.35 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 22.40 # Average write queue length when enqueuing
-system.physmem.readRowHits 318003 # Number of row buffer hits during reads
-system.physmem.writeRowHits 215951 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 82.29 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 73.20 # Row buffer hit rate for writes
-system.physmem.avgGap 612060.49 # Average gap between requests
-system.physmem.pageHitRate 78.35 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 569562840 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 310773375 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 1528737600 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 980981280 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 27256781760 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 63486572355 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 194697293250 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 288830702460 # Total energy per rank (pJ)
-system.physmem_0.averagePower 692.121537 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 323337240250 # Time in different power states
-system.physmem_0.memoryStateTime::REF 13934960000 # Time in different power states
+system.physmem.busUtil 0.84 # Data bus utilization in percentage
+system.physmem.busUtilRead 0.48 # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite 0.37 # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 20.93 # Average write queue length when enqueuing
+system.physmem.readRowHits 317973 # Number of row buffer hits during reads
+system.physmem.writeRowHits 215927 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 82.40 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 73.24 # Row buffer hit rate for writes
+system.physmem.avgGap 592827.45 # Average gap between requests
+system.physmem.pageHitRate 78.43 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 569094120 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 310517625 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 1529307000 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 981933840 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 26367818880 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 62417540205 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 187468813500 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 279645025170 # Total energy per rank (pJ)
+system.physmem_0.averagePower 692.702062 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 311319479750 # Time in different power states
+system.physmem_0.memoryStateTime::REF 13480480000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 80039955000 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 78902125750 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 545136480 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 297445500 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 1485127800 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 930216960 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 27256781760 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 61714779795 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 196251513750 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 288481002045 # Total energy per rank (pJ)
-system.physmem_1.averagePower 691.283509 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 325936894250 # Time in different power states
-system.physmem_1.memoryStateTime::REF 13934960000 # Time in different power states
+system.physmem_1.actEnergy 540041040 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 294665250 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 1479816000 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 928013760 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 26367818880 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 60324869565 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 189304489500 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 279239713995 # Total energy per rank (pJ)
+system.physmem_1.averagePower 691.698075 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 314381404750 # Time in different power states
+system.physmem_1.memoryStateTime::REF 13480480000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 77440301000 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 75839865250 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.cpu.branchPred.lookups 230117471 # Number of BP lookups
-system.cpu.branchPred.condPredicted 230117471 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 9743461 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 131565165 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 128785895 # Number of BTB hits
+system.cpu.branchPred.lookups 219316547 # Number of BP lookups
+system.cpu.branchPred.condPredicted 219316547 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 8533340 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 124021938 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 121820147 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 97.887534 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 27740805 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 1463511 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 98.224676 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 27066490 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 1406992 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
system.cpu.workload.num_syscalls 551 # Number of system calls
-system.cpu.numCycles 834631611 # number of cpu cycles simulated
+system.cpu.numCycles 807413288 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 185091560 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 1269611575 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 230117471 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 156526700 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 638324625 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 20217139 # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles 543 # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles 96744 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 810626 # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles 1773 # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles 110 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 179459083 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 2721482 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes 2 # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples 834434550 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.830059 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.382636 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 175921222 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 1208610344 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 219316547 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 148886637 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 621541997 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 17781141 # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles 241 # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles 95442 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 760366 # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles 1422 # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles 41 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 170776115 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 2324492 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes 3 # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples 807211301 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.786075 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.367353 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 426827210 51.15% 51.15% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 33688698 4.04% 55.19% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 32854559 3.94% 59.13% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 33384869 4.00% 63.13% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 27147041 3.25% 66.38% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 27739461 3.32% 69.70% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 37019184 4.44% 74.14% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 33642570 4.03% 78.17% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 182130958 21.83% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 417064653 51.67% 51.67% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 32628603 4.04% 55.71% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 31895320 3.95% 59.66% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 32734486 4.06% 63.72% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 26590994 3.29% 67.01% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 26897855 3.33% 70.34% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 35141039 4.35% 74.70% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 31437377 3.89% 78.59% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 172820974 21.41% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 834434550 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.275711 # Number of branch fetches per cycle
-system.cpu.fetch.rate 1.521164 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 127499737 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 374953474 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 240627559 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 81245211 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 10108569 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 2225588633 # Number of instructions handled by decode
-system.cpu.rename.SquashCycles 10108569 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 159647168 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 159927889 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 39744 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 285634401 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 219076779 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 2175363345 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 166678 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 136608012 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents 24443504 # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents 48002145 # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands 2279615876 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 5501425511 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 3499355021 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 55759 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 807211301 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.271629 # Number of branch fetches per cycle
+system.cpu.fetch.rate 1.496892 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 120518152 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 370503139 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 225214950 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 82084490 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 8890570 # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts 2132165876 # Number of instructions handled by decode
+system.cpu.rename.SquashCycles 8890570 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 152539883 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 150620560 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 39985 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 271567858 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 223552445 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 2088589695 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 134600 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 138169190 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents 24839349 # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents 50537004 # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands 2190785289 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 5278493147 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 3357262511 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 59407 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 665575022 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 3123 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 2916 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 415832299 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 528432376 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 209864891 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 239237917 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 72205880 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 2101284212 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 24336 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 1827034633 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 401491 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 572319847 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 974276898 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 23784 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 834434550 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 2.189548 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 2.072515 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 576744435 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 3185 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 2908 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 421985771 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 507135954 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 200817604 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 229019753 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 68232285 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 2023164418 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 22990 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 1789038207 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 420221 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 494198707 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 833041498 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 22438 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 807211301 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 2.216320 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 2.070566 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 254639697 30.52% 30.52% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 125724347 15.07% 45.58% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 119353828 14.30% 59.89% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 111074898 13.31% 73.20% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 92504387 11.09% 84.28% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 61470741 7.37% 91.65% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 43061930 5.16% 96.81% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 19202673 2.30% 99.11% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 7402049 0.89% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 238530872 29.55% 29.55% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 123621910 15.31% 44.86% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 118898033 14.73% 59.59% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 107819129 13.36% 72.95% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 89545218 11.09% 84.04% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 60296093 7.47% 91.51% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 42279085 5.24% 96.75% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 18940691 2.35% 99.10% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 834434550 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 807211301 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
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-system.cpu.iq.fu_full::IntMult 0 0.00% 42.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 42.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 42.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 42.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 42.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 12172571 45.88% 88.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 3037482 11.45% 100.00% # attempts to use FU when none available
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+system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 42.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 42.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 42.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 12368193 45.83% 88.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 3098262 11.48% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 2711288 0.15% 0.15% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 1211298887 66.30% 66.45% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 388808 0.02% 66.47% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 3881058 0.21% 66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 134 0.00% 66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 33 0.00% 66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 403 0.00% 66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 435055867 23.81% 90.49% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 173698155 9.51% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass 2718353 0.15% 0.15% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 1183132640 66.13% 66.28% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 368609 0.02% 66.30% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 3881115 0.22% 66.52% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 137 0.00% 66.52% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.52% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.52% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 64 0.00% 66.52% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 344 0.00% 66.52% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.52% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 428541213 23.95% 90.48% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 170395732 9.52% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 1827034633 # Type of FU issued
-system.cpu.iq.rate 2.189031 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 26530239 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.014521 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 4515402541 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 2673889112 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 1796964967 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 33005 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 70700 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 7229 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 1850838268 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 15316 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 185431148 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 1789038207 # Type of FU issued
+system.cpu.iq.rate 2.215765 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 26987214 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.015085 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 4412665624 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 2517635859 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 1762385104 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 29526 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 68682 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 5548 # Number of floating instruction queue wakeup accesses
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system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
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system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
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system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
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system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
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system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
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system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
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system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards
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system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
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-system.cpu.commit.committed_per_cycle::1 175370720 23.17% 61.22% # Number of insts commited each cycle
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-system.cpu.commit.committed_per_cycle::6 9779675 1.29% 88.67% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 8926185 1.18% 89.85% # Number of insts commited each cycle
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+system.cpu.commit.committed_per_cycle::3 86300571 11.66% 79.76% # Number of insts commited each cycle
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+system.cpu.commit.committed_per_cycle::6 9870767 1.33% 88.19% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 8919978 1.21% 89.39% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 78508765 10.61% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 756729949 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 739988037 # Number of insts commited each cycle
system.cpu.commit.committedInsts 826877109 # Number of instructions committed
system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
@@ -579,344 +577,344 @@ system.cpu.commit.op_class_0::MemWrite 149160186 9.76% 100.00% # Cl
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 1528988701 # Class of committed instruction
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system.cpu.committedInsts 826877109 # Number of Instructions Simulated
system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated
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-system.cpu.cpi_total 1.009378 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.990709 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.990709 # IPC: Total IPC of All Threads
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+system.cpu.cpi_total 0.976461 # CPI: Total CPI of All Threads
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system.cpu.misc_regfile_writes 1 # number of misc regfile writes
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@@ -925,136 +923,136 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks 295029 # number of writebacks
-system.cpu.l2cache.writebacks::total 295029 # number of writebacks
+system.cpu.l2cache.writebacks::writebacks 294833 # number of writebacks
+system.cpu.l2cache.writebacks::total 294833 # number of writebacks
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits
-system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 2030 # number of CleanEvict MSHR misses
-system.cpu.l2cache.CleanEvict_mshr_misses::total 2030 # number of CleanEvict MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 178962 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total 178962 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206662 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 206662 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3497 # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3497 # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 176672 # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total 176672 # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 3497 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 383334 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 386831 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 3497 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 383334 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 386831 # number of overall MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 3764941068 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 3764941068 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 14314824000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 14314824000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 249717000 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 249717000 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 12450014500 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 12450014500 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 249717000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26764838500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 27014555500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 249717000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26764838500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 27014555500 # number of overall MSHR miss cycles
+system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1941 # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::total 1941 # number of CleanEvict MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 195142 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total 195142 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206554 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 206554 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3381 # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3381 # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 176265 # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total 176265 # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 3381 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 382819 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 386200 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 3381 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 382819 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 386200 # number of overall MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 4107801604 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 4107801604 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 14308484500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 14308484500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 242006000 # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 242006000 # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 12417930000 # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 12417930000 # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 242006000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26726414500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 26968420500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 242006000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26726414500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 26968420500 # number of overall MSHR miss cycles
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.989533 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.989533 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268119 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268119 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.405779 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.405779 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.099951 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.099951 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.405779 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.151016 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.151878 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.405779 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.151016 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.151878 # mshr miss rate for overall accesses
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 21037.656419 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 21037.656419 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69266.841509 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69266.841509 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71408.921933 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71408.921933 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70469.652803 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70469.652803 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71408.921933 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69821.196398 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69835.549633 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71408.921933 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69821.196398 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69835.549633 # average overall mshr miss latency
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.990664 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.990664 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268078 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268078 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.410515 # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.410515 # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.099902 # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.099902 # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.410515 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.151020 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.151861 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.410515 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.151020 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.151861 # mshr miss rate for overall accesses
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 21050.320300 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 21050.320300 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69272.367032 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69272.367032 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71578.231293 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71578.231293 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70450.344652 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70450.344652 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71578.231293 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69814.754492 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69830.192905 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71578.231293 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69814.754492 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69830.192905 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadResp 1957165 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 2627653 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict 256317 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 180855 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 180855 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 770784 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 770784 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq 189586 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq 1767580 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 204722 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7961776 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 8166498 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 551488 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311743232 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 312294720 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 535081 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 5804166 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 1.061010 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.239349 # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadResp 1969728 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 2625607 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict 254220 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq 196981 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp 196981 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 770499 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 770499 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq 205344 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq 1764386 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 219812 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7983854 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 8203666 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 526976 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311402176 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 311929152 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 550579 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 5828110 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1.060649 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.238686 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 5450053 93.90% 93.90% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 354113 6.10% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 5474639 93.94% 93.94% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 353471 6.06% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 5804166 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 5083850495 # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 284382490 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total 5828110 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 5096523027 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 308017990 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 3897973573 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%)
-system.membus.trans_dist::ReadResp 180168 # Transaction distribution
-system.membus.trans_dist::Writeback 295029 # Transaction distribution
-system.membus.trans_dist::CleanEvict 57519 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 179000 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 179000 # Transaction distribution
-system.membus.trans_dist::ReadExReq 206624 # Transaction distribution
-system.membus.trans_dist::ReadExResp 206624 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 180168 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1484132 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1484132 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 1484132 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43636544 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43636544 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 43636544 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.respLayer1.occupancy 3900818077 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%)
+system.membus.trans_dist::ReadResp 179644 # Transaction distribution
+system.membus.trans_dist::Writeback 294833 # Transaction distribution
+system.membus.trans_dist::CleanEvict 57066 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 195189 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 195189 # Transaction distribution
+system.membus.trans_dist::ReadExReq 206507 # Transaction distribution
+system.membus.trans_dist::ReadExResp 206507 # Transaction distribution
+system.membus.trans_dist::ReadSharedReq 179645 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1514580 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1514580 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 1514580 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43582976 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43582976 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 43582976 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 918340 # Request fanout histogram
+system.membus.snoop_fanout::samples 933240 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 918340 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 933240 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 918340 # Request fanout histogram
-system.membus.reqLayer0.occupancy 2219848930 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 0.5 # Layer utilization (%)
-system.membus.respLayer1.occupancy 2404009566 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 933240 # Request fanout histogram
+system.membus.reqLayer0.occupancy 2243803396 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.6 # Layer utilization (%)
+system.membus.respLayer1.occupancy 2433027599 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.6 # Layer utilization (%)
---------- End Simulation Statistics ----------
diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini b/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini
index de26fb04a..bab78d9da 100644
--- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini
@@ -84,7 +84,7 @@ clk_domain=system.cpu_clk_domain
eventq_index=0
[system.cpu.dcache]
-type=BaseCache
+type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=2
@@ -134,7 +134,7 @@ system=system
port=system.cpu.toL2Bus.slave[3]
[system.cpu.icache]
-type=BaseCache
+type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=2
@@ -200,7 +200,7 @@ system=system
port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
-type=BaseCache
+type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=8