diff options
Diffstat (limited to 'tests/long/se/20.parser')
4 files changed, 1427 insertions, 1427 deletions
diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index 5b82c90b2..5a3a68b8e 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.205973 # Number of seconds simulated -sim_ticks 205972871500 # Number of ticks simulated -final_tick 205972871500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.201852 # Number of seconds simulated +sim_ticks 201852280500 # Number of ticks simulated +final_tick 201852280500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 120709 # Simulator instruction rate (inst/s) -host_op_rate 135980 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 48850733 # Simulator tick rate (ticks/s) -host_mem_usage 233344 # Number of bytes of host memory used -host_seconds 4216.37 # Real time elapsed on the host +host_inst_rate 114620 # Simulator instruction rate (inst/s) +host_op_rate 129121 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 45458575 # Simulator tick rate (ticks/s) +host_mem_usage 239092 # Number of bytes of host memory used +host_seconds 4440.36 # Real time elapsed on the host sim_insts 508955133 # Number of instructions simulated sim_ops 573341693 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 219008 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10022656 # Number of bytes read from this memory -system.physmem.bytes_read::total 10241664 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 219008 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 219008 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6678912 # Number of bytes written to this memory -system.physmem.bytes_written::total 6678912 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3422 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 156604 # Number of read requests responded to by this memory -system.physmem.num_reads::total 160026 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 104358 # Number of write requests responded to by this memory -system.physmem.num_writes::total 104358 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1063286 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 48660078 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 49723364 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1063286 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1063286 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 32426173 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 32426173 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 32426173 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1063286 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 48660078 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 82149537 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 218816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10015872 # Number of bytes read from this memory +system.physmem.bytes_read::total 10234688 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 218816 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 218816 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6679360 # Number of bytes written to this memory +system.physmem.bytes_written::total 6679360 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3419 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 156498 # Number of read requests responded to by this memory +system.physmem.num_reads::total 159917 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 104365 # Number of write requests responded to by this memory +system.physmem.num_writes::total 104365 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 1084040 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 49619811 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50703851 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1084040 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1084040 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 33090337 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 33090337 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 33090337 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1084040 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 49619811 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 83794188 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,246 +77,246 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 411945744 # number of cpu cycles simulated +system.cpu.numCycles 403704562 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 184506499 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 144023121 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 7811219 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 98943918 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 90574887 # Number of BTB hits +system.cpu.BPredUnit.lookups 183613146 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 143294212 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 7789120 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 98042390 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 90143773 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 12841570 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 116417 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 119775248 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 774733961 # Number of instructions fetch has processed -system.cpu.fetch.Branches 184506499 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 103416457 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 173948363 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 37641339 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 87608822 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 33 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 852 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 115427194 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2630422 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 410365766 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.121718 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.964259 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 12795154 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 116199 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 119018383 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 771038085 # Number of instructions fetch has processed +system.cpu.fetch.Branches 183613146 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 102938927 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 173093371 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 37034444 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 81728576 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 14 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 370 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 114776707 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2639607 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 402291353 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.154621 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.975773 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 236430239 57.61% 57.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 14468090 3.53% 61.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 23474699 5.72% 66.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 23086036 5.63% 72.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 21070083 5.13% 77.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 13375231 3.26% 80.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 13311792 3.24% 84.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 12219273 2.98% 87.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 52930323 12.90% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 229210831 56.98% 56.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 14330362 3.56% 60.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 23398991 5.82% 66.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 22962860 5.71% 72.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 20943651 5.21% 77.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 13279878 3.30% 80.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 13299573 3.31% 83.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 12124758 3.01% 86.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 52740449 13.11% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 410365766 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.447890 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.880670 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 130418481 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 81705760 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 163995815 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 5288696 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 28957014 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 26711151 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 78514 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 846352874 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 312360 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 28957014 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 138753027 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 8994220 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 57785261 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 160771479 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 15104765 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 816103533 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1687 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2833405 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 8341364 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 82 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 971919658 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3572964194 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3572962534 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1660 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 402291353 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.454821 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.909907 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 129139991 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 76355942 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 163648868 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 4771100 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 28375452 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 26593121 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 78321 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 842377409 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 313716 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 28375452 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 137010485 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 5387793 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 57527480 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 160406240 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 13583903 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 812203916 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 883 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2847047 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 7163226 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 116 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 967528997 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3555884446 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3555882861 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1585 # Number of floating rename lookups system.cpu.rename.CommittedMaps 672200147 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 299719511 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 3043063 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 3043057 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 48313295 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 173521024 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 75304332 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 27654560 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 15950244 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 766864948 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 4467940 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 673990845 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1544807 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 195857289 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 503525509 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 746826 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 410365766 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.642415 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.726112 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 295328850 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 3042535 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 3042531 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 44411709 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 172477044 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 75019988 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 27139166 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 14058077 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 762853534 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 4467400 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 672309193 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1597303 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 191893802 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 493277148 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 746286 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 402291353 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.671200 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.739620 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 148669222 36.23% 36.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 76514251 18.65% 54.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 69467282 16.93% 71.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 54325200 13.24% 85.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 31258060 7.62% 92.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 16137199 3.93% 96.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 9372373 2.28% 98.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3363475 0.82% 99.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1258704 0.31% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 143645817 35.71% 35.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 74204584 18.45% 54.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 68520883 17.03% 71.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 53274856 13.24% 84.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 32167138 8.00% 92.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 16325737 4.06% 96.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 9421817 2.34% 98.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3434032 0.85% 99.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1296489 0.32% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 410365766 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 402291353 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 465577 4.81% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 6648335 68.74% 73.56% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2557266 26.44% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 436530 4.38% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 6785214 68.04% 72.42% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2750735 27.58% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 452813787 67.18% 67.18% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 386318 0.06% 67.24% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 122 0.00% 67.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 155728522 23.11% 90.35% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 65062093 9.65% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 451600936 67.17% 67.17% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 386071 0.06% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 116 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 155208445 23.09% 90.31% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 65113622 9.69% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 673990845 # Type of FU issued -system.cpu.iq.rate 1.636116 # Inst issue rate -system.cpu.iq.fu_busy_cnt 9671178 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014349 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1769563162 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 967995399 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 653126941 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 279 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 382 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 672309193 # Type of FU issued +system.cpu.iq.rate 1.665350 # Inst issue rate +system.cpu.iq.fu_busy_cnt 9972479 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014833 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1758479254 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 960016621 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 651381097 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 267 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 364 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 683661882 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 141 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 8511001 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 682281537 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 135 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 8428766 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 46747987 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 44107 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 809559 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 17700373 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 45704007 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 43585 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 806080 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 17416029 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 19520 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1145 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 19464 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1080 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 28957014 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 4178303 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 271851 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 772908179 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1249751 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 173521024 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 75304332 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2979209 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 139047 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 8399 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 809559 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4765794 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4187317 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8953111 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 663675930 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 152077702 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 10314915 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 28375452 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1989251 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 96453 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 768887058 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1243291 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 172477044 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 75019988 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2978672 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 38122 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 5312 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 806080 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4756345 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4163931 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8920276 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 661932492 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 151574229 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 10376701 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1575291 # number of nop insts executed -system.cpu.iew.exec_refs 215744053 # number of memory reference insts executed -system.cpu.iew.exec_branches 139807568 # Number of branches executed -system.cpu.iew.exec_stores 63666351 # Number of stores executed -system.cpu.iew.exec_rate 1.611076 # Inst execution rate -system.cpu.iew.wb_sent 658363692 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 653126957 # cumulative count of insts written-back -system.cpu.iew.wb_producers 376897633 # num instructions producing a value -system.cpu.iew.wb_consumers 649094102 # num instructions consuming a value +system.cpu.iew.exec_nop 1566124 # number of nop insts executed +system.cpu.iew.exec_refs 215230219 # number of memory reference insts executed +system.cpu.iew.exec_branches 139385144 # Number of branches executed +system.cpu.iew.exec_stores 63655990 # Number of stores executed +system.cpu.iew.exec_rate 1.639646 # Inst execution rate +system.cpu.iew.wb_sent 656632887 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 651381113 # cumulative count of insts written-back +system.cpu.iew.wb_producers 375930281 # num instructions producing a value +system.cpu.iew.wb_consumers 649035735 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.585468 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.580652 # average fanout of values written-back +system.cpu.iew.wb_rate 1.613509 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.579214 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 198243748 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 194215600 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 3721114 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 7735785 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 381408753 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.506745 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.186982 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 7713933 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 373915902 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.536938 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.196487 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 167968054 44.04% 44.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 103591951 27.16% 71.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 34406436 9.02% 80.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 19105358 5.01% 85.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 16473336 4.32% 89.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7646678 2.00% 91.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 6906631 1.81% 93.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3084312 0.81% 94.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 22225997 5.83% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 161102013 43.09% 43.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 102670077 27.46% 70.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 34449601 9.21% 79.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 18433917 4.93% 84.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 17480337 4.67% 89.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7750601 2.07% 91.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 6975147 1.87% 93.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3144360 0.84% 94.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 21909849 5.86% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 381408753 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 373915902 # Number of insts commited each cycle system.cpu.commit.committedInsts 510299017 # Number of instructions committed system.cpu.commit.committedOps 574685577 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -327,69 +327,69 @@ system.cpu.commit.branches 122291783 # Nu system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 473701621 # Number of committed integer instructions. system.cpu.commit.function_calls 9757362 # Number of function calls committed. -system.cpu.commit.bw_lim_events 22225997 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 21909849 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1132104943 # The number of ROB reads -system.cpu.rob.rob_writes 1574958649 # The number of ROB writes -system.cpu.timesIdled 76497 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 1579978 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 1120900092 # The number of ROB reads +system.cpu.rob.rob_writes 1566319482 # The number of ROB writes +system.cpu.timesIdled 51224 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 1413209 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 508955133 # Number of Instructions Simulated system.cpu.committedOps 573341693 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 508955133 # Number of Instructions Simulated -system.cpu.cpi 0.809395 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.809395 # CPI: Total CPI of All Threads -system.cpu.ipc 1.235491 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.235491 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3096810735 # number of integer regfile reads -system.cpu.int_regfile_writes 761477780 # number of integer regfile writes +system.cpu.cpi 0.793203 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.793203 # CPI: Total CPI of All Threads +system.cpu.ipc 1.260712 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.260712 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3088645957 # number of integer regfile reads +system.cpu.int_regfile_writes 759574381 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 1003236717 # number of misc regfile reads +system.cpu.misc_regfile_reads 999041226 # number of misc regfile reads system.cpu.misc_regfile_writes 4464048 # number of misc regfile writes -system.cpu.icache.replacements 15737 # number of replacements -system.cpu.icache.tagsinuse 1093.946958 # Cycle average of tags in use -system.cpu.icache.total_refs 115407568 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 17598 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 6557.993408 # Average number of references to valid blocks. +system.cpu.icache.replacements 15551 # number of replacements +system.cpu.icache.tagsinuse 1091.493459 # Cycle average of tags in use +system.cpu.icache.total_refs 114757583 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 17412 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 6590.718068 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1093.946958 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.534154 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.534154 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 115407568 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 115407568 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 115407568 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 115407568 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 115407568 # number of overall hits -system.cpu.icache.overall_hits::total 115407568 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 19626 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 19626 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 19626 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 19626 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 19626 # number of overall misses -system.cpu.icache.overall_misses::total 19626 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 282974000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 282974000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 282974000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 282974000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 282974000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 282974000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 115427194 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 115427194 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 115427194 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 115427194 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 115427194 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 115427194 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000170 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000170 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000170 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000170 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000170 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000170 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14418.322633 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14418.322633 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14418.322633 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14418.322633 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14418.322633 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14418.322633 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1091.493459 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.532956 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.532956 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 114757583 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 114757583 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 114757583 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 114757583 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 114757583 # number of overall hits +system.cpu.icache.overall_hits::total 114757583 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 19124 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 19124 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 19124 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 19124 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 19124 # number of overall misses +system.cpu.icache.overall_misses::total 19124 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 228709500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 228709500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 228709500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 228709500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 228709500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 228709500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 114776707 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 114776707 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 114776707 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 114776707 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 114776707 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 114776707 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000167 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000167 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000167 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000167 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000167 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000167 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 11959.291989 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 11959.291989 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 11959.291989 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 11959.291989 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 11959.291989 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 11959.291989 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -398,254 +398,254 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # 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number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 17655 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 17655 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 184079500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 184079500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 184079500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 184079500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 184079500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 184079500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000153 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000153 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000153 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000153 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000153 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000153 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 10426.479751 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 10426.479751 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10426.479751 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 10426.479751 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10426.479751 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 10426.479751 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1676 # 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number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 154473000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 154473000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 154473000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 154473000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 154473000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000152 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000152 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000152 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000152 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000152 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000152 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8853.335626 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 8853.335626 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8853.335626 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 8853.335626 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8853.335626 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 8853.335626 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1189180 # number of replacements -system.cpu.dcache.tagsinuse 4054.532653 # Cycle average of tags in use -system.cpu.dcache.total_refs 194989715 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1193276 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 163.407053 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 4672860000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4054.532653 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.989876 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.989876 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 137842002 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 137842002 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 52682481 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 52682481 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 2233095 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 2233095 # number of LoadLockedReq hits +system.cpu.dcache.replacements 1187048 # number of replacements +system.cpu.dcache.tagsinuse 4054.257449 # Cycle average of tags in use +system.cpu.dcache.total_refs 194842504 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1191144 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 163.575944 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 4633717000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4054.257449 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.989809 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.989809 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 137485453 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 137485453 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 52891890 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 52891890 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 2233029 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 2233029 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 2232023 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 2232023 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 190524483 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 190524483 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 190524483 # number of overall hits -system.cpu.dcache.overall_hits::total 190524483 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1271675 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1271675 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1556825 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1556825 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 43 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 43 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2828500 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2828500 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2828500 # number of overall misses -system.cpu.dcache.overall_misses::total 2828500 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 15608550500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 15608550500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 33157971000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 33157971000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 519500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 519500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 48766521500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 48766521500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 48766521500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 48766521500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 139113677 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 139113677 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 190377343 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 190377343 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 190377343 # number of overall hits +system.cpu.dcache.overall_hits::total 190377343 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1221436 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1221436 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1347416 # 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number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 412500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 32772976500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 32772976500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 32772976500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 32772976500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 138706889 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 138706889 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 2233138 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 2233138 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 2233076 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 2233076 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 2232023 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 2232023 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 193352983 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 193352983 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 193352983 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 193352983 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009141 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.009141 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.028703 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.028703 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000019 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000019 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.014629 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.014629 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.014629 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.014629 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12274.009083 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 12274.009083 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21298.457437 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 21298.457437 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12081.395349 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12081.395349 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 17241.124801 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 17241.124801 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 17241.124801 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 17241.124801 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 192946195 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 192946195 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 192946195 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 192946195 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.008806 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.008806 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024842 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.024842 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000021 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000021 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.013314 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.013314 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.013314 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.013314 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 7899.209619 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 7899.209619 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17162.181168 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 17162.181168 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8776.595745 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8776.595745 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 12757.829762 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 12757.829762 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 12757.829762 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 12757.829762 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3198500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 3322000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 556 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 557 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 5752.697842 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 5964.093357 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1103627 # number of writebacks -system.cpu.dcache.writebacks::total 1103627 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 426551 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 426551 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1208619 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1208619 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 43 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 43 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1635170 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1635170 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1635170 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1635170 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 845124 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 845124 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348206 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 348206 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1193330 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1193330 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1193330 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1193330 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4807719000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4807719000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4284226501 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4284226501 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9091945501 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9091945501 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9091945501 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9091945501 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006075 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006075 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006420 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006420 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006172 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006172 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006172 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006172 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 5688.773482 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 5688.773482 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 12303.712460 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 12303.712460 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 7618.970026 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 7618.970026 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 7618.970026 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 7618.970026 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 1101507 # number of writebacks +system.cpu.dcache.writebacks::total 1101507 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 378352 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 378352 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 999317 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 999317 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 47 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 47 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1377669 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1377669 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1377669 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1377669 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 843084 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 843084 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348099 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 348099 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1191183 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1191183 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1191183 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1191183 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3511124500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3511124500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4141906500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4141906500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7653031000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7653031000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7653031000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7653031000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006078 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006078 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006418 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006418 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006174 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006174 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006174 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006174 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 4164.620014 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 4164.620014 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 11898.645213 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 11898.645213 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 6424.731548 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 6424.731548 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 6424.731548 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 6424.731548 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 128816 # number of replacements -system.cpu.l2cache.tagsinuse 26503.825438 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1724855 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 160033 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 10.778121 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 106591903000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 22677.867679 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 308.367342 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 3517.590417 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.692074 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.009411 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.107348 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.808833 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 14164 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 788094 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 802258 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1103627 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1103627 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 50 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 50 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 248556 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 248556 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 14164 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1036650 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1050814 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 14164 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1036650 # number of overall hits -system.cpu.l2cache.overall_hits::total 1050814 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3429 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 53158 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 56587 # number of ReadReq misses +system.cpu.l2cache.replacements 128736 # number of replacements +system.cpu.l2cache.tagsinuse 26456.309379 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1725132 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 159966 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 10.784367 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 105169103500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 22633.637803 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 309.674133 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 3512.997443 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.690724 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.009451 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.107208 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.807382 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 13983 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 789454 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 803437 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1101507 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1101507 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 35 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 35 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 245171 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 245171 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 13983 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1034625 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1048608 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 13983 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1034625 # number of overall hits +system.cpu.l2cache.overall_hits::total 1048608 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3427 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 53077 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 56504 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses::cpu.data 4 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 4 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 103468 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 103468 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3429 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 156626 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 160055 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3429 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 156626 # number of overall misses -system.cpu.l2cache.overall_misses::total 160055 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 121221500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1836597500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1957819000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3546741000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3546741000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 121221500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 5383338500 # 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average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31274.987540 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31303.213542 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32595.203276 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31274.987540 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31303.213542 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt index 3143a40a6..27346e35d 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.720346 # Number of seconds simulated -sim_ticks 720345914000 # Number of ticks simulated -final_tick 720345914000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.717833 # Number of seconds simulated +sim_ticks 717832876000 # Number of ticks simulated +final_tick 717832876000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1112468 # Simulator instruction rate (inst/s) -host_op_rate 1253563 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1586896277 # Simulator tick rate (ticks/s) -host_mem_usage 231144 # Number of bytes of host memory used -host_seconds 453.93 # Real time elapsed on the host +host_inst_rate 1074460 # Simulator instruction rate (inst/s) +host_op_rate 1210735 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1527332222 # Simulator tick rate (ticks/s) +host_mem_usage 237040 # Number of bytes of host memory used +host_seconds 469.99 # Real time elapsed on the host sim_insts 504986853 # Number of instructions simulated sim_ops 569034839 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 178368 # Number of bytes read from this memory @@ -23,17 +23,17 @@ system.physmem.num_reads::cpu.data 150998 # Nu system.physmem.num_reads::total 153785 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 102730 # Number of write requests responded to by this memory system.physmem.num_writes::total 102730 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 247614 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13415599 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13663213 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 247614 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 247614 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 9127171 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 9127171 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 9127171 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 247614 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13415599 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 22790384 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 248481 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13462565 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13711047 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 248481 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 248481 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 9159124 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 9159124 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 9159124 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 248481 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13462565 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 22870170 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,7 +77,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 1440691828 # number of cpu cycles simulated +system.cpu.numCycles 1435665752 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 504986853 # Number of instructions committed @@ -96,18 +96,18 @@ system.cpu.num_mem_refs 182890034 # nu system.cpu.num_load_insts 126029555 # Number of load instructions system.cpu.num_store_insts 56860479 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 1440691828 # Number of busy cycles +system.cpu.num_busy_cycles 1435665752 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 9788 # number of replacements -system.cpu.icache.tagsinuse 983.378720 # Cycle average of tags in use +system.cpu.icache.tagsinuse 982.776891 # Cycle average of tags in use system.cpu.icache.total_refs 516599855 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 11521 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 44839.845066 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 983.378720 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.480165 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.480165 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 982.776891 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.479872 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.479872 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 516599855 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 516599855 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 516599855 # number of demand (read+write) hits @@ -120,12 +120,12 @@ system.cpu.icache.demand_misses::cpu.inst 11521 # n system.cpu.icache.demand_misses::total 11521 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 11521 # number of overall misses system.cpu.icache.overall_misses::total 11521 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 279753000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 279753000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 279753000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 279753000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 279753000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 279753000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 266834000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 266834000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 266834000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 266834000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 266834000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 266834000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 516611376 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 516611376 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 516611376 # number of demand (read+write) accesses @@ -138,12 +138,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24282.006770 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 24282.006770 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 24282.006770 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 24282.006770 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 24282.006770 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 24282.006770 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23160.663137 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 23160.663137 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 23160.663137 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 23160.663137 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 23160.663137 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 23160.663137 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -158,34 +158,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 11521 system.cpu.icache.demand_mshr_misses::total 11521 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 11521 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 11521 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 245190000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 245190000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 245190000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 245190000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 245190000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 245190000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 243792000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 243792000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 243792000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 243792000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 243792000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 243792000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000022 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000022 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21282.006770 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21282.006770 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21282.006770 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 21282.006770 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21282.006770 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 21282.006770 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21160.663137 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21160.663137 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21160.663137 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 21160.663137 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21160.663137 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 21160.663137 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 1134822 # number of replacements -system.cpu.dcache.tagsinuse 4065.381389 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4065.317414 # Cycle average of tags in use system.cpu.dcache.total_refs 179817786 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 1138918 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 157.884752 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 11899663000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4065.381389 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.992525 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.992525 # Average percentage of cache occupancy +system.cpu.dcache.warmup_cycle 11885124000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4065.317414 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.992509 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.992509 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 122957658 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 122957658 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 53883046 # number of WriteReq hits @@ -206,14 +206,14 @@ system.cpu.dcache.demand_misses::cpu.data 1138918 # n system.cpu.dcache.demand_misses::total 1138918 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 1138918 # number of overall misses system.cpu.dcache.overall_misses::total 1138918 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 13181704000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 13181704000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9327564000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9327564000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 22509268000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 22509268000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 22509268000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 22509268000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 12178377000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 12178377000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8970025000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8970025000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 21148402000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 21148402000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 21148402000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 21148402000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 123740316 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 123740316 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) @@ -234,14 +234,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.006399 system.cpu.dcache.demand_miss_rate::total 0.006399 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.006399 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.006399 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16842.227384 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16842.227384 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26181.900859 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 26181.900859 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 19763.730137 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 19763.730137 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 19763.730137 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 19763.730137 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15560.279202 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15560.279202 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25178.310784 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 25178.310784 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 18568.853947 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 18568.853947 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 18568.853947 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 18568.853947 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -260,14 +260,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1138918 system.cpu.dcache.demand_mshr_misses::total 1138918 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1138918 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1138918 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10833730000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10833730000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8258784000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8258784000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19092514000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 19092514000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19092514000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 19092514000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10613061000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10613061000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8257505000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8257505000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18870566000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 18870566000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18870566000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 18870566000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006325 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006325 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006568 # mshr miss rate for WriteReq accesses @@ -276,28 +276,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006399 system.cpu.dcache.demand_mshr_miss_rate::total 0.006399 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006399 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.006399 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13842.227384 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13842.227384 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23181.900859 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23181.900859 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16763.730137 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 16763.730137 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16763.730137 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 16763.730137 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13560.279202 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13560.279202 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23178.310784 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23178.310784 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16568.853947 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 16568.853947 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16568.853947 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 16568.853947 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 122482 # number of replacements -system.cpu.l2cache.tagsinuse 26939.836590 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 26931.505779 # Cycle average of tags in use system.cpu.l2cache.total_refs 1623186 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 153644 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 10.564591 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 344531371000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 23226.765026 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 246.719769 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 3466.351794 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.708825 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.007529 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.105785 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.822139 # Average percentage of cache occupancy +system.cpu.l2cache.warmup_cycle 343812481000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 23220.335885 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 246.652044 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 3464.517849 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.708628 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.007527 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.105729 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.821884 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 8734 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 734961 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 743695 # number of ReadReq hits @@ -322,17 +322,17 @@ system.cpu.l2cache.demand_misses::total 153785 # nu system.cpu.l2cache.overall_misses::cpu.inst 2787 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 150998 # number of overall misses system.cpu.l2cache.overall_misses::total 153785 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 144924000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2480244000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 2625168000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5371652000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5371652000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 144924000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7851896000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 7996820000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 144924000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7851896000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 7996820000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 144931000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2480793000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 2625724000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5371655000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5371655000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 144931000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7852448000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 7997379000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 144931000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7852448000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 7997379000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 11521 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 782658 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 794179 # number of ReadReq accesses(hits+misses) @@ -357,17 +357,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.133675 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.241906 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.132580 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.133675 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52002.511661 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52011.510158 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52011.013390 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.029041 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.029041 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52002.511661 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52003.655678 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52003.634945 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52002.511661 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52003.655678 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52003.634945 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -389,17 +389,17 @@ system.cpu.l2cache.demand_mshr_misses::total 153785 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2787 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 150998 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 153785 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 111480000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1907880000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2019360000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4132040000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4132040000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 111480000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6039920000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6151400000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 111480000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6039920000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6151400000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 111487000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1908429000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2019916000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4132043000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4132043000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 111487000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6040472000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6151959000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 111487000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6040472000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6151959000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.241906 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.060942 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.063568 # mshr miss rate for ReadReq accesses @@ -411,17 +411,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.133675 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.241906 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.132580 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.133675 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40002.511661 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40011.510158 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40011.013390 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.029041 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.029041 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40002.511661 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40003.655678 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40003.634945 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40002.511661 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40003.655678 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40003.634945 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index 6f010c94a..eb9886f3f 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,278 +1,278 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.433409 # Number of seconds simulated -sim_ticks 433408519000 # Number of ticks simulated -final_tick 433408519000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.427481 # Number of seconds simulated +sim_ticks 427481057500 # Number of ticks simulated +final_tick 427481057500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 113614 # Simulator instruction rate (inst/s) -host_op_rate 210085 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 59550946 # Simulator tick rate (ticks/s) -host_mem_usage 266596 # Number of bytes of host memory used -host_seconds 7277.95 # Real time elapsed on the host +host_inst_rate 54913 # Simulator instruction rate (inst/s) +host_op_rate 101540 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 28388930 # Simulator tick rate (ticks/s) +host_mem_usage 267916 # Number of bytes of host memory used +host_seconds 15058.02 # Real time elapsed on the host sim_insts 826877109 # Number of instructions simulated sim_ops 1528988699 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 223616 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 27616960 # Number of bytes read from this memory -system.physmem.bytes_read::total 27840576 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 223616 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 223616 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 20804096 # Number of bytes written to this memory -system.physmem.bytes_written::total 20804096 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3494 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 431515 # Number of read requests responded to by this memory -system.physmem.num_reads::total 435009 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 325064 # Number of write requests responded to by this memory -system.physmem.num_writes::total 325064 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 515947 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 63720390 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 64236338 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 515947 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 515947 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 48001124 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 48001124 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 48001124 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 515947 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 63720390 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 112237462 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 222080 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 27608960 # Number of bytes read from this memory +system.physmem.bytes_read::total 27831040 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 222080 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 222080 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 20798528 # Number of bytes written to this memory +system.physmem.bytes_written::total 20798528 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3470 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 431390 # Number of read requests responded to by this memory +system.physmem.num_reads::total 434860 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 324977 # Number of write requests responded to by this memory +system.physmem.num_writes::total 324977 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 519508 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 64585224 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 65104733 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 519508 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 519508 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 48653683 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 48653683 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 48653683 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 519508 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 64585224 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 113758416 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 866817039 # number of cpu cycles simulated +system.cpu.numCycles 854962116 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 221487081 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 221487081 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 14390308 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 156608955 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 152775295 # Number of BTB hits +system.cpu.BPredUnit.lookups 221542687 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 221542687 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 14424166 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 156350035 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 152734220 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 187015787 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1232613370 # Number of instructions fetch has processed -system.cpu.fetch.Branches 221487081 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 152775295 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 382812407 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 92129156 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 211136743 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 29595 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 290923 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 179403606 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 4116177 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 858776870 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.664123 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.408324 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 186980274 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1231567115 # Number of instructions fetch has processed +system.cpu.fetch.Branches 221542687 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 152734220 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 382634785 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 91865959 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 200356871 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 29611 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 292723 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 179385748 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 4126859 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 847490251 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.698073 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.416409 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 480379655 55.94% 55.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 25485451 2.97% 58.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 28110483 3.27% 62.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 29418527 3.43% 65.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 18947498 2.21% 67.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 25073247 2.92% 70.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 31697541 3.69% 74.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 30731731 3.58% 78.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 188932737 22.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 469274174 55.37% 55.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 25456463 3.00% 58.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 28089429 3.31% 61.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 29452206 3.48% 65.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 18977949 2.24% 67.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 25085896 2.96% 70.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 31632952 3.73% 74.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 30710148 3.62% 77.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 188811034 22.28% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 858776870 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.255518 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.421999 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 243893330 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 168016637 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 325049297 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 44326191 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 77491415 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2234477290 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 77491415 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 277619036 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 38518487 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 15798 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 333479611 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 131652523 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2182901177 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 23899 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 19427368 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 98042792 # Number of times rename has blocked due to LSQ full +system.cpu.fetch.rateDist::total 847490251 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.259126 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.440493 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 242064219 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 159033013 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 325519019 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 43678013 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 77195987 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2233248714 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 77195987 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 275570857 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 34110312 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 14758 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 334015692 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 126582645 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2180982884 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 23384 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 17625674 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 93760649 # Number of times rename has blocked due to LSQ full system.cpu.rename.FullRegisterEvents 161 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2282806171 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5519898710 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 5519661560 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 237150 # Number of floating rename lookups +system.cpu.rename.RenamedOperands 2280809501 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5515289668 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 5515055744 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 233924 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1614040851 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 668765320 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1577 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1532 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 321506074 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 528464573 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 210836617 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 202710665 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 58518610 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2088631495 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 25170 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1835731702 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 979947 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 553767245 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 915534947 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 24617 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 858776870 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.137612 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.891337 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 666768650 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1407 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1265 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 312542490 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 527887651 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 210543369 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 206203596 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 60708248 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2086420498 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 33397 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1834774344 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 951947 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 551393168 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 912351431 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 32844 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 847490251 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.164950 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.897317 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 233191073 27.15% 27.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 144020170 16.77% 43.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 136609479 15.91% 59.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 135995630 15.84% 75.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 99689263 11.61% 87.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 59771994 6.96% 94.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 35471375 4.13% 98.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 12162676 1.42% 99.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1865210 0.22% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 226384740 26.71% 26.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 141456799 16.69% 43.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 133569524 15.76% 59.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 133051620 15.70% 74.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 103773872 12.24% 87.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 59584692 7.03% 94.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 35598450 4.20% 98.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 12150443 1.43% 99.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1920111 0.23% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 858776870 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 847490251 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 5023267 32.65% 32.65% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 32.65% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 32.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 32.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 32.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 32.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.65% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 7736612 50.28% 82.92% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2627522 17.08% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 5020198 29.82% 29.82% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 29.82% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 29.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 29.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 29.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 29.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 29.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 29.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 29.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 29.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 29.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 29.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 29.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 29.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 29.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 29.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 29.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 29.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 29.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 29.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 29.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 29.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 29.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 29.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 29.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 29.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 29.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 29.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 29.82% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9164809 54.44% 84.27% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2648245 15.73% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2697797 0.15% 0.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1210853930 65.96% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 444242795 24.20% 90.31% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 177937180 9.69% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2709053 0.15% 0.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1209921951 65.94% 66.09% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.09% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 66.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.09% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 444260889 24.21% 90.30% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 177882451 9.70% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1835731702 # Type of FU issued -system.cpu.iq.rate 2.117785 # Inst issue rate -system.cpu.iq.fu_busy_cnt 15387401 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.008382 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4546566873 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2642600298 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1793170888 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 40749 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 78738 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 9468 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1848402423 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 18883 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 170058795 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1834774344 # Type of FU issued +system.cpu.iq.rate 2.146030 # Inst issue rate +system.cpu.iq.fu_busy_cnt 16833252 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.009175 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4534784465 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2638023268 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1791909670 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 39673 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 77216 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 9185 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1848880362 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 18181 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 169562147 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 144362417 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 511205 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 267668 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 61676904 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 143785495 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 532532 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 265743 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 61383726 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 10972 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 14 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 10593 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 77491415 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 5069554 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 791692 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2088656665 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 2509040 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 528464573 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 210837089 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5181 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 437341 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 70182 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 267668 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 10030872 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4891333 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 14922205 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1805797916 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 435944125 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 29933786 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 77195987 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 3929046 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 530860 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2086453895 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 2572498 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 527887651 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 210543911 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5247 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 306238 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 13529 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 265743 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 10035586 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4925818 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 14961404 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1804635725 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 435893328 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 30138619 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 608566280 # number of memory reference insts executed -system.cpu.iew.exec_branches 171216670 # Number of branches executed -system.cpu.iew.exec_stores 172622155 # Number of stores executed -system.cpu.iew.exec_rate 2.083252 # Inst execution rate -system.cpu.iew.wb_sent 1800513420 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1793180356 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1362010404 # num instructions producing a value -system.cpu.iew.wb_consumers 1993207324 # num instructions consuming a value +system.cpu.iew.exec_refs 608398138 # number of memory reference insts executed +system.cpu.iew.exec_branches 171115964 # Number of branches executed +system.cpu.iew.exec_stores 172504810 # Number of stores executed +system.cpu.iew.exec_rate 2.110779 # Inst execution rate +system.cpu.iew.wb_sent 1799306282 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1791918855 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1361399176 # num instructions producing a value +system.cpu.iew.wb_consumers 1998222448 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.068695 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.683326 # average fanout of values written-back +system.cpu.iew.wb_rate 2.095904 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.681305 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 559701427 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 557495358 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 553 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 14419517 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 781285455 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.957017 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.446096 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 14453256 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 770294264 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.984941 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.459206 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 285259296 36.51% 36.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 196991997 25.21% 61.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 62815706 8.04% 69.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 91733389 11.74% 81.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 26919948 3.45% 84.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 29020227 3.71% 88.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 9830313 1.26% 89.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10314314 1.32% 91.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 68400265 8.75% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 276893916 35.95% 35.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 195328257 25.36% 61.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 61767064 8.02% 69.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 90267747 11.72% 81.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 27669896 3.59% 84.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 28983308 3.76% 88.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 10477535 1.36% 89.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10390589 1.35% 91.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 68515952 8.89% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 781285455 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 770294264 # Number of insts commited each cycle system.cpu.commit.committedInsts 826877109 # Number of instructions committed system.cpu.commit.committedOps 1528988699 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -283,69 +283,69 @@ system.cpu.commit.branches 149758583 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 1528317557 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 68400265 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 68515952 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2801575316 # The number of ROB reads -system.cpu.rob.rob_writes 4255093941 # The number of ROB writes -system.cpu.timesIdled 198389 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 8040169 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2788262369 # The number of ROB reads +system.cpu.rob.rob_writes 4250388650 # The number of ROB writes +system.cpu.timesIdled 191112 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7471865 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826877109 # Number of Instructions Simulated system.cpu.committedOps 1528988699 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 826877109 # Number of Instructions Simulated -system.cpu.cpi 1.048302 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.048302 # CPI: Total CPI of All Threads -system.cpu.ipc 0.953923 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.953923 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3391505058 # number of integer regfile reads -system.cpu.int_regfile_writes 1872959305 # number of integer regfile writes -system.cpu.fp_regfile_reads 9467 # number of floating regfile reads -system.cpu.fp_regfile_writes 1 # number of floating regfile writes -system.cpu.misc_regfile_reads 993321385 # number of misc regfile reads -system.cpu.icache.replacements 5754 # number of replacements -system.cpu.icache.tagsinuse 1042.434990 # Cycle average of tags in use -system.cpu.icache.total_refs 179199016 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 7367 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 24324.557622 # Average number of references to valid blocks. +system.cpu.cpi 1.033965 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.033965 # CPI: Total CPI of All Threads +system.cpu.ipc 0.967151 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.967151 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3390266607 # number of integer regfile reads +system.cpu.int_regfile_writes 1871785238 # number of integer regfile writes +system.cpu.fp_regfile_reads 9183 # number of floating regfile reads +system.cpu.fp_regfile_writes 2 # number of floating regfile writes +system.cpu.misc_regfile_reads 992828832 # number of misc regfile reads +system.cpu.icache.replacements 5688 # number of replacements +system.cpu.icache.tagsinuse 1035.102627 # Cycle average of tags in use +system.cpu.icache.total_refs 179169407 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 7297 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 24553.845005 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1042.434990 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.509001 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.509001 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 179215714 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 179215714 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 179215714 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 179215714 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 179215714 # number of overall hits -system.cpu.icache.overall_hits::total 179215714 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 187892 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 187892 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 187892 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 187892 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 187892 # number of overall misses -system.cpu.icache.overall_misses::total 187892 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1425771000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1425771000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1425771000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1425771000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1425771000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1425771000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 179403606 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 179403606 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 179403606 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 179403606 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 179403606 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 179403606 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001047 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.001047 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.001047 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.001047 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.001047 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.001047 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 7588.247504 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 7588.247504 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 7588.247504 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 7588.247504 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 7588.247504 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 7588.247504 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1035.102627 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.505421 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.505421 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 179186003 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 179186003 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 179186003 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 179186003 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 179186003 # number of overall hits +system.cpu.icache.overall_hits::total 179186003 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 199745 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 199745 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 199745 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 199745 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 199745 # number of overall misses +system.cpu.icache.overall_misses::total 199745 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1237682000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1237682000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1237682000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1237682000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1237682000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1237682000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 179385748 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 179385748 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 179385748 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 179385748 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 179385748 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 179385748 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001113 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.001113 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.001113 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.001113 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.001113 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.001113 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6196.310296 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 6196.310296 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 6196.310296 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 6196.310296 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 6196.310296 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 6196.310296 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -354,94 +354,94 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1602 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1602 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1602 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1602 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1602 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1602 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 186290 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 186290 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 186290 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 186290 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 186290 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 186290 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 789947000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 789947000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 789947000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 789947000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 789947000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 789947000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001038 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001038 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001038 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.001038 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001038 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.001038 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4240.415481 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4240.415481 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4240.415481 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 4240.415481 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4240.415481 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 4240.415481 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1573 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1573 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1573 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1573 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1573 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1573 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 198172 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 198172 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 198172 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 198172 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 198172 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 198172 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 804804500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 804804500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 804804500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 804804500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 804804500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 804804500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001105 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001105 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001105 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.001105 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001105 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.001105 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4061.141332 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4061.141332 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4061.141332 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 4061.141332 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4061.141332 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 4061.141332 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 2529214 # number of replacements -system.cpu.dcache.tagsinuse 4087.821968 # Cycle average of tags in use -system.cpu.dcache.total_refs 410284602 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2533310 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 161.955940 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 1779749000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4087.821968 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.998003 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.998003 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 261560100 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 261560100 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148207018 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148207018 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 409767118 # 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number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 17736374000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 17736374000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 53391126000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 53391126000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 53391126000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 53391126000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 264320137 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 264320137 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 2529003 # number of replacements +system.cpu.dcache.tagsinuse 4087.729607 # Cycle average of tags in use +system.cpu.dcache.total_refs 410749337 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2533099 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 162.152895 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 1774400000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4087.729607 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.997981 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.997981 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 261990574 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 261990574 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148196003 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148196003 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 410186577 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 410186577 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 410186577 # 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number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 46853107500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 46853107500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 46853107500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 46853107500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 264751521 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 264751521 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149160201 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 149160201 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 413480338 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 413480338 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 413480338 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 413480338 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010442 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.010442 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006390 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.006390 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.008980 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.008980 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.008980 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.008980 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12918.215227 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 12918.215227 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 18607.522375 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 18607.522375 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14378.659492 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14378.659492 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14378.659492 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14378.659492 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 413911722 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 413911722 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 413911722 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 413911722 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010428 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.010428 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006464 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.006464 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.009000 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009000 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009000 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009000 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 10827.054087 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 10827.054087 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17589.940033 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 17589.940033 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 12577.525841 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 12577.525841 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 12577.525841 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 12577.525841 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -450,144 +450,144 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2304349 # number of writebacks -system.cpu.dcache.writebacks::total 2304349 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 997818 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 997818 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3197 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3197 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1001015 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1001015 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1001015 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1001015 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762219 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1762219 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 949986 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 949986 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2712205 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2712205 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2712205 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2712205 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12599150566 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 12599150566 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14683018004 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 14683018004 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27282168570 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 27282168570 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27282168570 # 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average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15456.036198 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15456.036198 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10059.036308 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 10059.036308 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10059.036308 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 10059.036308 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 2304289 # number of writebacks +system.cpu.dcache.writebacks::total 2304289 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 998325 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 998325 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2874 # 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Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 441022 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 8.189918 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 209697302000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 21100.579663 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 146.976593 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 8058.630796 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.643939 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.004485 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.245930 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.894354 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 3776 # 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average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -596,60 +596,60 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 325064 # number of writebacks -system.cpu.l2cache.writebacks::total 325064 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3494 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 222289 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 225783 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 177436 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 177436 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 209266 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 209266 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3494 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 431555 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 435049 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3494 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 431555 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 435049 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 111572500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6940846499 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7052418999 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 5502498500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 5502498500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6489948500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6489948500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 111572500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 13430794999 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 13542367499 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 111572500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 13430794999 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 13542367499 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.477518 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.126204 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.127657 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991855 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991855 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.271084 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.271084 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.477518 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.170352 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.171237 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.477518 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.170352 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.171237 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31932.598741 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31224.426305 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31235.385299 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31011.173043 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31011.173043 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31012.914186 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31012.914186 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31932.598741 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31121.861638 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31128.372894 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31932.598741 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31121.861638 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31128.372894 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 324977 # number of writebacks +system.cpu.l2cache.writebacks::total 324977 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3470 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 222202 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 225672 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 189416 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 189416 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 209218 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 209218 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3470 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 431420 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 434890 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3470 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 431420 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 434890 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 111424500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6957189466 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7068613966 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 5872774499 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 5872774499 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6488320000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6488320000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 111424500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 13445509466 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 13556933966 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 111424500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 13445509466 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 13556933966 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.478885 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.126143 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.127588 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.992512 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.992512 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.271152 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.271152 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.478885 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.170313 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.171193 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.478885 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.170313 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.171193 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32110.806916 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31310.201825 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31322.512168 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31004.637934 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31004.637934 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31012.245600 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31012.245600 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32110.806916 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31165.707352 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31173.248329 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32110.806916 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31165.707352 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31173.248329 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt index 20a253054..3dab46390 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.652607 # Number of seconds simulated -sim_ticks 1652606827000 # Number of ticks simulated -final_tick 1652606827000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.649901 # Number of seconds simulated +sim_ticks 1649900881000 # Number of ticks simulated +final_tick 1649900881000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 548890 # Simulator instruction rate (inst/s) -host_op_rate 1014960 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1097019218 # Simulator tick rate (ticks/s) -host_mem_usage 278012 # Number of bytes of host memory used -host_seconds 1506.45 # Real time elapsed on the host +host_inst_rate 669860 # Simulator instruction rate (inst/s) +host_op_rate 1238647 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1336598464 # Simulator tick rate (ticks/s) +host_mem_usage 232964 # Number of bytes of host memory used +host_seconds 1234.40 # Real time elapsed on the host sim_insts 826877110 # Number of instructions simulated sim_ops 1528988700 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 123584 # Number of bytes read from this memory @@ -23,19 +23,19 @@ system.physmem.num_reads::cpu.data 427498 # Nu system.physmem.num_reads::total 429429 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 323570 # Number of write requests responded to by this memory system.physmem.num_writes::total 323570 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 74781 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 16555585 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 16630366 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 74781 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 74781 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 12530797 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 12530797 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 12530797 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 74781 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 16555585 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 29161162 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 74904 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 16582737 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 16657641 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 74904 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 74904 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 12551348 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 12551348 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 12551348 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 74904 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 16582737 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 29208989 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 3305213654 # number of cpu cycles simulated +system.cpu.numCycles 3299801762 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 826877110 # Number of instructions committed @@ -54,18 +54,18 @@ system.cpu.num_mem_refs 533262341 # nu system.cpu.num_load_insts 384102156 # Number of load instructions system.cpu.num_store_insts 149160185 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 3305213654 # Number of busy cycles +system.cpu.num_busy_cycles 3299801762 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 1253 # number of replacements -system.cpu.icache.tagsinuse 881.608211 # Cycle average of tags in use +system.cpu.icache.tagsinuse 881.283724 # Cycle average of tags in use system.cpu.icache.total_refs 1068344252 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 2814 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 379653.252310 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 881.608211 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.430473 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.430473 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 881.283724 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.430314 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.430314 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1068344252 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1068344252 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1068344252 # number of demand (read+write) hits @@ -78,12 +78,12 @@ system.cpu.icache.demand_misses::cpu.inst 2814 # n system.cpu.icache.demand_misses::total 2814 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 2814 # number of overall misses system.cpu.icache.overall_misses::total 2814 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 120792000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 120792000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 120792000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 120792000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 120792000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 120792000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 117690500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 117690500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 117690500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 117690500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 117690500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 117690500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1068347066 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1068347066 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1068347066 # number of demand (read+write) accesses @@ -96,12 +96,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000003 system.cpu.icache.demand_miss_rate::total 0.000003 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000003 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000003 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42925.373134 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 42925.373134 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 42925.373134 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 42925.373134 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 42925.373134 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 42925.373134 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41823.205402 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 41823.205402 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 41823.205402 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 41823.205402 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 41823.205402 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 41823.205402 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -116,34 +116,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 2814 system.cpu.icache.demand_mshr_misses::total 2814 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 2814 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 2814 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 112350000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 112350000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 112350000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 112350000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 112350000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 112350000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 112062500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 112062500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 112062500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 112062500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 112062500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 112062500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39925.373134 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39925.373134 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39925.373134 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 39925.373134 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39925.373134 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 39925.373134 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39823.205402 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39823.205402 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39823.205402 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 39823.205402 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39823.205402 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 39823.205402 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 2514362 # number of replacements -system.cpu.dcache.tagsinuse 4086.432071 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4086.427569 # Cycle average of tags in use system.cpu.dcache.total_refs 530743928 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 2518458 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 210.741624 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 8218649000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4086.432071 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.997664 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.997664 # Average percentage of cache occupancy +system.cpu.dcache.warmup_cycle 8211722000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4086.427569 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.997663 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.997663 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 382374771 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 382374771 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 148369157 # number of WriteReq hits @@ -160,14 +160,14 @@ system.cpu.dcache.demand_misses::cpu.data 2518458 # n system.cpu.dcache.demand_misses::total 2518458 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 2518458 # number of overall misses system.cpu.dcache.overall_misses::total 2518458 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 33364275000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 33364275000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 19892603500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 19892603500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 53256878500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 53256878500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 53256878500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 53256878500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 31594062000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 31594062000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 19100972000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 19100972000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 50695034000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 50695034000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 50695034000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 50695034000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 384102185 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 384102185 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149160201 # number of WriteReq accesses(hits+misses) @@ -184,14 +184,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.004723 system.cpu.dcache.demand_miss_rate::total 0.004723 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.004723 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.004723 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19314.579481 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 19314.579481 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25147.278154 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 25147.278154 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 21146.621663 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 21146.621663 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 21146.621663 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 21146.621663 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18289.803139 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 18289.803139 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24146.535465 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 24146.535465 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 20129.394256 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 20129.394256 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 20129.394256 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 20129.394256 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -210,14 +210,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2518458 system.cpu.dcache.demand_mshr_misses::total 2518458 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2518458 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2518458 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 28182031000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 28182031000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17519463000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 17519463000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 45701494000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 45701494000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 45701494000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 45701494000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 28139234000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 28139234000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17518884000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 17518884000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 45658118000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 45658118000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 45658118000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 45658118000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004497 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004497 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005303 # mshr miss rate for WriteReq accesses @@ -226,28 +226,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.004723 system.cpu.dcache.demand_mshr_miss_rate::total 0.004723 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.004723 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16314.578323 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16314.578323 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22147.267409 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22147.267409 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18146.617494 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 18146.617494 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18146.617494 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 18146.617494 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16289.803139 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16289.803139 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22146.535465 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22146.535465 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18129.394256 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 18129.394256 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18129.394256 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 18129.394256 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 403150 # number of replacements -system.cpu.l2cache.tagsinuse 29113.385897 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 29110.547277 # Cycle average of tags in use system.cpu.l2cache.total_refs 3572765 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 435501 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 8.203804 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 773011482000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 21035.861795 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 79.696350 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 7997.827752 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.641964 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.002432 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.244074 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.888470 # Average percentage of cache occupancy +system.cpu.l2cache.warmup_cycle 772497646000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 21034.967888 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 79.712550 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 7995.866840 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.641936 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.002433 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.244014 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.888383 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 883 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1509854 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1510737 # number of ReadReq hits @@ -272,17 +272,17 @@ system.cpu.l2cache.demand_misses::total 429429 # nu system.cpu.l2cache.overall_misses::cpu.inst 1931 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 427498 # number of overall misses system.cpu.l2cache.overall_misses::total 429429 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 100412000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11313120000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 11413532000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10916779000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 10916779000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 100412000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 22229899000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 22330311000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 100412000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 22229899000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 22330311000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 100418500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11313280000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 11413698500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10916780000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 10916780000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 100418500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 22230060000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 22330478500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 100418500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 22230060000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 22330478500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 2814 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 1727414 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 1730228 # number of ReadReq accesses(hits+misses) @@ -307,17 +307,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.170322 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.686212 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.169746 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.170322 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.014290 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.014290 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.007018 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000.006986 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.007018 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000.006986 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52003.366132 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000.735429 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000.758573 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.019053 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.019053 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52003.366132 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.383628 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000.397039 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52003.366132 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.383628 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000.397039 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -339,17 +339,17 @@ system.cpu.l2cache.demand_mshr_misses::total 429429 system.cpu.l2cache.overall_mshr_misses::cpu.inst 1931 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 427498 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 429429 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 77240000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8702400000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8779640000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 77246000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8702551000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8779797000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8397520000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8397520000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 77240000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 17099920000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 17177160000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 77240000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 17099920000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 17177160000 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 77246000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 17100071000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17177317000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 77246000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 17100071000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17177317000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.686212 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.125945 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.126857 # mshr miss rate for ReadReq accesses @@ -361,17 +361,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.170322 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.686212 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.169746 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.170322 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40003.107198 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000.694061 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.715291 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40003.107198 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.353218 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.365602 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40003.107198 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.353218 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.365602 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |