diff options
Diffstat (limited to 'tests/long/se/20.parser')
13 files changed, 1358 insertions, 1357 deletions
diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini index 5e05f1621..79d4aa555 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini @@ -497,7 +497,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port @@ -529,7 +529,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr index 374965c0a..b4d96e4ea 100755 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr @@ -1,4 +1,3 @@ warn: Sockets disabled, not accepting gdb connections warn: CP14 unimplemented crn[8], opc1[2], crm[9], opc2[4] -warn: CP14 unimplemented crn[15], opc1[7], crm[5], opc2[7] hack: be nice to actually delete the event here diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout index 5a5a625da..19d21974e 100755 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:10:14 -gem5 started Jun 29 2012 00:45:14 +gem5 compiled Jul 2 2012 09:08:16 +gem5 started Jul 2 2012 15:42:24 gem5 executing on zizzer command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/20.parser/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -67,4 +67,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 210036334500 because target called exit() +Exiting @ tick 213265939500 because target called exit() diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index 43f7dedd0..e448a6379 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.210036 # Number of seconds simulated -sim_ticks 210036334500 # Number of ticks simulated -final_tick 210036334500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.213266 # Number of seconds simulated +sim_ticks 213265939500 # Number of ticks simulated +final_tick 213265939500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 177312 # Simulator instruction rate (inst/s) -host_op_rate 199743 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 73173320 # Simulator tick rate (ticks/s) -host_mem_usage 239056 # Number of bytes of host memory used -host_seconds 2870.40 # Real time elapsed on the host -sim_insts 508955243 # Number of instructions simulated -sim_ops 573341803 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 219136 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10020416 # Number of bytes read from this memory -system.physmem.bytes_read::total 10239552 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 219136 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 219136 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6682560 # Number of bytes written to this memory -system.physmem.bytes_written::total 6682560 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3424 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 156569 # Number of read requests responded to by this memory -system.physmem.num_reads::total 159993 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 104415 # Number of write requests responded to by this memory -system.physmem.num_writes::total 104415 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1043324 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 47708012 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 48751336 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1043324 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1043324 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 31816209 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 31816209 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 31816209 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1043324 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 47708012 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 80567546 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 150954 # Simulator instruction rate (inst/s) +host_op_rate 170051 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 63253971 # Simulator tick rate (ticks/s) +host_mem_usage 238980 # Number of bytes of host memory used +host_seconds 3371.58 # Real time elapsed on the host +sim_insts 508955143 # Number of instructions simulated +sim_ops 573341703 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 218944 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10016576 # Number of bytes read from this memory +system.physmem.bytes_read::total 10235520 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 218944 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 218944 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6679616 # Number of bytes written to this memory +system.physmem.bytes_written::total 6679616 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3421 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 156509 # Number of read requests responded to by this memory +system.physmem.num_reads::total 159930 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 104369 # Number of write requests responded to by this memory +system.physmem.num_writes::total 104369 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 1026624 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 46967537 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 47994162 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1026624 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1026624 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 31320594 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 31320594 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 31320594 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1026624 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 46967537 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 79314756 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,143 +77,143 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 420072670 # number of cpu cycles simulated +system.cpu.numCycles 426531880 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 180017694 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 142687184 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 7729396 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 94339767 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 87293897 # Number of BTB hits +system.cpu.BPredUnit.lookups 180717428 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 143299693 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 7745708 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 94822680 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 87599174 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 12415335 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 116774 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 120382403 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 794428106 # Number of instructions fetch has processed -system.cpu.fetch.Branches 180017694 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 99709232 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 176656328 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 41234330 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 91071148 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 14 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 358 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 113830042 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2509224 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 418577617 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.181681 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.031530 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 12446842 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 117258 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 120998369 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 797263404 # Number of instructions fetch has processed +system.cpu.fetch.Branches 180717428 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 100046016 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 177300353 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 41685655 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 95764916 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 19 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 750 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 114346660 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2503858 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 424958022 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.156047 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.022518 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 241934136 57.80% 57.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 14312407 3.42% 61.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 20602450 4.92% 66.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 22857238 5.46% 71.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 20951996 5.01% 76.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 13135363 3.14% 79.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 13267726 3.17% 82.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 12107850 2.89% 85.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 59408451 14.19% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 247670464 58.28% 58.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 14397332 3.39% 61.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 20689751 4.87% 66.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 22947722 5.40% 71.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 21025298 4.95% 76.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 13188609 3.10% 79.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 13288793 3.13% 83.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 12167829 2.86% 85.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 59582224 14.02% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 418577617 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.428539 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.891168 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 132749600 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 85626153 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 165029361 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 4780262 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 30392241 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 26480489 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 78151 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 870641905 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 312699 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 30392241 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 142822329 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 6003622 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 66002577 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 159587024 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 13769824 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 815822534 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 858 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2869085 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 7326440 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 62 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 963278183 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3562240909 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3562236360 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 4549 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 672200323 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 291077860 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 5318003 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 5317721 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 67395600 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 171954811 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 74969765 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 27370082 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 14835909 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 760687253 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 6768595 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 671184661 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1545827 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 191893024 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 487573539 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 3047459 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 418577617 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.603489 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.725201 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 424958022 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.423690 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.869177 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 133827033 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 89884158 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 165222726 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 5205901 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 30818204 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 26548087 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 78411 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 873467434 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 311843 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 30818204 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 144286364 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 8884116 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 66224882 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 159795223 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 14949233 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 818684887 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1541 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2838925 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 8204276 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 192 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 966602186 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3574693177 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3574688542 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 4635 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 672200163 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 294402023 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 5323897 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 5323528 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 70458787 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 172688867 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 75177672 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 27536611 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 15452316 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 763600148 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 6775253 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 672568642 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1541380 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 194741611 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 494202077 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 3054137 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 424958022 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.582671 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.715070 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 157194444 37.55% 37.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 77339610 18.48% 56.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 70514833 16.85% 72.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 51630225 12.33% 85.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 31661646 7.56% 92.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 16095104 3.85% 96.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 9461042 2.26% 98.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3409350 0.81% 99.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1271363 0.30% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 161198015 37.93% 37.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 79163376 18.63% 56.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 71154341 16.74% 73.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 52720722 12.41% 85.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 30628875 7.21% 92.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 16032619 3.77% 96.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 9417662 2.22% 98.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3389445 0.80% 99.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1252967 0.29% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 418577617 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 424958022 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 446687 4.54% 4.54% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.54% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.54% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.54% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.54% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.54% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.54% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.54% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.54% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 6731982 68.43% 72.97% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2658540 27.03% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 469414 4.82% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 6674941 68.55% 73.37% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2592845 26.63% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 450868550 67.18% 67.18% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 385779 0.06% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 451773589 67.17% 67.17% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 385931 0.06% 67.23% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 220 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 236 0.00% 67.23% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.23% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.23% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.23% # Type of FU issued @@ -239,159 +239,159 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.23% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.23% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.23% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 154882510 23.08% 90.31% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 65047599 9.69% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 155280491 23.09% 90.32% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 65128392 9.68% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 671184661 # Type of FU issued -system.cpu.iq.rate 1.597782 # Inst issue rate -system.cpu.iq.fu_busy_cnt 9837209 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014656 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1772329499 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 960150284 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 650772394 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 476 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 942 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 672568642 # Type of FU issued +system.cpu.iq.rate 1.576831 # Inst issue rate +system.cpu.iq.fu_busy_cnt 9737200 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014478 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1781373379 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 965920498 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 652179695 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 507 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 988 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 681021630 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 240 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 8403522 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 682305587 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 255 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 8455481 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 45181752 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 43422 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 806126 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 17365784 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 45915828 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 43410 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 808399 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 17573711 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 19422 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1337 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 19491 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1190 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 30392241 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2471437 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 146089 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 773606723 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1210159 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 171954811 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 74969765 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5279868 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 67842 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 6482 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 806126 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4698240 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 6420025 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 11118265 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 661214126 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 151365480 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 9970535 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 30818204 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 4164130 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 269264 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 776544403 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1215899 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 172688867 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 75177672 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5286544 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 138154 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 7994 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 808399 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4709852 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 6436476 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 11146328 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 662608710 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 151741633 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 9959932 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 6150875 # number of nop insts executed -system.cpu.iew.exec_refs 214988835 # number of memory reference insts executed -system.cpu.iew.exec_branches 137027568 # Number of branches executed -system.cpu.iew.exec_stores 63623355 # Number of stores executed -system.cpu.iew.exec_rate 1.574047 # Inst execution rate -system.cpu.iew.wb_sent 655977937 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 650772410 # cumulative count of insts written-back -system.cpu.iew.wb_producers 374973371 # num instructions producing a value -system.cpu.iew.wb_consumers 645025945 # num instructions consuming a value +system.cpu.iew.exec_nop 6169002 # number of nop insts executed +system.cpu.iew.exec_refs 215464084 # number of memory reference insts executed +system.cpu.iew.exec_branches 137322673 # Number of branches executed +system.cpu.iew.exec_stores 63722451 # Number of stores executed +system.cpu.iew.exec_rate 1.553480 # Inst execution rate +system.cpu.iew.wb_sent 657371500 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 652179711 # cumulative count of insts written-back +system.cpu.iew.wb_producers 375708324 # num instructions producing a value +system.cpu.iew.wb_consumers 644520569 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.549190 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.581331 # average fanout of values written-back +system.cpu.iew.wb_rate 1.529029 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.582927 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 510299127 # The number of committed instructions -system.cpu.commit.commitCommittedOps 574685687 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 198937259 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 3721136 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 9897053 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 388185377 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.480441 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.160280 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 510299027 # The number of committed instructions +system.cpu.commit.commitCommittedOps 574685587 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 201878689 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 3721116 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 9919991 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 394139819 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.458075 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.151494 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 174260848 44.89% 44.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 102323189 26.36% 71.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 36274304 9.34% 80.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 18231179 4.70% 85.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 17368323 4.47% 89.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 8208578 2.11% 91.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 6882791 1.77% 93.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3781895 0.97% 94.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 20854270 5.37% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 179649221 45.58% 45.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 103014328 26.14% 71.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 36282541 9.21% 80.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 18903013 4.80% 85.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 16466891 4.18% 89.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 8169845 2.07% 91.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 6904317 1.75% 93.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3742857 0.95% 94.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 21006806 5.33% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 388185377 # Number of insts commited each cycle -system.cpu.commit.committedInsts 510299127 # Number of instructions committed -system.cpu.commit.committedOps 574685687 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 394139819 # Number of insts commited each cycle +system.cpu.commit.committedInsts 510299027 # Number of instructions committed +system.cpu.commit.committedOps 574685587 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 184377040 # Number of memory references committed -system.cpu.commit.loads 126773059 # Number of loads committed +system.cpu.commit.refs 184377000 # Number of memory references committed +system.cpu.commit.loads 126773039 # Number of loads committed system.cpu.commit.membars 1488542 # Number of memory barriers committed -system.cpu.commit.branches 120192244 # Number of branches committed +system.cpu.commit.branches 120192224 # Number of branches committed system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. -system.cpu.commit.int_insts 473701709 # Number of committed integer instructions. +system.cpu.commit.int_insts 473701629 # Number of committed integer instructions. system.cpu.commit.function_calls 9757362 # Number of function calls committed. -system.cpu.commit.bw_lim_events 20854270 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 21006806 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1140946915 # The number of ROB reads -system.cpu.rob.rob_writes 1577778936 # The number of ROB writes -system.cpu.timesIdled 55077 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 1495053 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 508955243 # Number of Instructions Simulated -system.cpu.committedOps 573341803 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 508955243 # Number of Instructions Simulated -system.cpu.cpi 0.825363 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.825363 # CPI: Total CPI of All Threads -system.cpu.ipc 1.211589 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.211589 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3085576786 # number of integer regfile reads -system.cpu.int_regfile_writes 758984284 # number of integer regfile writes +system.cpu.rob.rob_reads 1149690151 # The number of ROB reads +system.cpu.rob.rob_writes 1584089992 # The number of ROB writes +system.cpu.timesIdled 76999 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 1573858 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 508955143 # Number of Instructions Simulated +system.cpu.committedOps 573341703 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 508955143 # Number of Instructions Simulated +system.cpu.cpi 0.838054 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.838054 # CPI: Total CPI of All Threads +system.cpu.ipc 1.193241 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.193241 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3092178369 # number of integer regfile reads +system.cpu.int_regfile_writes 760489659 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 1021861854 # number of misc regfile reads -system.cpu.misc_regfile_writes 4464092 # number of misc regfile writes -system.cpu.icache.replacements 15860 # number of replacements -system.cpu.icache.tagsinuse 1099.172767 # Cycle average of tags in use -system.cpu.icache.total_refs 113810641 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 17722 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 6421.997574 # Average number of references to valid blocks. +system.cpu.misc_regfile_reads 1025175182 # number of misc regfile reads +system.cpu.misc_regfile_writes 4464052 # number of misc regfile writes +system.cpu.icache.replacements 15943 # number of replacements +system.cpu.icache.tagsinuse 1097.454054 # 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number of overall hits -system.cpu.icache.overall_hits::total 113810641 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 19401 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 19401 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 19401 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 19401 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 19401 # number of overall misses -system.cpu.icache.overall_misses::total 19401 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 248637000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 248637000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 248637000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 248637000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 248637000 # 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Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 114326971 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 114326971 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 114326971 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 114326971 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 114326971 # number of overall hits +system.cpu.icache.overall_hits::total 114326971 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 19689 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 19689 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 19689 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 19689 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 19689 # number of overall misses +system.cpu.icache.overall_misses::total 19689 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 281738500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 281738500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 281738500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 281738500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 281738500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 281738500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 114346660 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 114346660 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 114346660 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 114346660 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 114346660 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 114346660 # 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average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14309.436741 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -400,254 +400,256 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1635 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1635 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1635 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1635 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1635 # 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number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 157002000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 157002000 # number of overall MSHR miss cycles +system.cpu.icache.writebacks::writebacks 1 # number of writebacks +system.cpu.icache.writebacks::total 1 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1829 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1829 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1829 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1829 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1829 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1829 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 17860 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 17860 # 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average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 8837.217156 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 10343.952968 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 10343.952968 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10343.952968 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 10343.952968 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10343.952968 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 10343.952968 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1187572 # number of replacements -system.cpu.dcache.tagsinuse 4054.018588 # Cycle average of tags in use -system.cpu.dcache.total_refs 194536167 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1191668 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 163.246950 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 4842467000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4054.018588 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.989751 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.989751 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 137268360 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 137268360 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 52802735 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 52802735 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 2232908 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 2232908 # 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number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 2232952 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 2232952 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 2232045 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 2232045 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 192769177 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 192769177 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 192769177 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 192769177 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009106 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.009106 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.026486 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.026486 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000020 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000020 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.013996 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.013996 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.013996 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.013996 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 8872.951167 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 8872.951167 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17001.313893 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 17001.313893 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9784.090909 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9784.090909 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 13200.829330 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 13200.829330 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 13200.829330 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 13200.829330 # average overall miss latency +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 2232903 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 2232903 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 2232025 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 2232025 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 193089953 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 193089953 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 193089953 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 193089953 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009124 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.009124 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.028683 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.028683 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000018 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000018 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.014618 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.014618 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.014618 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.014618 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12268.035923 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 12268.035923 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21278.153551 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 21278.153551 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12597.560976 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12597.560976 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 17234.088115 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 17234.088115 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 17234.088115 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 17234.088115 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3248500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 3299000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 559 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 5811.270125 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 5901.610018 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1101877 # number of writebacks -system.cpu.dcache.writebacks::total 1101877 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 417972 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 417972 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1088398 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1088398 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 44 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 44 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1506370 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1506370 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1506370 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1506370 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 843539 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 843539 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348173 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 348173 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1191712 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1191712 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1191712 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1191712 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3801302500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3801302500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4208028500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4208028500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8009331000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8009331000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8009331000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8009331000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006089 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006089 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 1102764 # number of writebacks +system.cpu.dcache.writebacks::total 1102764 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 422570 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 422570 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1207611 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1207611 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 41 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 41 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1630181 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1630181 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1630181 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1630181 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 844346 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 844346 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348143 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 348143 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1192489 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1192489 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1192489 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1192489 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4793812500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4793812500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4284005501 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4284005501 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9077818001 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9077818001 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9077818001 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9077818001 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006081 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006081 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006419 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006419 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006182 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006182 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006182 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006182 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 4506.374335 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 4506.374335 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 12086.027636 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 12086.027636 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 6720.861248 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 6720.861248 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 6720.861248 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 6720.861248 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006176 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006176 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006176 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006176 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 5677.545106 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 5677.545106 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 12305.304145 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 12305.304145 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 7612.496217 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 7612.496217 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 7612.496217 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 7612.496217 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 128814 # number of replacements -system.cpu.l2cache.tagsinuse 26521.071882 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1726136 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 160049 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 10.785047 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 108383253000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 22699.952079 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 308.453582 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 3512.666221 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.692748 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.009413 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.107198 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.809359 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 14292 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 789500 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 803792 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1101877 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1101877 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 38 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 38 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 245577 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 245577 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 14292 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1035077 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1049369 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 14292 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1035077 # number of overall hits -system.cpu.l2cache.overall_hits::total 1049369 # number of overall hits +system.cpu.l2cache.replacements 128738 # number of replacements +system.cpu.l2cache.tagsinuse 26549.866286 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1724393 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 159968 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 10.779612 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 109550112000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 22721.325025 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 308.211644 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 3520.329617 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.693400 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.009406 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.107432 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.810238 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 14375 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 787281 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 801656 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1102765 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1102765 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 44 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 44 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 248622 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 248622 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 14375 # 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number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 117618500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1820625500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1938244000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3542483500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3542483500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 117618500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 5363109000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 5480727500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 117618500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 5363109000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 5480727500 # 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mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.132149 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.192159 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.131253 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.132149 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32221.572640 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31395.211331 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31445.297828 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31005.670173 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31005.670173 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31105.724299 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31026.556812 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31028.251059 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31105.724299 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31026.556812 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31028.251059 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31047.864990 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31047.864990 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32221.572640 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31165.535749 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31188.124879 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32221.572640 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31165.535749 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31188.124879 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini index 6a9499ace..ffe909bf7 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini @@ -166,7 +166,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port @@ -198,7 +198,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout b/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout index 64f0d2855..384283516 100755 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:10:14 -gem5 started Jun 29 2012 00:48:24 +gem5 compiled Jul 2 2012 09:08:16 +gem5 started Jul 2 2012 15:48:14 gem5 executing on zizzer command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second @@ -67,4 +67,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 718982756000 because target called exit() +Exiting @ tick 720345914000 because target called exit() diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt index 8439efddd..b8350e4f6 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.718983 # Number of seconds simulated -sim_ticks 718982756000 # Number of ticks simulated -final_tick 718982756000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.720346 # Number of seconds simulated +sim_ticks 720345914000 # Number of ticks simulated +final_tick 720345914000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1474104 # Simulator instruction rate (inst/s) -host_op_rate 1661066 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2098778351 # Simulator tick rate (ticks/s) -host_mem_usage 237008 # Number of bytes of host memory used -host_seconds 342.57 # Real time elapsed on the host +host_inst_rate 808443 # Simulator instruction rate (inst/s) +host_op_rate 910979 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1153216038 # Simulator tick rate (ticks/s) +host_mem_usage 236932 # Number of bytes of host memory used +host_seconds 624.64 # Real time elapsed on the host sim_insts 504986853 # Number of instructions simulated sim_ops 569034839 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 178368 # Number of bytes read from this memory @@ -23,17 +23,17 @@ system.physmem.num_reads::cpu.data 150998 # Nu system.physmem.num_reads::total 153785 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 102730 # Number of write requests responded to by this memory system.physmem.num_writes::total 102730 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 248084 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13441034 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13689118 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 248084 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 248084 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 9144475 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 9144475 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 9144475 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 248084 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13441034 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 22833594 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 247614 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13415599 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13663213 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 247614 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 247614 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 9127171 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 9127171 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 9127171 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 247614 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13415599 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 22790384 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,7 +77,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 1437965512 # number of cpu cycles simulated +system.cpu.numCycles 1440691828 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 504986853 # Number of instructions committed @@ -96,18 +96,18 @@ system.cpu.num_mem_refs 182890034 # nu system.cpu.num_load_insts 126029555 # Number of load instructions system.cpu.num_store_insts 56860479 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 1437965512 # Number of busy cycles +system.cpu.num_busy_cycles 1440691828 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 9788 # number of replacements -system.cpu.icache.tagsinuse 983.088334 # Cycle average of tags in use +system.cpu.icache.tagsinuse 983.378720 # Cycle average of tags in use system.cpu.icache.total_refs 516599855 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 11521 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 44839.845066 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 983.088334 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.480024 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.480024 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 983.378720 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.480165 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.480165 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 516599855 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 516599855 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 516599855 # number of demand (read+write) hits @@ -120,12 +120,12 @@ system.cpu.icache.demand_misses::cpu.inst 11521 # n system.cpu.icache.demand_misses::total 11521 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 11521 # number of overall misses system.cpu.icache.overall_misses::total 11521 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 278348000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 278348000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 278348000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 278348000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 278348000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 278348000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 279753000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 279753000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 279753000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 279753000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 279753000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 279753000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 516611376 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 516611376 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 516611376 # number of demand (read+write) accesses @@ -138,12 +138,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24160.055551 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 24160.055551 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 24160.055551 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 24160.055551 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 24160.055551 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 24160.055551 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24282.006770 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 24282.006770 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 24282.006770 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 24282.006770 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 24282.006770 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 24282.006770 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -158,34 +158,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 11521 system.cpu.icache.demand_mshr_misses::total 11521 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 11521 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 11521 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 243785000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 243785000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 243785000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 243785000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 243785000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 243785000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 245190000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 245190000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 245190000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 245190000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 245190000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 245190000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000022 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000022 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21160.055551 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21160.055551 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21160.055551 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 21160.055551 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21160.055551 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 21160.055551 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21282.006770 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21282.006770 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21282.006770 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 21282.006770 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21282.006770 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 21282.006770 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 1134822 # number of replacements -system.cpu.dcache.tagsinuse 4065.352134 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4065.381389 # Cycle average of tags in use system.cpu.dcache.total_refs 179817786 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 1138918 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 157.884752 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 11889977000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4065.352134 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.992518 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.992518 # Average percentage of cache occupancy +system.cpu.dcache.warmup_cycle 11899663000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4065.381389 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.992525 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.992525 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 122957658 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 122957658 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 53883046 # number of WriteReq hits @@ -206,14 +206,14 @@ system.cpu.dcache.demand_misses::cpu.data 1138918 # n system.cpu.dcache.demand_misses::total 1138918 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 1138918 # number of overall misses system.cpu.dcache.overall_misses::total 1138918 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 12960486000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 12960486000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9326282000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9326282000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 22286768000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 22286768000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 22286768000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 22286768000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 13181704000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 13181704000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9327564000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9327564000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 22509268000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 22509268000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 22509268000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 22509268000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 123740316 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 123740316 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) @@ -234,14 +234,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.006399 system.cpu.dcache.demand_miss_rate::total 0.006399 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.006399 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.006399 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16559.577747 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16559.577747 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26178.302363 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 26178.302363 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 19568.369277 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 19568.369277 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 19568.369277 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 19568.369277 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16842.227384 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16842.227384 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26181.900859 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 26181.900859 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 19763.730137 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 19763.730137 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 19763.730137 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 19763.730137 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -260,14 +260,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1138918 system.cpu.dcache.demand_mshr_misses::total 1138918 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1138918 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1138918 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10612512000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10612512000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8257502000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8257502000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18870014000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 18870014000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18870014000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 18870014000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10833730000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10833730000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8258784000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8258784000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19092514000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 19092514000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19092514000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 19092514000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006325 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006325 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006568 # mshr miss rate for WriteReq accesses @@ -276,28 +276,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006399 system.cpu.dcache.demand_mshr_miss_rate::total 0.006399 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006399 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.006399 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13559.577747 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13559.577747 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23178.302363 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23178.302363 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16568.369277 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 16568.369277 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16568.369277 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 16568.369277 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13842.227384 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13842.227384 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23181.900859 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23181.900859 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16763.730137 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 16763.730137 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16763.730137 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 16763.730137 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 122482 # number of replacements -system.cpu.l2cache.tagsinuse 26935.750905 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 26939.836590 # Cycle average of tags in use system.cpu.l2cache.total_refs 1623186 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 153644 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 10.564591 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 344124821000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 23223.605882 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 246.683502 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 3465.461521 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.708728 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.007528 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.105757 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.822014 # Average percentage of cache occupancy +system.cpu.l2cache.warmup_cycle 344531371000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 23226.765026 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 246.719769 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 3466.351794 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.708825 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.007529 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.105785 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.822139 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 8734 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 734961 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 743695 # number of ReadReq hits diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini index 1f04164bf..9aac7b043 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini @@ -500,7 +500,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port @@ -532,7 +532,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout index 2f3625356..96a3d5c32 100755 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout @@ -1,15 +1,15 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:08:09 -gem5 started Jun 28 2012 23:20:26 +gem5 compiled Jul 2 2012 08:58:39 +gem5 started Jul 2 2012 13:33:28 gem5 executing on zizzer command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/20.parser/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/long/se/20.parser/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Reading the dictionary files: ***********************info: Increasing stack size by one page. -********************info: Increasing stack size by one page. +***************info: Increasing stack size by one page. info: Increasing stack size by one page. info: Increasing stack size by one page. info: Increasing stack size by one page. @@ -22,7 +22,7 @@ info: Increasing stack size by one page. info: Increasing stack size by one page. info: Increasing stack size by one page. info: Increasing stack size by one page. -****** +*********** 58924 words stored in 3784810 bytes @@ -80,4 +80,4 @@ Echoing of input sentence turned on. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 455813328500 because target called exit() +Exiting @ tick 460577560500 because target called exit() diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index 46181ad4f..96eed0126 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,280 +1,280 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.455813 # Number of seconds simulated -sim_ticks 455813328500 # Number of ticks simulated -final_tick 455813328500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.460578 # Number of seconds simulated +sim_ticks 460577560500 # Number of ticks simulated +final_tick 460577560500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 110548 # Simulator instruction rate (inst/s) -host_op_rate 204416 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 60939389 # Simulator tick rate (ticks/s) -host_mem_usage 266636 # Number of bytes of host memory used -host_seconds 7479.78 # Real time elapsed on the host +host_inst_rate 104932 # Simulator instruction rate (inst/s) +host_op_rate 194032 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 58448222 # Simulator tick rate (ticks/s) +host_mem_usage 266596 # Number of bytes of host memory used +host_seconds 7880.10 # Real time elapsed on the host sim_insts 826877144 # Number of instructions simulated sim_ops 1528988756 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 220672 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 27604992 # Number of bytes read from this memory -system.physmem.bytes_read::total 27825664 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 220672 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 220672 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 20791296 # Number of bytes written to this memory -system.physmem.bytes_written::total 20791296 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3448 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 431328 # Number of read requests responded to by this memory -system.physmem.num_reads::total 434776 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 324864 # Number of write requests responded to by this memory -system.physmem.num_writes::total 324864 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 484128 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 60562055 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 61046183 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 484128 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 484128 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 45613620 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 45613620 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 45613620 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 484128 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 60562055 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 106659803 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 222400 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 27604032 # Number of bytes read from this memory +system.physmem.bytes_read::total 27826432 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 222400 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 222400 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 20791104 # Number of bytes written to this memory +system.physmem.bytes_written::total 20791104 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3475 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 431313 # Number of read requests responded to by this memory +system.physmem.num_reads::total 434788 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 324861 # Number of write requests responded to by this memory +system.physmem.num_writes::total 324861 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 482872 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 59933515 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 60416387 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 482872 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 482872 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 45141374 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 45141374 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 45141374 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 482872 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 59933515 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 105557761 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 911626658 # number of cpu cycles simulated +system.cpu.numCycles 921155122 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 225614318 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 225614318 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 14285714 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 160541063 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 155870604 # Number of BTB hits +system.cpu.BPredUnit.lookups 225826893 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 225826893 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 14312665 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 160782597 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 155982448 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 191565109 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1263061891 # Number of instructions fetch has processed -system.cpu.fetch.Branches 225614318 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 155870604 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 392054994 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 98473885 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 230412581 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 25920 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 273577 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 183478574 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 3652581 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 898267437 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.606318 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.392133 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 191746261 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1263371603 # Number of instructions fetch has processed +system.cpu.fetch.Branches 225826893 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 155982448 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 392161652 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 98608350 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 239363044 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 24915 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 235054 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 183579479 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 3670479 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 907575951 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.580457 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.385202 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 510675527 56.85% 56.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 25992328 2.89% 59.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 29100733 3.24% 62.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 30303597 3.37% 66.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 19641643 2.19% 68.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 25615145 2.85% 71.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 32617140 3.63% 75.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 30849776 3.43% 78.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 193471548 21.54% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 519878601 57.28% 57.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 25999906 2.86% 60.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 29091750 3.21% 63.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 30316480 3.34% 66.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 19610375 2.16% 68.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 25620095 2.82% 71.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 32648944 3.60% 75.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 30886362 3.40% 78.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 193523438 21.32% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 898267437 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.247485 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.385503 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 252696641 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 182534450 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 330171612 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 48929478 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 83935256 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2290198570 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 4 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 83935256 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 289311592 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 40780199 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 14639 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 340344585 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 143881166 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2240282902 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 2186 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 22940117 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 103602655 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 11705 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2887046684 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 6493129070 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 6492267923 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 861147 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 907575951 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.245156 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.371508 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 253842060 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 190511569 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 329127835 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 50049462 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 84045025 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2290915196 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 84045025 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 290488035 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 45203385 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 15283 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 340026605 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 147797618 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2240907588 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 2049 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 24533767 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 107236940 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 12284 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2887565810 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 6495003002 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 6494129328 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 873674 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1993077484 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 893969200 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1261 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1244 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 345524950 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 540216674 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 217364695 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 216116185 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 63552241 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2143188368 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 61311 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1846653007 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1596963 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 612532438 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1230905034 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 60758 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 898267437 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.055794 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.806511 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 894488326 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1298 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1285 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 351684544 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 540282589 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 217467537 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 211757951 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 61365379 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2143556526 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 68297 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1846659599 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1592599 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 612964134 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1231726867 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 67744 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 907575951 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.034716 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.801175 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 244119309 27.18% 27.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 156083539 17.38% 44.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 150204364 16.72% 61.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 147125554 16.38% 77.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 103909500 11.57% 89.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 58948328 6.56% 95.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 27781277 3.09% 98.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 9047752 1.01% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1047814 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 248881296 27.42% 27.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 159283558 17.55% 44.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 154019271 16.97% 61.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 148934495 16.41% 78.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 98823398 10.89% 89.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 59633911 6.57% 95.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 27979654 3.08% 98.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 8970001 0.99% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1050367 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 898267437 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 907575951 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2653512 16.69% 16.69% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 16.69% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 16.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 16.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 16.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 16.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 16.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 16.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 16.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 16.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 16.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 16.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 16.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 16.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 16.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 16.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 16.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 16.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 16.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 16.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 16.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 16.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 16.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 16.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 16.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 16.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 16.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 16.69% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 10033753 63.11% 79.79% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3212720 20.21% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2635862 18.39% 18.39% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 18.39% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 18.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 18.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 18.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 18.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.39% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8471298 59.09% 77.48% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3228137 22.52% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2721869 0.15% 0.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1219400147 66.03% 66.18% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.18% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 66.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.18% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 447092064 24.21% 90.39% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 177438927 9.61% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2716270 0.15% 0.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1219519641 66.04% 66.19% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.19% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 66.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.19% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 447028129 24.21% 90.39% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 177395559 9.61% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1846653007 # Type of FU issued -system.cpu.iq.rate 2.025668 # Inst issue rate -system.cpu.iq.fu_busy_cnt 15899985 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.008610 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4609062574 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2755747075 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1806129295 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 7825 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 296338 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 285 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1859828366 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2757 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 167960734 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1846659599 # Type of FU issued +system.cpu.iq.rate 2.004722 # Inst issue rate +system.cpu.iq.fu_busy_cnt 14335297 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.007763 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4616815245 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2756549096 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1806310045 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 7800 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 300622 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 277 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1858275871 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2755 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 168023437 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 156114514 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 428176 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 272950 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 68204770 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 156180429 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 430384 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 272150 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 68307598 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 6724 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 7 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 7189 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 83935256 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 5705090 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1089193 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2143249679 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 2772043 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 540216674 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 217364955 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5665 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 876205 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 14852 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 272950 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 10085276 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 5239623 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 15324899 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1818663600 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 438639718 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 27989407 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 84045025 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 6572333 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1289879 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2143624823 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 2858157 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 540282589 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 217467783 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5279 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 972146 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 66800 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 272150 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 10086391 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 5256955 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 15343346 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1818812244 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 438622961 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 27847355 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 610490535 # number of memory reference insts executed -system.cpu.iew.exec_branches 170808194 # Number of branches executed -system.cpu.iew.exec_stores 171850817 # Number of stores executed -system.cpu.iew.exec_rate 1.994965 # Inst execution rate -system.cpu.iew.wb_sent 1813450071 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1806129580 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1379661197 # num instructions producing a value -system.cpu.iew.wb_consumers 2939711936 # num instructions consuming a value +system.cpu.iew.exec_refs 610455243 # number of memory reference insts executed +system.cpu.iew.exec_branches 170879995 # Number of branches executed +system.cpu.iew.exec_stores 171832282 # Number of stores executed +system.cpu.iew.exec_rate 1.974491 # Inst execution rate +system.cpu.iew.wb_sent 1813575376 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1806310322 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1378798297 # num instructions producing a value +system.cpu.iew.wb_consumers 2933608967 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.981216 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.469319 # average fanout of values written-back +system.cpu.iew.wb_rate 1.960919 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.470001 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 826877144 # The number of committed instructions system.cpu.commit.commitCommittedOps 1528988756 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 614283465 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 614662287 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 553 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 14312346 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 814332181 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.877598 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.330573 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 14337681 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 823530926 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.856626 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.319528 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 298731075 36.68% 36.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 203556250 25.00% 61.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 73630894 9.04% 70.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 94876671 11.65% 82.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 30957165 3.80% 86.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 28752943 3.53% 89.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 16466236 2.02% 91.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 11737662 1.44% 93.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 55623285 6.83% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 305238213 37.06% 37.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 205541162 24.96% 62.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 74423413 9.04% 71.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 96471007 11.71% 82.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 29999240 3.64% 86.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 28772955 3.49% 89.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 15805357 1.92% 91.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 11742762 1.43% 93.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 55536817 6.74% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 814332181 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 823530926 # Number of insts commited each cycle system.cpu.commit.committedInsts 826877144 # Number of instructions committed system.cpu.commit.committedOps 1528988756 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -285,69 +285,69 @@ system.cpu.commit.branches 149758588 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 1528317614 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 55623285 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 55536817 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2901981117 # The number of ROB reads -system.cpu.rob.rob_writes 4370596606 # The number of ROB writes -system.cpu.timesIdled 304669 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 13359221 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2911645152 # The number of ROB reads +system.cpu.rob.rob_writes 4371462099 # The number of ROB writes +system.cpu.timesIdled 309415 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 13579171 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826877144 # Number of Instructions Simulated system.cpu.committedOps 1528988756 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 826877144 # Number of Instructions Simulated -system.cpu.cpi 1.102493 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.102493 # CPI: Total CPI of All Threads -system.cpu.ipc 0.907035 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.907035 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 4004133317 # number of integer regfile reads -system.cpu.int_regfile_writes 2286262019 # number of integer regfile writes -system.cpu.fp_regfile_reads 284 # number of floating regfile reads -system.cpu.fp_regfile_writes 1 # number of floating regfile writes -system.cpu.misc_regfile_reads 1001892809 # number of misc regfile reads -system.cpu.icache.replacements 5521 # number of replacements -system.cpu.icache.tagsinuse 1042.048866 # Cycle average of tags in use -system.cpu.icache.total_refs 183243707 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 7141 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 25660.790786 # Average number of references to valid blocks. +system.cpu.cpi 1.114017 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.114017 # CPI: Total CPI of All Threads +system.cpu.ipc 0.897652 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.897652 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 4004251902 # number of integer regfile reads +system.cpu.int_regfile_writes 2286361140 # number of integer regfile writes +system.cpu.fp_regfile_reads 274 # number of floating regfile reads +system.cpu.fp_regfile_writes 3 # number of floating regfile writes +system.cpu.misc_regfile_reads 1001934144 # number of misc regfile reads +system.cpu.icache.replacements 5528 # number of replacements +system.cpu.icache.tagsinuse 1043.833365 # Cycle average of tags in use +system.cpu.icache.total_refs 183339964 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 7144 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 25663.488802 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1042.048866 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.508813 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.508813 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 183260633 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 183260633 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 183260633 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 183260633 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 183260633 # number of overall hits -system.cpu.icache.overall_hits::total 183260633 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 217941 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 217941 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 217941 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 217941 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 217941 # number of overall misses -system.cpu.icache.overall_misses::total 217941 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1509664000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1509664000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1509664000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1509664000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1509664000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1509664000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 183478574 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 183478574 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 183478574 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 183478574 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 183478574 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 183478574 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001188 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.001188 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.001188 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.001188 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.001188 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.001188 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6926.938942 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 6926.938942 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 6926.938942 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 6926.938942 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 6926.938942 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 6926.938942 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1043.833365 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.509684 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.509684 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 183356988 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 183356988 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 183356988 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 183356988 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 183356988 # number of overall hits +system.cpu.icache.overall_hits::total 183356988 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 222491 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 222491 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 222491 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 222491 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 222491 # number of overall misses +system.cpu.icache.overall_misses::total 222491 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1555664000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1555664000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1555664000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1555664000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1555664000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1555664000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 183579479 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 183579479 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 183579479 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 183579479 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 183579479 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 183579479 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001212 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.001212 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.001212 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.001212 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.001212 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.001212 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6992.031138 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 6992.031138 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 6992.031138 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 6992.031138 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 6992.031138 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 6992.031138 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -358,94 +358,94 @@ system.cpu.icache.fast_writes 0 # nu system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks::writebacks 8 # number of writebacks system.cpu.icache.writebacks::total 8 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1622 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1622 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1622 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1622 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1622 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1622 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 216319 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 216319 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 216319 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 216319 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 216319 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 216319 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 823021000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 823021000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 823021000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 823021000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 823021000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 823021000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001179 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001179 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001179 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.001179 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001179 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.001179 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 3804.663483 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 3804.663483 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 3804.663483 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 3804.663483 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 3804.663483 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 3804.663483 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1714 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1714 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1714 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1714 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1714 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1714 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 220777 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 220777 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 220777 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 220777 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 220777 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 220777 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 807311500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 807311500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 807311500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 807311500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 807311500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 807311500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001203 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001203 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001203 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.001203 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001203 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.001203 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 3656.682988 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 3656.682988 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 3656.682988 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 3656.682988 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 3656.682988 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 3656.682988 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 2527069 # number of replacements -system.cpu.dcache.tagsinuse 4086.938445 # Cycle average of tags in use -system.cpu.dcache.total_refs 415239447 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2531165 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 164.050722 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 2117139000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4086.938445 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.997788 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.997788 # 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number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 269038413 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 269038413 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 2526932 # number of replacements +system.cpu.dcache.tagsinuse 4087.002869 # Cycle average of tags in use +system.cpu.dcache.total_refs 415155555 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2531028 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 164.026457 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 2119650000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4087.002869 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.997803 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.997803 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 266306304 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 266306304 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148172784 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148172784 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 414479088 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 414479088 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 414479088 # number of overall hits +system.cpu.dcache.overall_hits::total 414479088 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2652001 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2652001 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 987417 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 987417 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3639418 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3639418 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3639418 # number of overall misses +system.cpu.dcache.overall_misses::total 3639418 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 36687997500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 36687997500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 18991122500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 18991122500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 55679120000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 55679120000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 55679120000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 55679120000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 268958305 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 268958305 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149160201 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 149160201 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 418198614 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 418198614 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 418198614 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 418198614 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009821 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.009821 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006625 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.006625 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.008681 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.008681 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.008681 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.008681 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12787.034255 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 12787.034255 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 19076.087638 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 19076.087638 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14498.936331 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14498.936331 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14498.936331 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14498.936331 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 418118506 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 418118506 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 418118506 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 418118506 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009860 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.009860 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006620 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.006620 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.008704 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.008704 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.008704 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.008704 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13834.081322 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13834.081322 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 19233.133013 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 19233.133013 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 15298.907682 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 15298.907682 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 15298.907682 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 15298.907682 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -454,144 +454,144 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2302786 # number of writebacks -system.cpu.dcache.writebacks::total 2302786 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 881124 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 881124 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 8927 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 8927 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 890051 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 890051 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 890051 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 890051 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1761038 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1761038 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 979269 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 979269 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2740307 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2740307 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2740307 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2740307 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11264952000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 11264952000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 15850782000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 15850782000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27115734000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 27115734000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27115734000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 27115734000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006546 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006546 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006565 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006565 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006553 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006553 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006553 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006553 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 6396.768270 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 6396.768270 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16186.341036 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16186.341036 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 9895.144595 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 9895.144595 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 9895.144595 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 9895.144595 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 2302590 # number of writebacks +system.cpu.dcache.writebacks::total 2302590 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 891786 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 891786 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3028 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3028 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 894814 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 894814 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 894814 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 894814 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1760215 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1760215 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 984389 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 984389 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2744604 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2744604 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2744604 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2744604 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12497957644 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 12497957644 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 15832587002 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 15832587002 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28330544646 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 28330544646 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28330544646 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 28330544646 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006545 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006545 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006600 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006600 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006564 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006564 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006564 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006564 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7100.244938 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7100.244938 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16083.669161 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16083.669161 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10322.270406 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 10322.270406 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10322.270406 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 10322.270406 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 408621 # number of replacements -system.cpu.l2cache.tagsinuse 29300.466705 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3609267 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 440961 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 8.185003 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 219912062000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 21087.117194 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 148.252410 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 8065.097101 # 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number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 431347 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 434822 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3475 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 431347 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 434822 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 110937500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6934880499 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7045817999 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 6582250000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 6582250000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6487010500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6487010500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 110937500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 13421890999 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 13532828499 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 110937500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 13421890999 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 13532828499 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.489644 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.126260 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.127720 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.994007 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.994007 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.271149 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.271149 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.489644 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.170430 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.171322 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.489644 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.170430 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.171322 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31924.460432 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31218.513095 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31229.386340 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31006.373447 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31006.373447 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31007.616858 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31007.616858 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31924.460432 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31116.226609 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31122.685832 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31924.460432 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31116.226609 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31122.685832 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini b/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini index 2db6fca67..2d97cc0b1 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini @@ -169,7 +169,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port @@ -201,7 +201,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout index 0422a99cd..1335d3658 100755 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:08:09 -gem5 started Jun 28 2012 23:33:45 +gem5 compiled Jul 2 2012 08:58:39 +gem5 started Jul 2 2012 13:47:25 gem5 executing on zizzer command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/20.parser/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/long/se/20.parser/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second @@ -69,4 +69,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 1652422044000 because target called exit() +Exiting @ tick 1652606875000 because target called exit() diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt index 246184477..ae8bc7b58 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.652422 # Number of seconds simulated -sim_ticks 1652422044000 # Number of ticks simulated -final_tick 1652422044000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.652607 # Number of seconds simulated +sim_ticks 1652606875000 # Number of ticks simulated +final_tick 1652606875000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1001096 # Simulator instruction rate (inst/s) -host_op_rate 1851139 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2000579398 # Simulator tick rate (ticks/s) -host_mem_usage 231692 # Number of bytes of host memory used -host_seconds 825.97 # Real time elapsed on the host +host_inst_rate 673883 # Simulator instruction rate (inst/s) +host_op_rate 1246085 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1346830511 # Simulator tick rate (ticks/s) +host_mem_usage 232676 # Number of bytes of host memory used +host_seconds 1227.03 # Real time elapsed on the host sim_insts 826877145 # Number of instructions simulated sim_ops 1528988757 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 123584 # Number of bytes read from this memory @@ -23,19 +23,19 @@ system.physmem.num_reads::cpu.data 427498 # Nu system.physmem.num_reads::total 429429 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 323570 # Number of write requests responded to by this memory system.physmem.num_writes::total 323570 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 74790 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 16557436 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 16632225 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 74790 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 74790 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 12532198 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 12532198 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 12532198 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 74790 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 16557436 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 29164423 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 74781 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 16555584 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 16630365 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 74781 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 74781 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 12530796 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 12530796 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 12530796 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 74781 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 16555584 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 29161162 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 3304844088 # number of cpu cycles simulated +system.cpu.numCycles 3305213750 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 826877145 # Number of instructions committed @@ -54,18 +54,18 @@ system.cpu.num_mem_refs 533262345 # nu system.cpu.num_load_insts 384102160 # Number of load instructions system.cpu.num_store_insts 149160185 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 3304844088 # Number of busy cycles +system.cpu.num_busy_cycles 3305213750 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 1253 # number of replacements -system.cpu.icache.tagsinuse 881.582723 # Cycle average of tags in use +system.cpu.icache.tagsinuse 881.608185 # Cycle average of tags in use system.cpu.icache.total_refs 1068344296 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 2814 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 379653.267946 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 881.582723 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.430460 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.430460 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 881.608185 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.430473 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.430473 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1068344296 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1068344296 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1068344296 # number of demand (read+write) hits @@ -78,12 +78,12 @@ system.cpu.icache.demand_misses::cpu.inst 2814 # n system.cpu.icache.demand_misses::total 2814 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 2814 # number of overall misses system.cpu.icache.overall_misses::total 2814 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 120498000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 120498000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 120498000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 120498000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 120498000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 120498000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 120792000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 120792000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 120792000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 120792000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 120792000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 120792000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1068347110 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1068347110 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1068347110 # number of demand (read+write) accesses @@ -96,12 +96,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000003 system.cpu.icache.demand_miss_rate::total 0.000003 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000003 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000003 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42820.895522 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 42820.895522 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 42820.895522 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 42820.895522 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 42820.895522 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 42820.895522 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42925.373134 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 42925.373134 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 42925.373134 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 42925.373134 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 42925.373134 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 42925.373134 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -116,34 +116,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 2814 system.cpu.icache.demand_mshr_misses::total 2814 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 2814 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 2814 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 112056000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 112056000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 112056000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 112056000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 112056000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 112056000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 112350000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 112350000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 112350000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 112350000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 112350000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 112350000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39820.895522 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39820.895522 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39820.895522 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 39820.895522 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39820.895522 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 39820.895522 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39925.373134 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39925.373134 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39925.373134 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 39925.373134 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39925.373134 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 39925.373134 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 2514362 # number of replacements -system.cpu.dcache.tagsinuse 4086.435686 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4086.431953 # Cycle average of tags in use system.cpu.dcache.total_refs 530743932 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 2518458 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 210.741625 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 8216675000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4086.435686 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.997665 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.997665 # Average percentage of cache occupancy +system.cpu.dcache.warmup_cycle 8218697000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4086.431953 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.997664 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.997664 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 382374775 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 382374775 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 148369157 # number of WriteReq hits @@ -160,14 +160,14 @@ system.cpu.dcache.demand_misses::cpu.data 2518458 # n system.cpu.dcache.demand_misses::total 2518458 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 2518458 # number of overall misses system.cpu.dcache.overall_misses::total 2518458 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 33321318000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 33321318000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 19892023500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 19892023500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 53213341500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 53213341500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 53213341500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 53213341500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 33364275000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 33364275000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 19892603500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 19892603500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 53256878500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 53256878500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 53256878500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 53256878500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 384102189 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 384102189 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149160201 # number of WriteReq accesses(hits+misses) @@ -184,14 +184,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.004723 system.cpu.dcache.demand_miss_rate::total 0.004723 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.004723 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.004723 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19289.711673 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 19289.711673 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25146.544946 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 25146.544946 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 21129.334498 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 21129.334498 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 21129.334498 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 21129.334498 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19314.579481 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 19314.579481 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25147.278154 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 25147.278154 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 21146.621663 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 21146.621663 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 21146.621663 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 21146.621663 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -210,14 +210,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2518458 system.cpu.dcache.demand_mshr_misses::total 2518458 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2518458 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2518458 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 28139074000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 28139074000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17518883000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 17518883000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 45657957000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 45657957000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 45657957000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 45657957000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 28182031000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 28182031000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17519463000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 17519463000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 45701494000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 45701494000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 45701494000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 45701494000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004497 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004497 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005303 # mshr miss rate for WriteReq accesses @@ -226,28 +226,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.004723 system.cpu.dcache.demand_mshr_miss_rate::total 0.004723 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.004723 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16289.710515 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16289.710515 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22146.534200 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22146.534200 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18129.330328 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 18129.330328 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18129.330328 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 18129.330328 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16314.578323 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16314.578323 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22147.267409 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22147.267409 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18146.617494 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 18146.617494 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18146.617494 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 18146.617494 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 403150 # number of replacements -system.cpu.l2cache.tagsinuse 29113.171325 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 29113.385052 # Cycle average of tags in use system.cpu.l2cache.total_refs 3572765 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 435501 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 8.203804 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 772998682000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 21035.686564 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 79.698096 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 7997.786666 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.641958 # Average percentage of cache occupancy +system.cpu.l2cache.warmup_cycle 773011530000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 21035.861184 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 79.696348 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 7997.827520 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.641964 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.002432 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.244073 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.888463 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.244074 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.888470 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 883 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1509854 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1510737 # number of ReadReq hits |