diff options
Diffstat (limited to 'tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt')
| -rw-r--r-- | tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt | 256 |
1 files changed, 128 insertions, 128 deletions
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt index 06e2fa444..63af08cbf 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,32 +1,32 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.141175 # Number of seconds simulated -sim_ticks 141175129500 # Number of ticks simulated -final_tick 141175129500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 141174877500 # Number of ticks simulated +final_tick 141174877500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 110841 # Simulator instruction rate (inst/s) -host_op_rate 110841 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 39251086 # Simulator tick rate (ticks/s) -host_mem_usage 221340 # Number of bytes of host memory used -host_seconds 3596.72 # Real time elapsed on the host +host_inst_rate 165783 # Simulator instruction rate (inst/s) +host_op_rate 165783 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 58706881 # Simulator tick rate (ticks/s) +host_mem_usage 225068 # Number of bytes of host memory used +host_seconds 2404.74 # Real time elapsed on the host sim_insts 398664595 # Number of instructions simulated sim_ops 398664595 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 214592 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 254400 # Number of bytes read from this memory -system.physmem.bytes_read::total 468992 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 254016 # Number of bytes read from this memory +system.physmem.bytes_read::total 468608 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 214592 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 214592 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu.inst 3353 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3975 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7328 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1520041 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1802017 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3322058 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1520041 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1520041 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1520041 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1802017 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3322058 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::cpu.data 3969 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7322 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1520044 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1799300 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3319344 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1520044 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1520044 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1520044 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1799300 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3319344 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -60,7 +60,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 282350260 # number of cpu cycles simulated +system.cpu.numCycles 282349756 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.lookups 53870351 # Number of BP lookups @@ -93,9 +93,9 @@ system.cpu.contextSwitches 1 # Nu system.cpu.threadCycles 281921224 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.timesIdled 6799 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 13475974 # Number of cycles cpu's stages were not processed +system.cpu.idleCycles 13475470 # Number of cycles cpu's stages were not processed system.cpu.runCycles 268874286 # Number of cycles cpu stages are processed. -system.cpu.activity 95.227214 # Percentage of cycles cpu is active +system.cpu.activity 95.227384 # Percentage of cycles cpu is active system.cpu.comLoads 94754489 # Number of Load instructions committed system.cpu.comStores 73520729 # Number of Store instructions committed system.cpu.comBranches 44587532 # Number of Branches instructions committed @@ -107,34 +107,34 @@ system.cpu.committedInsts 398664595 # Nu system.cpu.committedOps 398664595 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 398664595 # Number of Instructions committed (Total) -system.cpu.cpi 0.708240 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.708239 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.708240 # CPI: Total CPI of All Threads -system.cpu.ipc 1.411951 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.708239 # CPI: Total CPI of All Threads +system.cpu.ipc 1.411953 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.411951 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 78536322 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 1.411953 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 78535818 # Number of cycles 0 instructions are processed. system.cpu.stage0.runCycles 203813938 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 72.184788 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 108863639 # Number of cycles 0 instructions are processed. +system.cpu.stage0.utilization 72.184917 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 108863135 # Number of cycles 0 instructions are processed. system.cpu.stage1.runCycles 173486621 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 61.443762 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 104640873 # Number of cycles 0 instructions are processed. +system.cpu.stage1.utilization 61.443871 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 104640369 # Number of cycles 0 instructions are processed. system.cpu.stage2.runCycles 177709387 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 62.939339 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 183568799 # Number of cycles 0 instructions are processed. +system.cpu.stage2.utilization 62.939451 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 183568295 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 98781461 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 34.985433 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 92657665 # Number of cycles 0 instructions are processed. +system.cpu.stage3.utilization 34.985495 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 92657161 # Number of cycles 0 instructions are processed. system.cpu.stage4.runCycles 189692595 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 67.183432 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.utilization 67.183552 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 1974 # number of replacements -system.cpu.icache.tagsinuse 1829.918694 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1829.918683 # Cycle average of tags in use system.cpu.icache.total_refs 49107469 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 3901 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 12588.430915 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1829.918694 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 1829.918683 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.893515 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.893515 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 49107469 # number of ReadReq hits @@ -213,12 +213,12 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47480.645988 system.cpu.icache.overall_avg_mshr_miss_latency::total 47480.645988 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 764 # number of replacements -system.cpu.dcache.tagsinuse 3284.843893 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 3284.843876 # Cycle average of tags in use system.cpu.dcache.total_refs 168261959 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 40525.519990 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3284.843893 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 3284.843876 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.801964 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.801964 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 94753265 # number of ReadReq hits @@ -237,14 +237,14 @@ system.cpu.dcache.demand_misses::cpu.data 13259 # n system.cpu.dcache.demand_misses::total 13259 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 13259 # number of overall misses system.cpu.dcache.overall_misses::total 13259 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 63819000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 63819000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 63567000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 63567000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 626556000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 626556000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 690375000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 690375000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 690375000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 690375000 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 690123000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 690123000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 690123000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 690123000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 94754489 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 94754489 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) @@ -261,14 +261,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000079 system.cpu.dcache.demand_miss_rate::total 0.000079 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000079 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000079 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 52139.705882 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 52139.705882 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51933.823529 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 51933.823529 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52061.154965 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 52061.154965 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 52068.406365 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 52068.406365 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 52068.406365 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 52068.406365 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 52049.400407 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 52049.400407 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 52049.400407 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 52049.400407 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 82410500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -295,14 +295,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4152 system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 46180000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 46180000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 45925000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 45925000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 169537000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 169537000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 215717000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 215717000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 215717000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 215717000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 215462000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 215462000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 215462000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 215462000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses @@ -311,63 +311,63 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48610.526316 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48610.526316 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48342.105263 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48342.105263 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52947.220487 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52947.220487 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51954.961464 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 51954.961464 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51954.961464 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 51954.961464 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51893.545279 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 51893.545279 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51893.545279 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 51893.545279 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 13 # number of replacements -system.cpu.l2cache.tagsinuse 3896.685167 # Cycle average of tags in use -system.cpu.l2cache.total_refs 736 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 4717 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.156031 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.tagsinuse 3900.421280 # Cycle average of tags in use +system.cpu.l2cache.total_refs 754 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 4711 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.160051 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 370.518693 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2902.345937 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 623.820537 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 370.518684 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2902.345910 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 627.556686 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.011307 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.088573 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.019037 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.118917 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.019152 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.119031 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 548 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 117 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 665 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 123 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 671 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 649 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 649 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 60 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 60 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.inst 548 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 177 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 725 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 183 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 731 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 548 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 177 # number of overall hits -system.cpu.l2cache.overall_hits::total 725 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 183 # number of overall hits +system.cpu.l2cache.overall_hits::total 731 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 3353 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 830 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 4183 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 824 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 4177 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 3145 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 3145 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 3353 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 3975 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 7328 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 3969 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 7322 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 3353 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 3975 # number of overall misses -system.cpu.l2cache.overall_misses::total 7328 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 3969 # number of overall misses +system.cpu.l2cache.overall_misses::total 7322 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 175438000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 43622500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 219060500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 43307500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 218745500 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 164970500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 164970500 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 175438000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 208593000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 384031000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 208278000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 383716000 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 175438000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 208593000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 384031000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 208278000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 383716000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 3901 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 947 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 4848 # number of ReadReq accesses(hits+misses) @@ -382,27 +382,27 @@ system.cpu.l2cache.overall_accesses::cpu.inst 3901 system.cpu.l2cache.overall_accesses::cpu.data 4152 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 8053 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.859523 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.876452 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.862830 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.870116 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.861592 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.981279 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.981279 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.859523 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.957370 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.909971 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.955925 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.909226 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.859523 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.957370 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.909971 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.955925 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.909226 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52322.696093 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52557.228916 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52369.232608 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52557.645631 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52369.044769 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52454.848967 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52454.848967 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52322.696093 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52476.226415 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52405.977074 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52476.190476 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52405.900027 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52322.696093 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52476.226415 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52405.977074 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52476.190476 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52405.900027 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -412,49 +412,49 @@ system.cpu.l2cache.avg_blocked_cycles::no_targets nan system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3353 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 830 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 4183 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 824 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 4177 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3145 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 3145 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 3353 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 3975 # 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number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 33277500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 167868500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 126757500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 126757500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 134591000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 160275000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 294866000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 160035000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 294626000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 134591000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 160275000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 294866000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 160035000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 294626000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.859523 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.876452 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.862830 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.870116 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.861592 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.981279 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.981279 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.859523 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.957370 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.909971 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.909226 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.859523 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.957370 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.909971 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.909226 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40140.471220 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40382.530120 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40188.501076 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40385.315534 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40188.771846 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40304.451510 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40304.451510 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40140.471220 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40320.754717 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40238.264192 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40321.239607 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40238.459437 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40140.471220 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40320.754717 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40238.264192 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40321.239607 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40238.459437 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |