diff options
Diffstat (limited to 'tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt')
| -rw-r--r-- | tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt | 694 |
1 files changed, 347 insertions, 347 deletions
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt index a158074c5..1ee5829a5 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.141089 # Number of seconds simulated -sim_ticks 141089296500 # Number of ticks simulated -final_tick 141089296500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.139847 # Number of seconds simulated +sim_ticks 139846906500 # Number of ticks simulated +final_tick 139846906500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 83115 # Simulator instruction rate (inst/s) -host_op_rate 83115 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 29414893 # Simulator tick rate (ticks/s) -host_mem_usage 223012 # Number of bytes of host memory used -host_seconds 4796.53 # Real time elapsed on the host +host_inst_rate 122154 # Simulator instruction rate (inst/s) +host_op_rate 122154 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 42850332 # Simulator tick rate (ticks/s) +host_mem_usage 220236 # Number of bytes of host memory used +host_seconds 3263.61 # Real time elapsed on the host sim_insts 398664595 # Number of instructions simulated sim_ops 398664595 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 214976 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 214976 # Nu system.physmem.num_reads::cpu.inst 3359 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 3969 # Number of read requests responded to by this memory system.physmem.num_reads::total 7328 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1523688 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1800392 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3324079 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1523688 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1523688 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1523688 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1800392 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3324079 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1537224 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1816386 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3353610 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1537224 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1537224 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1537224 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1816386 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3353610 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 7328 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 7328 # Reqs generatd by CPU via cache - shady @@ -37,7 +37,7 @@ system.physmem.bytesConsumedWr 0 # by system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 465 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 464 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 465 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 518 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 520 # Track reads on a per bank basis system.physmem.perBankRdReqs::4 382 # Track reads on a per bank basis @@ -48,7 +48,7 @@ system.physmem.perBankRdReqs::8 407 # Tr system.physmem.perBankRdReqs::9 457 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 588 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 397 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 529 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 528 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 418 # Track reads on a per bank basis system.physmem.perBankRdReqs::14 396 # Track reads on a per bank basis system.physmem.perBankRdReqs::15 488 # Track reads on a per bank basis @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 141089244500 # Total gap between requests +system.physmem.totGap 139846854500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -98,11 +98,11 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 4661 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1890 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 520 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 190 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 66 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4654 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1888 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 524 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 196 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 65 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -164,47 +164,47 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 39617295 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 175175295 # Sum of mem lat for all requests +system.physmem.totQLat 39390791 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 174626791 # Sum of mem lat for all requests system.physmem.totBusLat 29312000 # Total cycles spent in databus access -system.physmem.totBankLat 106246000 # Total cycles spent in bank access -system.physmem.avgQLat 5406.29 # Average queueing delay per request -system.physmem.avgBankLat 14498.64 # Average bank access latency per request +system.physmem.totBankLat 105924000 # Total cycles spent in bank access +system.physmem.avgQLat 5375.38 # Average queueing delay per request +system.physmem.avgBankLat 14454.69 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 23904.93 # Average memory access latency -system.physmem.avgRdBW 3.32 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 23830.08 # Average memory access latency +system.physmem.avgRdBW 3.35 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 3.32 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 3.35 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 6442 # Number of row buffer hits during reads +system.physmem.readRowHits 6444 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.91 # Row buffer hit rate for reads +system.physmem.readRowHitRate 87.94 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 19253444.94 # Average gap between requests +system.physmem.avgGap 19083904.82 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 94754611 # DTB read hits +system.cpu.dtb.read_hits 94754613 # DTB read hits system.cpu.dtb.read_misses 21 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 94754632 # DTB read accesses -system.cpu.dtb.write_hits 73521102 # DTB write hits +system.cpu.dtb.read_accesses 94754634 # DTB read accesses +system.cpu.dtb.write_hits 73521103 # DTB write hits system.cpu.dtb.write_misses 35 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 73521137 # DTB write accesses -system.cpu.dtb.data_hits 168275713 # DTB hits +system.cpu.dtb.write_accesses 73521138 # DTB write accesses +system.cpu.dtb.data_hits 168275716 # DTB hits system.cpu.dtb.data_misses 56 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 168275769 # DTB accesses -system.cpu.itb.fetch_hits 49091192 # ITB hits -system.cpu.itb.fetch_misses 88817 # ITB misses +system.cpu.dtb.data_accesses 168275772 # DTB accesses +system.cpu.itb.fetch_hits 48611354 # ITB hits +system.cpu.itb.fetch_misses 44520 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 49180009 # ITB accesses +system.cpu.itb.fetch_accesses 48655874 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -218,42 +218,42 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 282178594 # number of cpu cycles simulated +system.cpu.numCycles 279693814 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 53863325 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 30909619 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 16029157 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 33388385 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 15622160 # Number of BTB hits +system.cpu.branch_predictor.lookups 53489670 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 30685393 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 15149659 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 32882351 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 15212538 # Number of BTB hits system.cpu.branch_predictor.usedRAS 8007516 # Number of times the RAS was used to get a target. -system.cpu.branch_predictor.RASInCorrect 19 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 46.789205 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 29654286 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 24209039 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 280812298 # Number of Reads from Int. Register File +system.cpu.branch_predictor.RASInCorrect 20 # Number of incorrect RAS predictions. +system.cpu.branch_predictor.BTBHitPct 46.263535 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 29230505 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 24259165 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 280386588 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 159335859 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 440148157 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 119908557 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 439722447 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 119631948 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 100196481 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 220105038 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 100451904 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 168699560 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 14461353 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 1567145 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 16028498 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 28559053 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 35.948370 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 205751378 # Number of Instructions Executed. -system.cpu.mult_div_unit.multiplies 2124332 # Number of Multipy Operations Executed +system.cpu.regfile_manager.floatRegFileAccesses 219828429 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 100484563 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 168485322 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 14315634 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 833366 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 15149000 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 29438551 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 33.975851 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 205475782 # Number of Instructions Executed. +system.cpu.mult_div_unit.multiplies 2124323 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 281883987 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 279400729 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 7632 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 13336617 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 268841977 # Number of cycles cpu stages are processed. -system.cpu.activity 95.273696 # Percentage of cycles cpu is active +system.cpu.timesIdled 7654 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 13387179 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 266306635 # Number of cycles cpu stages are processed. +system.cpu.activity 95.213631 # Percentage of cycles cpu is active system.cpu.comLoads 94754489 # Number of Load instructions committed system.cpu.comStores 73520729 # Number of Store instructions committed system.cpu.comBranches 44587532 # Number of Branches instructions committed @@ -265,245 +265,137 @@ system.cpu.committedInsts 398664595 # Nu system.cpu.committedOps 398664595 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 398664595 # Number of Instructions committed (Total) -system.cpu.cpi 0.707810 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.701577 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.707810 # CPI: Total CPI of All Threads -system.cpu.ipc 1.412809 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.701577 # CPI: Total CPI of All Threads +system.cpu.ipc 1.425361 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.412809 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 78396963 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 203781631 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 72.217254 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 108683745 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 173494849 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 61.484058 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 104474173 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 177704421 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 62.975869 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 183396585 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 98782009 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 35.006911 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 92487828 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 189690766 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 67.223656 # Percentage of cycles stage was utilized (processing insts). -system.cpu.icache.replacements 1982 # number of replacements -system.cpu.icache.tagsinuse 1831.235862 # Cycle average of tags in use -system.cpu.icache.total_refs 49086683 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 3910 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 12554.138875 # Average number of references to valid blocks. +system.cpu.ipc_total 1.425361 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 77946120 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 201747694 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 72.131625 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 107042067 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 172651747 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 61.728840 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 102478598 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 177215216 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 63.360435 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 180949238 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 98744576 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 35.304526 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 90225845 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 189467969 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 67.741208 # Percentage of cycles stage was utilized (processing insts). +system.cpu.icache.replacements 1975 # number of replacements +system.cpu.icache.tagsinuse 1831.257835 # Cycle average of tags in use +system.cpu.icache.total_refs 48606847 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 3903 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 12453.714322 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1831.235862 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.894158 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.894158 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 49086683 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 49086683 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 49086683 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 49086683 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 49086683 # number of overall hits -system.cpu.icache.overall_hits::total 49086683 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 4508 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 4508 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 4508 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 4508 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 4508 # number of overall misses -system.cpu.icache.overall_misses::total 4508 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 196984000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 196984000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 196984000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 196984000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 196984000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 196984000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 49091191 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 49091191 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 49091191 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 49091191 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 49091191 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 49091191 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000092 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000092 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000092 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000092 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000092 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000092 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43696.539485 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 43696.539485 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 43696.539485 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 43696.539485 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 43696.539485 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 43696.539485 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 220 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1831.257835 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.894169 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.894169 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 48606847 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 48606847 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 48606847 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 48606847 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 48606847 # number of overall hits +system.cpu.icache.overall_hits::total 48606847 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 4507 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 4507 # 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number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.860620 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.870116 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.861231 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.862474 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.981279 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.981279 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.859079 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.860620 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.955925 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.908956 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.859079 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.909745 # 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average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 48417.088419 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 49324.389015 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 48908.501638 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.909745 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47903.691575 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54629.247573 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 49228.544107 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 48320.349762 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 48320.349762 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47903.691575 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 49630.133535 # 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number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 535 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.229907 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 649 # number of writebacks +system.cpu.dcache.writebacks::total 649 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 354 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 354 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16289 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16289 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 16643 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 16643 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 16643 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 16643 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 950 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 950 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3202 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 3202 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4152 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 47442500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 47442500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 155739500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 155739500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 203182000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 203182000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 203182000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 203182000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000044 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49939.473684 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49939.473684 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48638.194878 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48638.194878 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48935.934489 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 48935.934489 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48935.934489 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 48935.934489 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |