diff options
Diffstat (limited to 'tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt')
| -rw-r--r-- | tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt | 545 |
1 files changed, 263 insertions, 282 deletions
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt index eb5995295..4b6099b52 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.139926 # Nu sim_ticks 139926186500 # Number of ticks simulated final_tick 139926186500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 138827 # Simulator instruction rate (inst/s) -host_op_rate 138827 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 48726388 # Simulator tick rate (ticks/s) -host_mem_usage 236592 # Number of bytes of host memory used -host_seconds 2871.67 # Real time elapsed on the host +host_inst_rate 124689 # Simulator instruction rate (inst/s) +host_op_rate 124689 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 43764124 # Simulator tick rate (ticks/s) +host_mem_usage 271420 # Number of bytes of host memory used +host_seconds 3197.28 # Real time elapsed on the host sim_insts 398664595 # Number of instructions simulated sim_ops 398664595 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -90,11 +90,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4635 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1820 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 581 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 229 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 62 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4589 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1831 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 611 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 237 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 59 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -154,79 +154,60 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1198 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 387.899833 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 185.568922 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 772.018563 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 419 34.97% 34.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 201 16.78% 51.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 128 10.68% 62.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 91 7.60% 70.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 61 5.09% 75.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 40 3.34% 78.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 30 2.50% 80.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 22 1.84% 82.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 25 2.09% 84.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 18 1.50% 86.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 20 1.67% 88.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 8 0.67% 88.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 17 1.42% 90.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 10 0.83% 90.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 8 0.67% 91.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 6 0.50% 92.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 10 0.83% 92.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 7 0.58% 93.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 7 0.58% 94.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 1 0.08% 94.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 4 0.33% 94.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 4 0.33% 94.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 2 0.17% 95.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 5 0.42% 95.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 5 0.42% 95.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 4 0.33% 96.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 1 0.08% 96.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 2 0.17% 96.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 1 0.08% 96.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 2 0.17% 96.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 1 0.08% 96.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 2 0.17% 96.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 1 0.08% 97.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 1 0.08% 97.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 2 0.17% 97.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 1 0.08% 97.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 1 0.08% 97.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 4 0.33% 97.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 2 0.17% 98.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 1 0.08% 98.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 2 0.17% 98.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 1 0.08% 98.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 1 0.08% 98.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 1 0.08% 98.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 2 0.17% 98.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 1 0.08% 98.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 1 0.08% 98.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 1 0.08% 98.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 1 0.08% 99.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 1 0.08% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 1 0.08% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 1 0.08% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5057 1 0.08% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 1 0.08% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5441 1 0.08% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6529 1 0.08% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7105 1 0.08% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7617 1 0.08% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 1 0.08% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 2 0.17% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1198 # Bytes accessed per row activation -system.physmem.totQLat 59880500 # Total ticks spent queuing -system.physmem.totMemAccLat 197624250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 558 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 480.917563 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 280.270360 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 415.877438 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 147 26.34% 26.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 107 19.18% 45.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 50 8.96% 54.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 28 5.02% 59.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 15 2.69% 62.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 15 2.69% 64.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7 1.25% 66.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5 0.90% 67.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 184 32.97% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 558 # Bytes accessed per row activation +system.physmem.totQLat 59527000 # Total ticks spent queuing +system.physmem.totMemAccLat 199924500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 36640000 # Total ticks spent in databus transfers -system.physmem.totBankLat 101103750 # Total ticks spent accessing banks -system.physmem.avgQLat 8171.47 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 13796.91 # Average bank access latency per DRAM burst +system.physmem.totBankLat 103757500 # Total ticks spent accessing banks +system.physmem.avgQLat 8123.23 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 14159.05 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26968.37 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 27282.27 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.35 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.35 # Average system read bandwidth in MiByte/s @@ -235,15 +216,15 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 6130 # Number of row buffer hits during reads +system.physmem.readRowHits 5962 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.65 # Row buffer hit rate for reads +system.physmem.readRowHitRate 81.36 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 19094720.66 # Average gap between requests -system.physmem.pageHitRate 83.65 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.42 # Percentage of time for which DRAM has all the banks in precharge state +system.physmem.pageHitRate 81.36 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.43 # Percentage of time for which DRAM has all the banks in precharge state system.membus.throughput 3351710 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 4183 # Transaction distribution system.membus.trans_dist::ReadResp 4183 # Transaction distribution @@ -257,7 +238,7 @@ system.membus.data_through_bus 468992 # To system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 8743500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 68145750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 68133000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 53489673 # Number of BP lookups @@ -273,22 +254,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 94754637 # DTB read hits +system.cpu.dtb.read_hits 94754639 # DTB read hits system.cpu.dtb.read_misses 21 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 94754658 # DTB read accesses -system.cpu.dtb.write_hits 73521124 # DTB write hits +system.cpu.dtb.read_accesses 94754660 # DTB read accesses +system.cpu.dtb.write_hits 73521131 # DTB write hits system.cpu.dtb.write_misses 35 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 73521159 # DTB write accesses -system.cpu.dtb.data_hits 168275761 # DTB hits +system.cpu.dtb.write_accesses 73521166 # DTB write accesses +system.cpu.dtb.data_hits 168275770 # DTB hits system.cpu.dtb.data_misses 56 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 168275817 # DTB accesses -system.cpu.itb.fetch_hits 48611324 # ITB hits +system.cpu.dtb.data_accesses 168275826 # DTB accesses +system.cpu.itb.fetch_hits 48611322 # ITB hits system.cpu.itb.fetch_misses 44520 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 48655844 # ITB accesses +system.cpu.itb.fetch_accesses 48655842 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -307,13 +288,13 @@ system.cpu.numWorkItemsStarted 0 # nu system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.predictedTaken 29230505 # Number of Branches Predicted As Taken (True). system.cpu.branch_predictor.predictedNotTaken 24259168 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 280386579 # Number of Reads from Int. Register File +system.cpu.regfile_manager.intRegFileReads 280386572 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 159335859 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 439722438 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 119631950 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 439722431 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 119631955 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 100196481 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 219828431 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 100484574 # Number of Registers Read Through Forwarding Logic +system.cpu.regfile_manager.floatRegFileAccesses 219828436 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 100484576 # Number of Registers Read Through Forwarding Logic system.cpu.agen_unit.agens 168485322 # Number of Address Generations system.cpu.execution_unit.predictedTakenIncorrect 14315634 # Number of Branches Incorrectly Predicted As Taken. system.cpu.execution_unit.predictedNotTakenIncorrect 833366 # Number of Branches Incorrectly Predicted As Not Taken). @@ -324,12 +305,12 @@ system.cpu.execution_unit.executions 205475782 # Nu system.cpu.mult_div_unit.multiplies 2124323 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 279400617 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 279400810 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 7206 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 13545708 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 266306666 # Number of cycles cpu stages are processed. -system.cpu.activity 95.159695 # Percentage of cycles cpu is active +system.cpu.timesIdled 7266 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 13545705 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 266306669 # Number of cycles cpu stages are processed. +system.cpu.activity 95.159696 # Percentage of cycles cpu is active system.cpu.comLoads 94754489 # Number of Load instructions committed system.cpu.comStores 73520729 # Number of Store instructions committed system.cpu.comBranches 44587532 # Number of Branches instructions committed @@ -350,27 +331,27 @@ system.cpu.ipc_total 1.424553 # IP system.cpu.stage0.idleCycles 78104700 # Number of cycles 0 instructions are processed. system.cpu.stage0.runCycles 201747674 # Number of cycles 1+ instructions are processed. system.cpu.stage0.utilization 72.090750 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 107200641 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 172651733 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 61.693860 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 107200637 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 172651737 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 61.693862 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage2.idleCycles 102637143 # Number of cycles 0 instructions are processed. system.cpu.stage2.runCycles 177215231 # Number of cycles 1+ instructions are processed. system.cpu.stage2.utilization 63.324541 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 181107759 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 98744615 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 35.284537 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 90384394 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 189467980 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 67.702831 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 181107747 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 98744627 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 35.284541 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 90384400 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 189467974 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 67.702829 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.tags.replacements 1975 # number of replacements -system.cpu.icache.tags.tagsinuse 1830.939408 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 48606790 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1830.934233 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 48606787 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 3903 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 12453.699718 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 12453.698950 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1830.939408 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.894013 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.894013 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1830.934233 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.894011 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.894011 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1928 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 135 # Occupied blocks per task id @@ -378,44 +359,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 322 system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1366 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.941406 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 97226551 # Number of tag accesses -system.cpu.icache.tags.data_accesses 97226551 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 48606790 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 48606790 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 48606790 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 48606790 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 48606790 # number of overall hits -system.cpu.icache.overall_hits::total 48606790 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 4534 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 4534 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 4534 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 4534 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 4534 # number of overall misses -system.cpu.icache.overall_misses::total 4534 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 280061250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 280061250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 280061250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 280061250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 280061250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 280061250 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 48611324 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 48611324 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 48611324 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 48611324 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 48611324 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 48611324 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 97226547 # Number of tag accesses +system.cpu.icache.tags.data_accesses 97226547 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 48606787 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 48606787 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 48606787 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 48606787 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 48606787 # number of overall hits +system.cpu.icache.overall_hits::total 48606787 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 4535 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 4535 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 4535 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 4535 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 4535 # number of overall misses +system.cpu.icache.overall_misses::total 4535 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 279787250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 279787250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 279787250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 279787250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 279787250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 279787250 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 48611322 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 48611322 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 48611322 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 48611322 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 48611322 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 48611322 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000093 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000093 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000093 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000093 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000093 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000093 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61769.133216 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 61769.133216 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 61769.133216 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 61769.133216 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 61769.133216 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 61769.133216 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61695.093716 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 61695.093716 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 61695.093716 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 61695.093716 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 61695.093716 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 61695.093716 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 330 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked @@ -424,36 +405,36 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 110 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 631 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 631 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 631 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 631 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 631 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 631 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 632 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 632 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 632 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 632 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 632 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 632 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3903 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 3903 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 3903 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 3903 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 3903 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 3903 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 244179750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 244179750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 244179750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 244179750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 244179750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 244179750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 243875500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 243875500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 243875500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 243875500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 243875500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 243875500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000080 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000080 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000080 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 62562.067640 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 62562.067640 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 62562.067640 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 62562.067640 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 62562.067640 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 62562.067640 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 62484.114783 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 62484.114783 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 62484.114783 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 62484.114783 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 62484.114783 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 62484.114783 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.throughput 3981070 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 4850 # Transaction distribution @@ -471,21 +452,21 @@ system.cpu.toL2Bus.data_through_bus 557056 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 5001000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 6459750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 6445500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 6671999 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 6649999 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 3906.845611 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 3906.832917 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 753 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 4717 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.159635 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 370.534640 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2908.739390 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 627.571581 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 370.533355 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2908.730052 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 627.569510 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.011308 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.088768 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.088767 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.019152 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.119227 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 4717 # Occupied blocks per task id @@ -520,17 +501,17 @@ system.cpu.l2cache.demand_misses::total 7328 # nu system.cpu.l2cache.overall_misses::cpu.inst 3359 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 3969 # number of overall misses system.cpu.l2cache.overall_misses::total 7328 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 234790750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 62080250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 296871000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 227075250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 227075250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 234790750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 289155500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 523946250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 234790750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 289155500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 523946250 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 234486500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 61133000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 295619500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 230289500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 230289500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 234486500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 291422500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 525909000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 234486500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 291422500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 525909000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 3903 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 947 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 4850 # number of ReadReq accesses(hits+misses) @@ -555,17 +536,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.909745 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.860620 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.955925 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.909745 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69899.002679 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75340.109223 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 70970.834329 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72201.987281 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72201.987281 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69899.002679 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72853.489544 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 71499.215338 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69899.002679 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72853.489544 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 71499.215338 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69808.425127 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74190.533981 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 70671.647143 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73224.006359 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73224.006359 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69808.425127 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73424.666163 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 71767.057860 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69808.425127 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73424.666163 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 71767.057860 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -585,17 +566,17 @@ system.cpu.l2cache.demand_mshr_misses::total 7328 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3359 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 3969 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7328 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 192686250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 51812250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 244498500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 188269250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 188269250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 192686250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 240081500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 432767750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 192686250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 240081500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 432767750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 192420000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 50867000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 243287000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 191492500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 191492500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 192420000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 242359500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 434779500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 192420000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 242359500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 434779500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.860620 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.870116 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.862474 # mshr miss rate for ReadReq accesses @@ -607,27 +588,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.909745 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.860620 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.909745 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57364.170884 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62878.944175 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58450.513985 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59863.036566 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59863.036566 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57364.170884 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60489.166037 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59056.734443 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57364.170884 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60489.166037 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59056.734443 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57284.906222 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61731.796117 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58160.889314 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60887.917329 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60887.917329 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57284.906222 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61063.114135 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59331.263646 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57284.906222 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61063.114135 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59331.263646 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 764 # number of replacements -system.cpu.dcache.tags.tagsinuse 3284.890275 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 168254255 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 3284.879976 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168254239 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4152 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 40523.664499 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 40523.660645 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3284.890275 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.801975 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.801975 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 3284.879976 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.801973 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.801973 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3388 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id @@ -639,28 +620,28 @@ system.cpu.dcache.tags.tag_accesses 336554588 # Nu system.cpu.dcache.tags.data_accesses 336554588 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 94753181 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 94753181 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73501074 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73501074 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 168254255 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168254255 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168254255 # number of overall hits -system.cpu.dcache.overall_hits::total 168254255 # number of overall hits +system.cpu.dcache.WriteReq_hits::cpu.data 73501058 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73501058 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 168254239 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168254239 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168254239 # number of overall hits +system.cpu.dcache.overall_hits::total 168254239 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 1308 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 1308 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 19655 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 19655 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 20963 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 20963 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 20963 # number of overall misses -system.cpu.dcache.overall_misses::total 20963 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 88453749 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 88453749 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1129220750 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1129220750 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1217674499 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1217674499 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1217674499 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1217674499 # number of overall miss cycles +system.cpu.dcache.WriteReq_misses::cpu.data 19671 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 19671 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 20979 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 20979 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 20979 # number of overall misses +system.cpu.dcache.overall_misses::total 20979 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 87087749 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 87087749 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1166784250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1166784250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 1253871999 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1253871999 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1253871999 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1253871999 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 94754489 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 94754489 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) @@ -671,25 +652,25 @@ system.cpu.dcache.overall_accesses::cpu.data 168275218 system.cpu.dcache.overall_accesses::total 168275218 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000014 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000014 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000267 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000267 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000268 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000268 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000125 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000125 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000125 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000125 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67625.190367 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 67625.190367 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57452.085983 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 57452.085983 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 58086.843438 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 58086.843438 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 58086.843438 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 58086.843438 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 33688 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66580.847859 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 66580.847859 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59314.943318 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 59314.943318 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 59767.958387 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 59767.958387 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 59767.958387 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 59767.958387 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 33117 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 584 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 591 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 57.684932 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 56.035533 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -697,12 +678,12 @@ system.cpu.dcache.writebacks::writebacks 649 # nu system.cpu.dcache.writebacks::total 649 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 358 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 358 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16453 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16453 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 16811 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 16811 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 16811 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 16811 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16469 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16469 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 16827 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 16827 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 16827 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 16827 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 950 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 950 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3202 # number of WriteReq MSHR misses @@ -711,14 +692,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4152 system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 64535001 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 64535001 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 230815000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 230815000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 295350001 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 295350001 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 295350001 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 295350001 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 63587751 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 63587751 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 234030250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 234030250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 297618001 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 297618001 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 297618001 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 297618001 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses @@ -727,14 +708,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67931.580000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67931.580000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72084.634603 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72084.634603 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71134.393304 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 71134.393304 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71134.393304 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 71134.393304 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66934.474737 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66934.474737 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73088.772642 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73088.772642 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71680.636079 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 71680.636079 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71680.636079 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 71680.636079 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |