diff options
Diffstat (limited to 'tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt')
| -rw-r--r-- | tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt | 79 |
1 files changed, 65 insertions, 14 deletions
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt index 28e031d9f..06e2fa444 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt @@ -4,22 +4,29 @@ sim_seconds 0.141175 # Nu sim_ticks 141175129500 # Number of ticks simulated final_tick 141175129500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 60144 # Simulator instruction rate (inst/s) -host_op_rate 60144 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 21298240 # Simulator tick rate (ticks/s) -host_mem_usage 221000 # Number of bytes of host memory used -host_seconds 6628.49 # Real time elapsed on the host +host_inst_rate 110841 # Simulator instruction rate (inst/s) +host_op_rate 110841 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 39251086 # Simulator tick rate (ticks/s) +host_mem_usage 221340 # Number of bytes of host memory used +host_seconds 3596.72 # Real time elapsed on the host sim_insts 398664595 # Number of instructions simulated sim_ops 398664595 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 468992 # Number of bytes read from this memory -system.physmem.bytes_inst_read 214592 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 7328 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 3322058 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1520041 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 3322058 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 214592 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 254400 # Number of bytes read from this memory +system.physmem.bytes_read::total 468992 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 214592 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 214592 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3353 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3975 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7328 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1520041 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1802017 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3322058 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1520041 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1520041 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1520041 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1802017 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3322058 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -155,11 +162,17 @@ system.cpu.icache.demand_accesses::total 49111849 # nu system.cpu.icache.overall_accesses::cpu.inst 49111849 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 49111849 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000089 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000089 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000089 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000089 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000089 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000089 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48928.995434 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 48928.995434 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 48928.995434 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 48928.995434 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 48928.995434 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 48928.995434 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 45000 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -187,11 +200,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 185222000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 185222000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 185222000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000079 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000079 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000079 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 47480.645988 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 47480.645988 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 47480.645988 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 47480.645988 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47480.645988 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 47480.645988 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 764 # number of replacements system.cpu.dcache.tagsinuse 3284.843893 # Cycle average of tags in use @@ -235,13 +254,21 @@ system.cpu.dcache.demand_accesses::total 168275218 # nu system.cpu.dcache.overall_accesses::cpu.data 168275218 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 168275218 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000013 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000013 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000164 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000164 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000079 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000079 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000079 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000079 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 52139.705882 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 52139.705882 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52061.154965 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 52061.154965 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 52068.406365 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 52068.406365 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 52068.406365 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 52068.406365 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 82410500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -277,13 +304,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 215717000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 215717000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 215717000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000044 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48610.526316 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48610.526316 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52947.220487 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52947.220487 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51954.961464 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 51954.961464 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51954.961464 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 51954.961464 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 13 # number of replacements system.cpu.l2cache.tagsinuse 3896.685167 # Cycle average of tags in use @@ -348,18 +383,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 4152 system.cpu.l2cache.overall_accesses::total 8053 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.859523 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.876452 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.862830 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.981279 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.981279 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.859523 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.957370 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.909971 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.859523 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.957370 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.909971 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52322.696093 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52557.228916 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52369.232608 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52454.848967 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52454.848967 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52322.696093 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52476.226415 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52405.977074 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52322.696093 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52476.226415 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52405.977074 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -392,18 +435,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 160275000 system.cpu.l2cache.overall_mshr_miss_latency::total 294866000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.859523 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.876452 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.862830 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.981279 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.981279 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.859523 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.957370 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.909971 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.859523 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.957370 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.909971 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40140.471220 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40382.530120 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40188.501076 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40304.451510 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40304.451510 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40140.471220 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40320.754717 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40238.264192 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40140.471220 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40320.754717 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40238.264192 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |