diff options
Diffstat (limited to 'tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt')
| -rw-r--r-- | tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt | 510 |
1 files changed, 256 insertions, 254 deletions
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt index 4b6099b52..16a9ab312 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.139926 # Number of seconds simulated -sim_ticks 139926186500 # Number of ticks simulated -final_tick 139926186500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.139925 # Number of seconds simulated +sim_ticks 139925460500 # Number of ticks simulated +final_tick 139925460500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 124689 # Simulator instruction rate (inst/s) -host_op_rate 124689 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 43764124 # Simulator tick rate (ticks/s) -host_mem_usage 271420 # Number of bytes of host memory used -host_seconds 3197.28 # Real time elapsed on the host +host_inst_rate 120046 # Simulator instruction rate (inst/s) +host_op_rate 120046 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 42134532 # Simulator tick rate (ticks/s) +host_mem_usage 271408 # Number of bytes of host memory used +host_seconds 3320.92 # Real time elapsed on the host sim_insts 398664595 # Number of instructions simulated sim_ops 398664595 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 214976 # Nu system.physmem.num_reads::cpu.inst 3359 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 3969 # Number of read requests responded to by this memory system.physmem.num_reads::total 7328 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1536353 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1815357 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3351710 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1536353 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1536353 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1536353 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1815357 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3351710 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1536361 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1815367 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3351727 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1536361 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1536361 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1536361 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1815367 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3351727 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 7328 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 7328 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 139926113000 # Total gap between requests +system.physmem.totGap 139925387000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,11 +90,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4589 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1831 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 611 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 237 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 59 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4503 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1916 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 608 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 242 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 58 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -186,28 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 558 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 480.917563 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 280.270360 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 415.877438 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 147 26.34% 26.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 107 19.18% 45.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 50 8.96% 54.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 28 5.02% 59.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 15 2.69% 62.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 15 2.69% 64.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 7 1.25% 66.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5 0.90% 67.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 184 32.97% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 558 # Bytes accessed per row activation -system.physmem.totQLat 59527000 # Total ticks spent queuing -system.physmem.totMemAccLat 199924500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 1345 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 345.790335 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 209.990258 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 340.082178 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 408 30.33% 30.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 331 24.61% 54.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 167 12.42% 67.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 84 6.25% 73.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 65 4.83% 78.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 45 3.35% 81.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 30 2.23% 84.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 29 2.16% 86.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 186 13.83% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1345 # Bytes accessed per row activation +system.physmem.totQLat 64590750 # Total ticks spent queuing +system.physmem.totMemAccLat 201990750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 36640000 # Total ticks spent in databus transfers -system.physmem.totBankLat 103757500 # Total ticks spent accessing banks -system.physmem.avgQLat 8123.23 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 14159.05 # Average bank access latency per DRAM burst +system.physmem.avgQLat 8814.24 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27282.27 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 27564.24 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.35 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.35 # Average system read bandwidth in MiByte/s @@ -218,14 +216,18 @@ system.physmem.busUtilRead 0.03 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 5962 # Number of row buffer hits during reads +system.physmem.readRowHits 5972 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.36 # Row buffer hit rate for reads +system.physmem.readRowHitRate 81.50 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 19094720.66 # Average gap between requests -system.physmem.pageHitRate 81.36 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.43 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 3351710 # Throughput (bytes/s) +system.physmem.avgGap 19094621.59 # Average gap between requests +system.physmem.pageHitRate 81.50 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 133853003250 # Time in different power states +system.physmem.memoryStateTime::REF 4672200000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 1393983000 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.membus.throughput 3351727 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 4183 # Transaction distribution system.membus.trans_dist::ReadResp 4183 # Transaction distribution system.membus.trans_dist::ReadExReq 3145 # Transaction distribution @@ -236,40 +238,40 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 468992 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 468992 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 8743500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 8819000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 68133000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 68224500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 53489673 # Number of BP lookups +system.cpu.branchPred.lookups 53489674 # Number of BP lookups system.cpu.branchPred.condPredicted 30685396 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 15149659 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 32882350 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 32882351 # Number of BTB lookups system.cpu.branchPred.BTBHits 15212538 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 46.263537 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 46.263535 # BTB Hit Percentage system.cpu.branchPred.usedRAS 8007516 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 20 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 94754639 # DTB read hits +system.cpu.dtb.read_hits 94754638 # DTB read hits system.cpu.dtb.read_misses 21 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 94754660 # DTB read accesses -system.cpu.dtb.write_hits 73521131 # DTB write hits +system.cpu.dtb.read_accesses 94754659 # DTB read accesses +system.cpu.dtb.write_hits 73521127 # DTB write hits system.cpu.dtb.write_misses 35 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 73521166 # DTB write accesses -system.cpu.dtb.data_hits 168275770 # DTB hits +system.cpu.dtb.write_accesses 73521162 # DTB write accesses +system.cpu.dtb.data_hits 168275765 # DTB hits system.cpu.dtb.data_misses 56 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 168275826 # DTB accesses -system.cpu.itb.fetch_hits 48611322 # ITB hits +system.cpu.dtb.data_accesses 168275821 # DTB accesses +system.cpu.itb.fetch_hits 48611320 # ITB hits system.cpu.itb.fetch_misses 44520 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 48655842 # ITB accesses +system.cpu.itb.fetch_accesses 48655840 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -283,18 +285,18 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 279852374 # number of cpu cycles simulated +system.cpu.numCycles 279850922 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.predictedTaken 29230505 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 24259168 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 280386572 # Number of Reads from Int. Register File +system.cpu.branch_predictor.predictedNotTaken 24259169 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 280386575 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 159335859 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 439722431 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 439722434 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 119631955 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 100196481 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 219828436 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 100484576 # Number of Registers Read Through Forwarding Logic +system.cpu.regfile_manager.regForwards 100484573 # Number of Registers Read Through Forwarding Logic system.cpu.agen_unit.agens 168485322 # Number of Address Generations system.cpu.execution_unit.predictedTakenIncorrect 14315634 # Number of Branches Incorrectly Predicted As Taken. system.cpu.execution_unit.predictedNotTakenIncorrect 833366 # Number of Branches Incorrectly Predicted As Not Taken). @@ -305,12 +307,12 @@ system.cpu.execution_unit.executions 205475782 # Nu system.cpu.mult_div_unit.multiplies 2124323 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 279400810 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 279400656 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 7266 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 13545705 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 266306669 # Number of cycles cpu stages are processed. -system.cpu.activity 95.159696 # Percentage of cycles cpu is active +system.cpu.timesIdled 7212 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 13544259 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 266306663 # Number of cycles cpu stages are processed. +system.cpu.activity 95.160188 # Percentage of cycles cpu is active system.cpu.comLoads 94754489 # Number of Load instructions committed system.cpu.comStores 73520729 # Number of Store instructions committed system.cpu.comBranches 44587532 # Number of Branches instructions committed @@ -322,81 +324,81 @@ system.cpu.committedInsts 398664595 # Nu system.cpu.committedOps 398664595 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 398664595 # Number of Instructions committed (Total) -system.cpu.cpi 0.701974 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.701971 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.701974 # CPI: Total CPI of All Threads -system.cpu.ipc 1.424553 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.701971 # CPI: Total CPI of All Threads +system.cpu.ipc 1.424561 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.424553 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 78104700 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 201747674 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 72.090750 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 107200637 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 172651737 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 61.693862 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 102637143 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 177215231 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 63.324541 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 181107747 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 98744627 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 35.284541 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 90384400 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 189467974 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 67.702829 # Percentage of cycles stage was utilized (processing insts). +system.cpu.ipc_total 1.424561 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 78103252 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 201747670 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 72.091122 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 107199191 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 172651731 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 61.694180 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 102635700 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 177215222 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 63.324866 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 181106302 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 98744620 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 35.284722 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 90382943 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 189467979 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 67.703182 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.tags.replacements 1975 # number of replacements -system.cpu.icache.tags.tagsinuse 1830.934233 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 48606787 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1830.939956 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 48606789 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 3903 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 12453.698950 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 12453.699462 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1830.934233 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.894011 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.894011 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1830.939956 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.894014 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.894014 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1928 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 135 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 322 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1366 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.941406 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 97226547 # Number of tag accesses -system.cpu.icache.tags.data_accesses 97226547 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 48606787 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 48606787 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 48606787 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 48606787 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 48606787 # number of overall hits -system.cpu.icache.overall_hits::total 48606787 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 4535 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 4535 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 4535 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 4535 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 4535 # number of overall misses -system.cpu.icache.overall_misses::total 4535 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 279787250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 279787250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 279787250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 279787250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 279787250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 279787250 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 48611322 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 48611322 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 48611322 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 48611322 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 48611322 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 48611322 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 97226543 # Number of tag accesses +system.cpu.icache.tags.data_accesses 97226543 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 48606789 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 48606789 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 48606789 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 48606789 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 48606789 # number of overall hits +system.cpu.icache.overall_hits::total 48606789 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 4531 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 4531 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 4531 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 4531 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 4531 # number of overall misses +system.cpu.icache.overall_misses::total 4531 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 279235250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 279235250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 279235250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 279235250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 279235250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 279235250 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 48611320 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 48611320 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 48611320 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 48611320 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 48611320 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 48611320 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000093 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000093 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000093 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000093 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000093 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000093 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61695.093716 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 61695.093716 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 61695.093716 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 61695.093716 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 61695.093716 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 61695.093716 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61627.731185 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 61627.731185 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 61627.731185 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 61627.731185 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 61627.731185 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 61627.731185 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 330 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked @@ -405,38 +407,38 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 110 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 632 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 632 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 632 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 632 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 632 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 632 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 628 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 628 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 628 # 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number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 243875500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 243875500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 243875500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 243851250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 243851250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 243851250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 243851250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 243851250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 243851250 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000080 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000080 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000080 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 62484.114783 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 62484.114783 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 62484.114783 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 62484.114783 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 62484.114783 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 62484.114783 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 62477.901614 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 62477.901614 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 62477.901614 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 62477.901614 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 62477.901614 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 62477.901614 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 3981070 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 3981091 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 4850 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 4850 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 649 # Transaction distribution @@ -452,26 +454,26 @@ system.cpu.toL2Bus.data_through_bus 557056 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 5001000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 6445500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 6455750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 6649999 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 6676249 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 3906.832917 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 3906.848534 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 753 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 4717 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.159635 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 370.533355 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2908.730052 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 627.569510 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 370.535307 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2908.741321 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 627.571906 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.011308 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.088767 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.088768 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.019152 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.119227 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.119228 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 4717 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 102 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 127 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 98 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 564 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3928 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.143951 # Percentage of cache occupancy per task id @@ -501,17 +503,17 @@ system.cpu.l2cache.demand_misses::total 7328 # nu system.cpu.l2cache.overall_misses::cpu.inst 3359 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 3969 # number of overall misses system.cpu.l2cache.overall_misses::total 7328 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 234486500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 61133000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 295619500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 230289500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 230289500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 234486500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 291422500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 525909000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 234486500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 291422500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 525909000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 234462250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 60397500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 294859750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 231906750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 231906750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 234462250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 292304250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 526766500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 234462250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 292304250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 526766500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 3903 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 947 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 4850 # number of ReadReq accesses(hits+misses) @@ -536,17 +538,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.909745 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.860620 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.955925 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.909745 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69808.425127 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74190.533981 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 70671.647143 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73224.006359 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73224.006359 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69808.425127 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73424.666163 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 71767.057860 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69808.425127 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73424.666163 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 71767.057860 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69801.205716 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73297.936893 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 70490.019125 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73738.235294 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73738.235294 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69801.205716 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73646.825397 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 71884.074782 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69801.205716 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73646.825397 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 71884.074782 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -566,17 +568,17 @@ system.cpu.l2cache.demand_mshr_misses::total 7328 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3359 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 3969 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7328 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 192420000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 50867000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 243287000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 191492500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 191492500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 192420000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 242359500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 434779500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 192420000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 242359500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 434779500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 192372250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 50131500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 242503750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 193005250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 193005250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 192372250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 243136750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 435509000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 192372250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 243136750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 435509000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.860620 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.870116 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.862474 # mshr miss rate for ReadReq accesses @@ -588,27 +590,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.909745 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.860620 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.909745 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57284.906222 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61731.796117 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58160.889314 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60887.917329 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60887.917329 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57284.906222 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61063.114135 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59331.263646 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57284.906222 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61063.114135 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59331.263646 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57270.690682 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60839.199029 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57973.643318 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61368.918919 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61368.918919 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57270.690682 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61258.944318 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59430.813319 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57270.690682 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61258.944318 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59430.813319 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 764 # number of replacements -system.cpu.dcache.tags.tagsinuse 3284.879976 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 3284.892778 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 168254239 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4152 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 40523.660645 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3284.879976 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.801973 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.801973 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 3284.892778 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.801976 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.801976 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3388 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id @@ -618,30 +620,30 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 3109 system.cpu.dcache.tags.occ_task_id_percent::1024 0.827148 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 336554588 # Number of tag accesses system.cpu.dcache.tags.data_accesses 336554588 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 94753181 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 94753181 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73501058 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73501058 # number of WriteReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 94753183 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 94753183 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 73501056 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73501056 # number of WriteReq hits system.cpu.dcache.demand_hits::cpu.data 168254239 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 168254239 # number of demand (read+write) hits system.cpu.dcache.overall_hits::cpu.data 168254239 # number of overall hits system.cpu.dcache.overall_hits::total 168254239 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1308 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1308 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 19671 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 19671 # number of WriteReq misses +system.cpu.dcache.ReadReq_misses::cpu.data 1306 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1306 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 19673 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 19673 # number of WriteReq misses system.cpu.dcache.demand_misses::cpu.data 20979 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 20979 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 20979 # number of overall misses system.cpu.dcache.overall_misses::total 20979 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 87087749 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 87087749 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1166784250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1166784250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1253871999 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1253871999 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1253871999 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1253871999 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 86414249 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 86414249 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1153377000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1153377000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 1239791249 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1239791249 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1239791249 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1239791249 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 94754489 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 94754489 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) @@ -658,28 +660,28 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000125 system.cpu.dcache.demand_miss_rate::total 0.000125 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000125 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000125 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66580.847859 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 66580.847859 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59314.943318 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 59314.943318 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 59767.958387 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 59767.958387 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 59767.958387 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 59767.958387 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 33117 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66167.112557 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 66167.112557 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 58627.408123 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 58627.408123 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 59096.775299 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 59096.775299 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 59096.775299 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 59096.775299 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 33700 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 591 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 588 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 56.035533 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 57.312925 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 649 # number of writebacks system.cpu.dcache.writebacks::total 649 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 358 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 358 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16469 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16469 # number of WriteReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 356 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 356 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16471 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16471 # number of WriteReq MSHR hits system.cpu.dcache.demand_mshr_hits::cpu.data 16827 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 16827 # number of demand (read+write) MSHR hits system.cpu.dcache.overall_mshr_hits::cpu.data 16827 # number of overall MSHR hits @@ -692,14 +694,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4152 system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 63587751 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 63587751 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 234030250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 234030250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 297618001 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 297618001 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 297618001 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 297618001 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 62852251 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 62852251 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 235649500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 235649500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 298501751 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 298501751 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 298501751 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 298501751 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses @@ -708,14 +710,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66934.474737 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66934.474737 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73088.772642 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73088.772642 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71680.636079 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 71680.636079 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71680.636079 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 71680.636079 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66160.264211 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66160.264211 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73594.472205 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73594.472205 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71893.485308 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 71893.485308 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71893.485308 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 71893.485308 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |