diff options
Diffstat (limited to 'tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt')
| -rw-r--r-- | tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt | 710 |
1 files changed, 355 insertions, 355 deletions
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt index 1a7177e69..988455083 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt @@ -1,52 +1,52 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.226045 # Number of seconds simulated -sim_ticks 226044973500 # Number of ticks simulated -final_tick 226044973500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.225711 # Number of seconds simulated +sim_ticks 225710988500 # Number of ticks simulated +final_tick 225710988500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 304016 # Simulator instruction rate (inst/s) -host_op_rate 304016 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 172378586 # Simulator tick rate (ticks/s) -host_mem_usage 302856 # Number of bytes of host memory used -host_seconds 1311.33 # Real time elapsed on the host +host_inst_rate 225638 # Simulator instruction rate (inst/s) +host_op_rate 225638 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 127748919 # Simulator tick rate (ticks/s) +host_mem_usage 297512 # Number of bytes of host memory used +host_seconds 1766.83 # Real time elapsed on the host sim_insts 398664665 # Number of instructions simulated sim_ops 398664665 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 249344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 249088 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 254592 # Number of bytes read from this memory -system.physmem.bytes_read::total 503936 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 249344 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 249344 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3896 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 503680 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 249088 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 249088 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3892 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 3978 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7874 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1103073 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1126289 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2229362 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1103073 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1103073 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1103073 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1126289 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2229362 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7874 # Number of read requests accepted +system.physmem.num_reads::total 7870 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1103571 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1127956 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2231526 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1103571 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1103571 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1103571 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1127956 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2231526 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7870 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 7874 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 7870 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 503936 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 503680 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 503936 # Total read bytes from the system interface side +system.physmem.bytesReadSys 503680 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 551 # Per bank write bursts +system.physmem.perBankRdBursts::0 549 # Per bank write bursts system.physmem.perBankRdBursts::1 676 # Per bank write bursts system.physmem.perBankRdBursts::2 471 # Per bank write bursts system.physmem.perBankRdBursts::3 633 # Per bank write bursts -system.physmem.perBankRdBursts::4 475 # Per bank write bursts -system.physmem.perBankRdBursts::5 478 # Per bank write bursts +system.physmem.perBankRdBursts::4 474 # Per bank write bursts +system.physmem.perBankRdBursts::5 477 # Per bank write bursts system.physmem.perBankRdBursts::6 563 # Per bank write bursts system.physmem.perBankRdBursts::7 560 # Per bank write bursts system.physmem.perBankRdBursts::8 470 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 226044886000 # Total gap between requests +system.physmem.totGap 225710901000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 7874 # Read request sizes (log2) +system.physmem.readPktSize::6 7870 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,8 +90,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 6812 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 977 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 6816 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 969 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 85 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1551 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 323.878788 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 193.961760 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 330.450478 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 540 34.82% 34.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 341 21.99% 56.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 198 12.77% 69.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 105 6.77% 76.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 68 4.38% 80.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 43 2.77% 83.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 33 2.13% 85.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 36 2.32% 87.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 187 12.06% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1551 # Bytes accessed per row activation -system.physmem.totQLat 53691750 # Total ticks spent queuing -system.physmem.totMemAccLat 201329250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 39370000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6818.87 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1545 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 324.680906 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 194.047178 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 332.516800 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 535 34.63% 34.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 349 22.59% 57.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 192 12.43% 69.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 105 6.80% 76.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 65 4.21% 80.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 39 2.52% 83.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 33 2.14% 85.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 33 2.14% 87.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 194 12.56% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1545 # Bytes accessed per row activation +system.physmem.totQLat 52849750 # Total ticks spent queuing +system.physmem.totMemAccLat 200412250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 39350000 # Total ticks spent in databus transfers +system.physmem.avgQLat 6715.34 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25568.87 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25465.34 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.23 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.23 # Average system read bandwidth in MiByte/s @@ -216,70 +216,70 @@ system.physmem.busUtilRead 0.02 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 6316 # Number of row buffer hits during reads +system.physmem.readRowHits 6317 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.21 # Row buffer hit rate for reads +system.physmem.readRowHitRate 80.27 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 28707757.94 # Average gap between requests -system.physmem.pageHitRate 80.21 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 6811560 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3716625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 34210800 # Energy for read commands per rank (pJ) +system.physmem.avgGap 28679911.18 # Average gap between requests +system.physmem.pageHitRate 80.27 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 6743520 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3679500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 34132800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 14764005360 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 5854324365 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 130490358000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 151153426710 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.693587 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 217080502500 # Time in different power states -system.physmem_0.memoryStateTime::REF 7548060000 # Time in different power states +system.physmem_0.refreshEnergy 14742137280 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 5830950375 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 130309976250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 150927619725 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.685069 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 216780859000 # Time in different power states +system.physmem_0.memoryStateTime::REF 7536880000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1414335000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1390733500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 4914000 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2681250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 27011400 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 4936680 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2693625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 27003600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 14764005360 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 5569701705 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 130740027000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 151108340715 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.494129 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 217498306250 # Time in different power states -system.physmem_1.memoryStateTime::REF 7548060000 # Time in different power states +system.physmem_1.refreshEnergy 14742137280 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 5568136200 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 130540515000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 150885422385 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.498114 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 217165940000 # Time in different power states +system.physmem_1.memoryStateTime::REF 7536880000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 997097750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1005282000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 46270920 # Number of BP lookups -system.cpu.branchPred.condPredicted 26727376 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1017825 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 25620092 # Number of BTB lookups -system.cpu.branchPred.BTBHits 21360645 # Number of BTB hits +system.cpu.branchPred.lookups 46155674 # Number of BP lookups +system.cpu.branchPred.condPredicted 26673496 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 964868 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 25433927 # Number of BTB lookups +system.cpu.branchPred.BTBHits 21299796 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 83.374584 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 8341957 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 323 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 83.745605 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 8306241 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 322 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 95612152 # DTB read hits -system.cpu.dtb.read_misses 116 # DTB read misses +system.cpu.dtb.read_hits 95501420 # DTB read hits +system.cpu.dtb.read_misses 115 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 95612268 # DTB read accesses -system.cpu.dtb.write_hits 73605970 # DTB write hits -system.cpu.dtb.write_misses 858 # DTB write misses +system.cpu.dtb.read_accesses 95501535 # DTB read accesses +system.cpu.dtb.write_hits 73594615 # DTB write hits +system.cpu.dtb.write_misses 852 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 73606828 # DTB write accesses -system.cpu.dtb.data_hits 169218122 # DTB hits -system.cpu.dtb.data_misses 974 # DTB misses +system.cpu.dtb.write_accesses 73595467 # DTB write accesses +system.cpu.dtb.data_hits 169096035 # DTB hits +system.cpu.dtb.data_misses 967 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 169219096 # DTB accesses -system.cpu.itb.fetch_hits 98739640 # ITB hits -system.cpu.itb.fetch_misses 1232 # ITB misses +system.cpu.dtb.data_accesses 169097002 # DTB accesses +system.cpu.itb.fetch_hits 98403660 # ITB hits +system.cpu.itb.fetch_misses 1242 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 98740872 # ITB accesses +system.cpu.itb.fetch_accesses 98404902 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -293,83 +293,83 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 452089947 # number of cpu cycles simulated +system.cpu.numCycles 451421977 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 398664665 # Number of instructions committed system.cpu.committedOps 398664665 # Number of ops (including micro ops) committed -system.cpu.discardedOps 4488161 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 4268732 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.134011 # CPI: cycles per instruction -system.cpu.ipc 0.881826 # IPC: instructions per cycle -system.cpu.tickCycles 448265885 # Number of cycles that the object actually ticked -system.cpu.idleCycles 3824062 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.132335 # CPI: cycles per instruction +system.cpu.ipc 0.883131 # IPC: instructions per cycle +system.cpu.tickCycles 447606238 # Number of cycles that the object actually ticked +system.cpu.idleCycles 3815739 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 771 # number of replacements -system.cpu.dcache.tags.tagsinuse 3291.715048 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 168032888 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 3291.720604 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 167948311 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4165 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 40344.030732 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 40323.724130 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3291.715048 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.803641 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.803641 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 3291.720604 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.803643 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.803643 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3394 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 216 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 3114 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 3113 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.828613 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 336084171 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 336084171 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 94518093 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 94518093 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73514795 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73514795 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 168032888 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168032888 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168032888 # number of overall hits -system.cpu.dcache.overall_hits::total 168032888 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1180 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1180 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5935 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5935 # number of WriteReq misses +system.cpu.dcache.tags.tag_accesses 335915017 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 335915017 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 94433513 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 94433513 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 73514798 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73514798 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 167948311 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 167948311 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 167948311 # number of overall hits +system.cpu.dcache.overall_hits::total 167948311 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1183 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1183 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5932 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5932 # number of WriteReq misses system.cpu.dcache.demand_misses::cpu.data 7115 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 7115 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 7115 # number of overall misses system.cpu.dcache.overall_misses::total 7115 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 87916000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 87916000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 428863500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 428863500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 516779500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 516779500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 516779500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 516779500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 94519273 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 94519273 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 87406500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 87406500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 430164000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 430164000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 517570500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 517570500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 517570500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 517570500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 94434696 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 94434696 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520730 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 73520730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 168040003 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 168040003 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 168040003 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 168040003 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000012 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000012 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 167955426 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 167955426 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 167955426 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 167955426 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000013 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000013 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000081 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.000081 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000042 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000042 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000042 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000042 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 74505.084746 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 74505.084746 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72260.067397 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 72260.067397 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 72632.396346 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 72632.396346 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 72632.396346 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 72632.396346 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73885.460693 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 73885.460693 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72515.846258 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 72515.846258 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 72743.569923 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 72743.569923 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 72743.569923 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 72743.569923 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -380,10 +380,10 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 654 # number of writebacks system.cpu.dcache.writebacks::total 654 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 211 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 211 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2739 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2739 # number of WriteReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 214 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 214 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2736 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2736 # number of WriteReq MSHR hits system.cpu.dcache.demand_mshr_hits::cpu.data 2950 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 2950 # number of demand (read+write) MSHR hits system.cpu.dcache.overall_mshr_hits::cpu.data 2950 # number of overall MSHR hits @@ -396,14 +396,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4165 system.cpu.dcache.demand_mshr_misses::total 4165 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4165 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4165 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 71088500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 71088500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 239432500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 239432500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 310521000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 310521000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 310521000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 310521000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 70744000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 70744000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 240380000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 240380000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 311124000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 311124000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 311124000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 311124000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for WriteReq accesses @@ -412,68 +412,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73362.745098 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73362.745098 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74916.301627 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74916.301627 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74554.861945 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 74554.861945 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74554.861945 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 74554.861945 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73007.223942 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73007.223942 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75212.765957 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75212.765957 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74699.639856 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 74699.639856 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74699.639856 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 74699.639856 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 3197 # number of replacements -system.cpu.icache.tags.tagsinuse 1918.682192 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 98734465 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 5175 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 19079.123671 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 3187 # number of replacements +system.cpu.icache.tags.tagsinuse 1919.659270 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 98398495 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 5165 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 19051.015489 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1918.682192 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.936857 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.936857 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1919.659270 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.937334 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.937334 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1978 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 207 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 203 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 397 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1281 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1282 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.965820 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 197484455 # Number of tag accesses -system.cpu.icache.tags.data_accesses 197484455 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 98734465 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 98734465 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 98734465 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 98734465 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 98734465 # number of overall hits -system.cpu.icache.overall_hits::total 98734465 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5175 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5175 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5175 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5175 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5175 # number of overall misses -system.cpu.icache.overall_misses::total 5175 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 319209000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 319209000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 319209000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 319209000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 319209000 # 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number of demand (read+write) hits +system.cpu.icache.demand_hits::total 98398495 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 98398495 # number of overall hits +system.cpu.icache.overall_hits::total 98398495 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5165 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5165 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5165 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5165 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5165 # number of overall misses +system.cpu.icache.overall_misses::total 5165 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 317382500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 317382500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 317382500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 317382500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 317382500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 317382500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 98403660 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 98403660 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 98403660 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 98403660 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 98403660 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 98403660 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000052 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000052 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000052 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000052 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000052 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000052 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61682.898551 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 61682.898551 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 61682.898551 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 61682.898551 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 61682.898551 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 61682.898551 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61448.693127 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 61448.693127 # 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number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 253881000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 262496000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 516377000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::total 7870 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 203693000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 203693000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 252182500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 252182500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 59406500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 59406500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 252182500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 263099500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 515282000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 252182500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 263099500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 515282000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.980926 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.980926 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.752850 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.752850 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.753533 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.753533 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.869700 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.869700 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.752850 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.753533 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.955102 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.843041 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.752850 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.843516 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.753533 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955102 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.843041 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64630.379343 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64630.379343 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65164.527721 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65164.527721 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71046.967895 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71046.967895 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65164.527721 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65986.928105 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65580.010160 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65164.527721 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65986.928105 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65580.010160 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.843516 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64932.419509 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64932.419509 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64795.092497 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64795.092497 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70637.931034 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70637.931034 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64795.092497 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66138.637506 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65474.205845 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64795.092497 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66138.637506 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65474.205845 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadResp 6142 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 6132 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 654 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 3314 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 3304 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 3198 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 3198 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 5175 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 5165 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 967 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 13547 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 13517 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9101 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 22648 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 331200 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 22618 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 330560 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 308416 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 639616 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 638976 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 13308 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 13288 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 13308 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 13288 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 13308 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 7308000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 13288 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 7298000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 7762500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 7747500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 6247999 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.trans_dist::ReadResp 4737 # Transaction distribution +system.membus.trans_dist::ReadResp 4733 # Transaction distribution system.membus.trans_dist::ReadExReq 3137 # Transaction distribution system.membus.trans_dist::ReadExResp 3137 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 4737 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15748 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 15748 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 503936 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 503936 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 4733 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15740 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 15740 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 503680 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 503680 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 7874 # Request fanout histogram +system.membus.snoop_fanout::samples 7870 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 7874 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 7870 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 7874 # Request fanout histogram -system.membus.reqLayer0.occupancy 9183500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 7870 # Request fanout histogram +system.membus.reqLayer0.occupancy 9171000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 41813250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 41782250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |