diff options
Diffstat (limited to 'tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt')
| -rw-r--r-- | tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt | 19 |
1 files changed, 5 insertions, 14 deletions
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt index 19e47bc98..2db84b627 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.223533 # Nu sim_ticks 223532962500 # Number of ticks simulated final_tick 223532962500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 354404 # Simulator instruction rate (inst/s) -host_op_rate 354404 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 198715635 # Simulator tick rate (ticks/s) -host_mem_usage 258580 # Number of bytes of host memory used -host_seconds 1124.89 # Real time elapsed on the host +host_inst_rate 349202 # Simulator instruction rate (inst/s) +host_op_rate 349202 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 195799110 # Simulator tick rate (ticks/s) +host_mem_usage 258576 # Number of bytes of host memory used +host_seconds 1141.64 # Real time elapsed on the host sim_insts 398664665 # Number of instructions simulated sim_ops 398664665 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -415,8 +415,6 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 654 # number of writebacks system.cpu.dcache.writebacks::total 654 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 214 # number of ReadReq MSHR hits @@ -459,7 +457,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74596.158463 system.cpu.dcache.demand_avg_mshr_miss_latency::total 74596.158463 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74596.158463 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 74596.158463 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 3190 # number of replacements system.cpu.icache.tags.tagsinuse 1919.630000 # Cycle average of tags in use system.cpu.icache.tags.total_refs 96785699 # Total number of references to valid blocks. @@ -519,8 +516,6 @@ system.cpu.icache.blocked::no_mshrs 0 # nu system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks::writebacks 3190 # number of writebacks system.cpu.icache.writebacks::total 3190 # number of writebacks system.cpu.icache.ReadReq_mshr_misses::cpu.inst 5168 # number of ReadReq MSHR misses @@ -547,7 +542,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60281.830495 system.cpu.icache.demand_avg_mshr_miss_latency::total 60281.830495 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60281.830495 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 60281.830495 # average overall mshr miss latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 4421.902302 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 4798 # Total number of references to valid blocks. @@ -655,8 +649,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3137 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 3137 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3892 # number of ReadCleanReq MSHR misses @@ -705,7 +697,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65328.398983 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64610.868448 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66030.417295 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65328.398983 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 13294 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 3961 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. |