diff options
Diffstat (limited to 'tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt')
| -rw-r--r-- | tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt | 527 |
1 files changed, 266 insertions, 261 deletions
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt index b65c3962a..6b30c3cf1 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.233526 # Number of seconds simulated -sim_ticks 233525789500 # Number of ticks simulated -final_tick 233525789500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.233534 # Number of seconds simulated +sim_ticks 233533887500 # Number of ticks simulated +final_tick 233533887500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 279317 # Simulator instruction rate (inst/s) -host_op_rate 279317 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 163615265 # Simulator tick rate (ticks/s) -host_mem_usage 255720 # Number of bytes of host memory used -host_seconds 1427.29 # Real time elapsed on the host +host_inst_rate 225573 # Simulator instruction rate (inst/s) +host_op_rate 225573 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 132138421 # Simulator tick rate (ticks/s) +host_mem_usage 260868 # Number of bytes of host memory used +host_seconds 1767.34 # Real time elapsed on the host sim_insts 398664651 # Number of instructions simulated sim_ops 398664651 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 233525789500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 249280 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 254592 # Number of bytes read from this memory system.physmem.bytes_read::total 503872 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 249280 # Nu system.physmem.num_reads::cpu.inst 3895 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 3978 # Number of read requests responded to by this memory system.physmem.num_reads::total 7873 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1067462 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1090209 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2157672 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1067462 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1067462 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1067462 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1090209 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2157672 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1067425 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1090172 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2157597 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1067425 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1067425 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1067425 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1090172 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2157597 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 7873 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 7873 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 233525688500 # Total gap between requests +system.physmem.totGap 233533785500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -91,9 +91,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 6857 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 948 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 68 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 6853 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 951 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 69 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -187,26 +187,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1541 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 326.852693 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 195.480715 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 331.694198 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 535 34.72% 34.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 344 22.32% 57.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 186 12.07% 69.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 104 6.75% 75.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 66 4.28% 80.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 53 3.44% 83.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 28 1.82% 85.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 39 2.53% 87.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 186 12.07% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1541 # Bytes accessed per row activation -system.physmem.totQLat 52273750 # Total ticks spent queuing -system.physmem.totMemAccLat 199892500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 1544 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 326.051813 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 195.846863 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 329.937998 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 532 34.46% 34.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 344 22.28% 56.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 193 12.50% 69.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 103 6.67% 75.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 73 4.73% 80.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 45 2.91% 83.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 32 2.07% 85.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 36 2.33% 87.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 186 12.05% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1544 # Bytes accessed per row activation +system.physmem.totQLat 53440000 # Total ticks spent queuing +system.physmem.totMemAccLat 201058750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 39365000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6639.62 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6787.76 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25389.62 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25537.76 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.16 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.16 # Average system read bandwidth in MiByte/s @@ -217,75 +217,75 @@ system.physmem.busUtilRead 0.02 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 6330 # Number of row buffer hits during reads +system.physmem.readRowHits 6327 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.40 # Row buffer hit rate for reads +system.physmem.readRowHitRate 80.36 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 29661588.78 # Average gap between requests -system.physmem.pageHitRate 80.40 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 6804000 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3712500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 34327800 # Energy for read commands per rank (pJ) +system.physmem.avgGap 29662617.24 # Average gap between requests +system.physmem.pageHitRate 80.36 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 6758640 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3687750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 34296600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 15252731520 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 5982776145 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 134867232750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 156147584715 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.653337 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 224361889750 # Time in different power states -system.physmem_0.memoryStateTime::REF 7797920000 # Time in different power states +system.physmem_0.refreshEnergy 15253240080 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 6038642700 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 134822908500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 156159534270 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.682165 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 224288059000 # Time in different power states +system.physmem_0.memoryStateTime::REF 7798180000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1365674000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1447046250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 4845960 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2644125 # Energy for precharge commands per rank (pJ) +system.physmem_1.actEnergy 4914000 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2681250 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 27058200 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 15252731520 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 5743132470 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 135077446500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 156107858775 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.483223 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 224713608000 # Time in different power states -system.physmem_1.memoryStateTime::REF 7797920000 # Time in different power states +system.physmem_1.refreshEnergy 15253240080 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 5739994620 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 135084870750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 156112758900 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.481917 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 224725904750 # Time in different power states +system.physmem_1.memoryStateTime::REF 7798180000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1013955750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1009185250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 233525789500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 45912937 # Number of BP lookups -system.cpu.branchPred.condPredicted 26702744 # Number of conditional branches predicted +system.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 45912940 # Number of BP lookups +system.cpu.branchPred.condPredicted 26702743 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 565787 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 25186730 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 25186733 # Number of BTB lookups system.cpu.branchPred.BTBHits 18811780 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 74.689251 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 74.689242 # BTB Hit Percentage system.cpu.branchPred.usedRAS 8285572 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 323 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 2249877 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectLookups 2249880 # Number of indirect predictor lookups. system.cpu.branchPred.indirectHits 2235903 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 13974 # Number of indirect misses. +system.cpu.branchPred.indirectMisses 13977 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 111495 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 95338457 # DTB read hits +system.cpu.dtb.read_hits 95338456 # DTB read hits system.cpu.dtb.read_misses 116 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 95338573 # DTB read accesses +system.cpu.dtb.read_accesses 95338572 # DTB read accesses system.cpu.dtb.write_hits 73578378 # DTB write hits system.cpu.dtb.write_misses 849 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_accesses 73579227 # DTB write accesses -system.cpu.dtb.data_hits 168916835 # DTB hits +system.cpu.dtb.data_hits 168916834 # DTB hits system.cpu.dtb.data_misses 965 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 168917800 # DTB accesses -system.cpu.itb.fetch_hits 96959231 # ITB hits +system.cpu.dtb.data_accesses 168917799 # DTB accesses +system.cpu.itb.fetch_hits 96959232 # ITB hits system.cpu.itb.fetch_misses 1239 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 96960470 # ITB accesses +system.cpu.itb.fetch_accesses 96960471 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -299,16 +299,16 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 233525789500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 467051579 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 233533887500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 467067775 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 398664651 # Number of instructions committed system.cpu.committedOps 398664651 # Number of ops (including micro ops) committed system.cpu.discardedOps 2289293 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.171540 # CPI: cycles per instruction -system.cpu.ipc 0.853577 # IPC: instructions per cycle +system.cpu.cpi 1.171581 # CPI: cycles per instruction +system.cpu.ipc 0.853548 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 23123356 5.80% 5.80% # Class of committed instruction system.cpu.op_class_0::IntAlu 141652555 35.53% 41.33% # Class of committed instruction system.cpu.op_class_0::IntMult 2124322 0.53% 41.86% # Class of committed instruction @@ -344,18 +344,18 @@ system.cpu.op_class_0::MemWrite 73520764 18.44% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 398664651 # Class of committed instruction -system.cpu.tickCycles 455740556 # Number of cycles that the object actually ticked -system.cpu.idleCycles 11311023 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 233525789500 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 455740572 # Number of cycles that the object actually ticked +system.cpu.idleCycles 11327203 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 771 # number of replacements -system.cpu.dcache.tags.tagsinuse 3291.966637 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 167817023 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 3291.924590 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 167817024 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4165 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 40292.202401 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 40292.202641 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3291.966637 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.803703 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.803703 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 3291.924590 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.803693 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.803693 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3394 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id @@ -365,31 +365,31 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 3113 system.cpu.dcache.tags.occ_task_id_percent::1024 0.828613 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 335652191 # Number of tag accesses system.cpu.dcache.tags.data_accesses 335652191 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 233525789500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 94302223 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 94302223 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73514800 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73514800 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 167817023 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 167817023 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 167817023 # number of overall hits -system.cpu.dcache.overall_hits::total 167817023 # number of overall hits +system.cpu.dcache.WriteReq_hits::cpu.data 73514801 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73514801 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 167817024 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 167817024 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 167817024 # number of overall hits +system.cpu.dcache.overall_hits::total 167817024 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 1061 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 1061 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5929 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5929 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 6990 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 6990 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 6990 # number of overall misses -system.cpu.dcache.overall_misses::total 6990 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 77930500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 77930500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 429190000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 429190000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 507120500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 507120500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 507120500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 507120500 # number of overall miss cycles +system.cpu.dcache.WriteReq_misses::cpu.data 5928 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5928 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 6989 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 6989 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 6989 # number of overall misses +system.cpu.dcache.overall_misses::total 6989 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 80682500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 80682500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 434084500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 434084500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 514767000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 514767000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 514767000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 514767000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 94303284 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 94303284 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) @@ -406,14 +406,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000042 system.cpu.dcache.demand_miss_rate::total 0.000042 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000042 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000042 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73450.047125 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 73450.047125 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72388.261090 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 72388.261090 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 72549.427754 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 72549.427754 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 72549.427754 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 72549.427754 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 76043.826579 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 76043.826579 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73226.130229 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 73226.130229 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 73653.884676 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 73653.884676 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 73653.884676 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 73653.884676 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -424,12 +424,12 @@ system.cpu.dcache.writebacks::writebacks 654 # nu system.cpu.dcache.writebacks::total 654 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 92 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 92 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2733 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2733 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2825 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2825 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2825 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2825 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2732 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2732 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2824 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2824 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2824 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2824 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 969 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 969 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3196 # number of WriteReq MSHR misses @@ -438,14 +438,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4165 system.cpu.dcache.demand_mshr_misses::total 4165 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4165 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4165 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 70280500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 70280500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 239912500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 239912500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 310193000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 310193000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 310193000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 310193000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 72936500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 72936500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 242391000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 242391000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 315327500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 315327500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 315327500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 315327500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for WriteReq accesses @@ -454,69 +454,69 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72528.895769 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72528.895769 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75066.489362 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75066.489362 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74476.110444 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 74476.110444 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74476.110444 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 74476.110444 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 233525789500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75269.865841 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75269.865841 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75841.989987 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75841.989987 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75708.883553 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 75708.883553 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75708.883553 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 75708.883553 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 3193 # number of replacements -system.cpu.icache.tags.tagsinuse 1919.750364 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 96954060 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1919.733373 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 96954061 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 5171 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 18749.576484 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 18749.576678 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1919.750364 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.937378 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.937378 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1919.733373 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.937370 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.937370 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1978 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 208 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 396 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1287 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.965820 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 193923633 # Number of tag accesses -system.cpu.icache.tags.data_accesses 193923633 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 233525789500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 96954060 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 96954060 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 96954060 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 96954060 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 96954060 # number of overall hits -system.cpu.icache.overall_hits::total 96954060 # number of overall hits +system.cpu.icache.tags.tag_accesses 193923635 # Number of tag accesses +system.cpu.icache.tags.data_accesses 193923635 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 96954061 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 96954061 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 96954061 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 96954061 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 96954061 # number of overall hits +system.cpu.icache.overall_hits::total 96954061 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 5171 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 5171 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 5171 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 5171 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 5171 # number of overall misses system.cpu.icache.overall_misses::total 5171 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 318040500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 318040500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 318040500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 318040500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 318040500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 318040500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 96959231 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 96959231 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 96959231 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 96959231 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 96959231 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 96959231 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 321948500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 321948500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 321948500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 321948500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 321948500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 321948500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 96959232 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 96959232 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 96959232 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 96959232 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 96959232 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 96959232 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000053 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000053 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000053 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000053 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000053 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000053 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61504.641269 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 61504.641269 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 61504.641269 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 61504.641269 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 61504.641269 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 61504.641269 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62260.394508 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 62260.394508 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 62260.394508 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 62260.394508 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 62260.394508 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 62260.394508 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -531,47 +531,46 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 5171 system.cpu.icache.demand_mshr_misses::total 5171 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 5171 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 5171 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 312869500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 312869500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 312869500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 312869500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 312869500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 312869500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 316777500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 316777500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 316777500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 316777500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 316777500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 316777500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000053 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000053 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000053 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60504.641269 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60504.641269 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60504.641269 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 60504.641269 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60504.641269 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 60504.641269 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 233525789500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61260.394508 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61260.394508 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61260.394508 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 61260.394508 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61260.394508 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 61260.394508 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 4425.384656 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4801 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 5273 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.910487 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 7128.160045 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 5427 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 7873 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.689318 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 372.164909 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3411.179805 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 642.039942 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.011358 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.104101 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.019594 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.135052 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 5273 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 126 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 613 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4442 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.160919 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 114871 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 114871 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 233525789500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3411.137560 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 3717.022485 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.104100 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.113435 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.217534 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 7873 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 118 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 503 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 7185 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.240265 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 114273 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 114273 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 654 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 654 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 3193 # number of WritebackClean hits @@ -600,18 +599,18 @@ system.cpu.l2cache.demand_misses::total 7873 # nu system.cpu.l2cache.overall_misses::cpu.inst 3895 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 3978 # number of overall misses system.cpu.l2cache.overall_misses::total 7873 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 234589500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 234589500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 291713500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 291713500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 67354500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 67354500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 291713500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 301944000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 593657500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 291713500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 301944000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 593657500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 237071000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 237071000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 295621500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 295621500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 70008000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 70008000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 295621500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 307079000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 602700500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 295621500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 307079000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 602700500 # number of overall miss cycles system.cpu.l2cache.WritebackDirty_accesses::writebacks 654 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 654 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 3193 # number of WritebackClean accesses(hits+misses) @@ -640,18 +639,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.843295 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.753239 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.955102 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.843295 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74781.479120 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74781.479120 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74894.351733 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74894.351733 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80088.585018 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80088.585018 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74894.351733 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75903.469080 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 75404.229646 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74894.351733 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75903.469080 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 75404.229646 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75572.521517 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75572.521517 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75897.689345 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75897.689345 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83243.757432 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83243.757432 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75897.689345 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77194.318753 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 76552.838816 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75897.689345 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77194.318753 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 76552.838816 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -670,18 +669,18 @@ system.cpu.l2cache.demand_mshr_misses::total 7873 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3895 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 3978 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7873 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 203219500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 203219500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 252763500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 252763500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 58944500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 58944500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 252763500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 262164000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 514927500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 252763500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 262164000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 514927500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 205701000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 205701000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 256671500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 256671500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 61598000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 61598000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 256671500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 267299000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 523970500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 256671500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 267299000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 523970500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.980926 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.980926 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.753239 # mshr miss rate for ReadCleanReq accesses @@ -694,25 +693,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.843295 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.753239 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955102 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.843295 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64781.479120 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64781.479120 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64894.351733 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64894.351733 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70088.585018 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70088.585018 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64894.351733 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65903.469080 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65404.229646 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64894.351733 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65903.469080 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65404.229646 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65572.521517 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65572.521517 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65897.689345 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65897.689345 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73243.757432 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73243.757432 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65897.689345 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67194.318753 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66552.838816 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65897.689345 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67194.318753 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66552.838816 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 13300 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 3964 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 233525789500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 6138 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 654 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 3193 # Transaction distribution @@ -744,9 +743,15 @@ system.cpu.toL2Bus.reqLayer0.occupancy 10497000 # La system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 7756500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 6247999 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 6247500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 233525789500 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 7873 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 4736 # Transaction distribution system.membus.trans_dist::ReadExReq 3137 # Transaction distribution system.membus.trans_dist::ReadExResp 3137 # Transaction distribution @@ -767,9 +772,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 7873 # Request fanout histogram -system.membus.reqLayer0.occupancy 9219000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 9223000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 41801750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 41799750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |