diff options
Diffstat (limited to 'tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt')
| -rw-r--r-- | tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt | 1256 |
1 files changed, 707 insertions, 549 deletions
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt index f5e3faa91..bdc3bba7f 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -1,52 +1,210 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.080354 # Number of seconds simulated -sim_ticks 80354154000 # Number of ticks simulated -final_tick 80354154000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.080450 # Number of seconds simulated +sim_ticks 80450416000 # Number of ticks simulated +final_tick 80450416000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 221188 # Simulator instruction rate (inst/s) -host_op_rate 221188 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 47323038 # Simulator tick rate (ticks/s) -host_mem_usage 219864 # Number of bytes of host memory used -host_seconds 1697.99 # Real time elapsed on the host +host_inst_rate 142052 # Simulator instruction rate (inst/s) +host_op_rate 142052 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 30428395 # Simulator tick rate (ticks/s) +host_mem_usage 223780 # Number of bytes of host memory used +host_seconds 2643.93 # Real time elapsed on the host sim_insts 375574808 # Number of instructions simulated sim_ops 375574808 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 222976 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 255424 # Number of bytes read from this memory -system.physmem.bytes_read::total 478400 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 222976 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 222976 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3484 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3991 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7475 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2774916 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3178728 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 5953644 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2774916 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2774916 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2774916 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3178728 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 5953644 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 222592 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 255232 # Number of bytes read from this memory +system.physmem.bytes_read::total 477824 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 222592 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 222592 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3478 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3988 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7466 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2766822 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3172538 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 5939360 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2766822 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2766822 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2766822 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3172538 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 5939360 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7466 # Total number of read requests seen +system.physmem.writeReqs 0 # Total number of write requests seen +system.physmem.cpureqs 7466 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 477824 # Total number of bytes read from memory +system.physmem.bytesWritten 0 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 477824 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 484 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 483 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 533 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 529 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 384 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 401 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 463 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 447 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 405 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 456 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 591 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 408 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 548 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 429 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 401 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 504 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis +system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 80450362000 # Total gap between requests +system.physmem.readPktSize::0 0 # Categorize read packet sizes +system.physmem.readPktSize::1 0 # Categorize read packet sizes +system.physmem.readPktSize::2 0 # Categorize read packet sizes +system.physmem.readPktSize::3 0 # Categorize read packet sizes +system.physmem.readPktSize::4 0 # Categorize read packet sizes +system.physmem.readPktSize::5 0 # Categorize read packet sizes +system.physmem.readPktSize::6 7466 # Categorize read packet sizes +system.physmem.readPktSize::7 0 # Categorize read packet sizes +system.physmem.readPktSize::8 0 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # categorize write packet sizes +system.physmem.writePktSize::1 0 # categorize write packet sizes +system.physmem.writePktSize::2 0 # categorize write packet sizes +system.physmem.writePktSize::3 0 # categorize write packet sizes +system.physmem.writePktSize::4 0 # categorize write packet sizes +system.physmem.writePktSize::5 0 # categorize write packet sizes +system.physmem.writePktSize::6 0 # categorize write packet sizes +system.physmem.writePktSize::7 0 # categorize write packet sizes +system.physmem.writePktSize::8 0 # categorize write packet sizes +system.physmem.neitherpktsize::0 0 # categorize neither packet sizes +system.physmem.neitherpktsize::1 0 # categorize neither packet sizes +system.physmem.neitherpktsize::2 0 # categorize neither packet sizes +system.physmem.neitherpktsize::3 0 # categorize neither packet sizes +system.physmem.neitherpktsize::4 0 # categorize neither packet sizes +system.physmem.neitherpktsize::5 0 # categorize neither packet sizes +system.physmem.neitherpktsize::6 0 # categorize neither packet sizes +system.physmem.neitherpktsize::7 0 # categorize neither packet sizes +system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.rdQLenPdf::0 3927 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2012 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 826 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 326 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 202 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 113 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 42 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.totQLat 54925938 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 190713938 # Sum of mem lat for all requests +system.physmem.totBusLat 29864000 # Total cycles spent in databus access +system.physmem.totBankLat 105924000 # Total cycles spent in bank access +system.physmem.avgQLat 7356.81 # Average queueing delay per request +system.physmem.avgBankLat 14187.52 # Average bank access latency per request +system.physmem.avgBusLat 4000.00 # Average bus latency per request +system.physmem.avgMemAccLat 25544.33 # Average memory access latency +system.physmem.avgRdBW 5.94 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 5.94 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.04 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.00 # Average read queue length over time +system.physmem.avgWrQLen 0.00 # Average write queue length over time +system.physmem.readRowHits 6527 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate 87.42 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 10775564.16 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 103401614 # DTB read hits -system.cpu.dtb.read_misses 88552 # DTB read misses -system.cpu.dtb.read_acv 48603 # DTB read access violations -system.cpu.dtb.read_accesses 103490166 # DTB read accesses -system.cpu.dtb.write_hits 79056152 # DTB write hits -system.cpu.dtb.write_misses 1601 # DTB write misses +system.cpu.dtb.read_hits 103443494 # DTB read hits +system.cpu.dtb.read_misses 89204 # DTB read misses +system.cpu.dtb.read_acv 48604 # DTB read access violations +system.cpu.dtb.read_accesses 103532698 # DTB read accesses +system.cpu.dtb.write_hits 79020707 # DTB write hits +system.cpu.dtb.write_misses 1585 # DTB write misses system.cpu.dtb.write_acv 2 # DTB write access violations -system.cpu.dtb.write_accesses 79057753 # DTB write accesses -system.cpu.dtb.data_hits 182457766 # DTB hits -system.cpu.dtb.data_misses 90153 # DTB misses -system.cpu.dtb.data_acv 48605 # DTB access violations -system.cpu.dtb.data_accesses 182547919 # DTB accesses -system.cpu.itb.fetch_hits 52578444 # ITB hits +system.cpu.dtb.write_accesses 79022292 # DTB write accesses +system.cpu.dtb.data_hits 182464201 # DTB hits +system.cpu.dtb.data_misses 90789 # DTB misses +system.cpu.dtb.data_acv 48606 # DTB access violations +system.cpu.dtb.data_accesses 182554990 # DTB accesses +system.cpu.itb.fetch_hits 52635617 # ITB hits system.cpu.itb.fetch_misses 446 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 52578890 # ITB accesses +system.cpu.itb.fetch_accesses 52636063 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -60,245 +218,245 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 160708310 # number of cpu cycles simulated +system.cpu.numCycles 160900834 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 52055858 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 30270064 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1609565 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 28583053 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 24291253 # Number of BTB hits +system.cpu.BPredUnit.lookups 52082511 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 30304197 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1627462 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 28687866 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 24364965 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 9363483 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 1125 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 53630506 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 462761975 # Number of instructions fetch has processed -system.cpu.fetch.Branches 52055858 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 33654736 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 81569260 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 7805922 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 19227823 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 182 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 8640 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 52578444 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 632985 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 160593743 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.881569 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.314206 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 9358559 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 1149 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 53712913 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 462927523 # Number of instructions fetch has processed +system.cpu.fetch.Branches 52082511 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 33723524 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 81628321 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 7863564 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 19256748 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 186 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 8496 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 52635617 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 625198 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 160803654 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.878837 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.313069 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 79024483 49.21% 49.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4373999 2.72% 51.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 7277585 4.53% 56.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 5624285 3.50% 59.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 12451588 7.75% 67.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 8090347 5.04% 72.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5701462 3.55% 76.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1906860 1.19% 77.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 36143134 22.51% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 79175333 49.24% 49.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4378645 2.72% 51.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 7276914 4.53% 56.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 5654242 3.52% 60.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 12481747 7.76% 67.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 8090070 5.03% 72.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5699527 3.54% 76.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1919584 1.19% 77.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 36127592 22.47% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 160593743 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.323915 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.879515 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 59159628 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 14701180 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 76777373 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3802489 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 6153073 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 9767212 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 4329 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 457201252 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 12277 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 6153073 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 62463630 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4784250 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 400809 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 77384574 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 9407407 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 451419869 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 14 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 20713 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 7782416 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 295098377 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 593658097 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 314398187 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 279259910 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 160803654 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.323693 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.877098 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 59260573 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 14714376 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 76844391 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3791608 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 6192706 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 9758398 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 4357 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 457340975 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 12460 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 6192706 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 62581380 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4767420 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 396481 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 77424943 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 9440724 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 451604153 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 25 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 23405 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 7795110 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 295281147 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 593898440 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 314599798 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 279298642 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259532329 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 35566048 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 38393 # count of serializing insts renamed +system.cpu.rename.UndoneMaps 35748818 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 38358 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 348 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 27305396 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 107006158 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 81864884 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 8914753 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 6402170 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 416586090 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 336 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 407940469 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1092011 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 40751586 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 19838559 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 121 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 160593743 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.540202 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.007855 # Number of insts issued each cycle +system.cpu.rename.skidInsts 27322373 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 107078098 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 81809760 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 8914792 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 6385731 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 416755970 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 334 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 407971342 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1213804 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 40920126 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 20099668 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 119 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 160803654 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.537078 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.007577 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 32107491 19.99% 19.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 26532573 16.52% 36.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 26024058 16.20% 52.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 24782303 15.43% 68.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 21577160 13.44% 81.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15465247 9.63% 91.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8675795 5.40% 96.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 4109702 2.56% 99.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1319414 0.82% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 32260500 20.06% 20.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 26539337 16.50% 36.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 26078054 16.22% 52.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 24787830 15.41% 68.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 21571430 13.41% 81.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15523746 9.65% 91.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8624317 5.36% 96.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 4085465 2.54% 99.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1332975 0.83% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 160593743 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 160803654 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 35836 0.30% 0.30% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 36186 0.30% 0.30% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 0.30% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.30% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 73145 0.62% 0.92% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 5467 0.05% 0.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 3221 0.03% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 1851348 15.57% 16.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 1774625 14.92% 31.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 31.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 31.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 31.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 31.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 31.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 31.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 31.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 31.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 31.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 31.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 31.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 31.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 31.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 31.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 31.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 31.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 31.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 31.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 31.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 31.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 31.48% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 5106562 42.94% 74.43% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3040891 25.57% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 74788 0.63% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 4408 0.04% 0.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 3062 0.03% 1.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 1840642 15.50% 16.50% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 1784659 15.03% 31.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 31.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 31.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 31.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 31.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 31.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 31.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 31.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 31.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 31.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 31.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 31.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 31.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 31.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 31.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 31.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 31.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 31.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 31.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 31.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 31.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 31.53% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 5098486 42.94% 74.47% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3030945 25.53% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 158120657 38.76% 38.77% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2126534 0.52% 39.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 39.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 33463281 8.20% 47.49% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 7848056 1.92% 49.42% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2840409 0.70% 50.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 16567576 4.06% 54.17% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 1592675 0.39% 54.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.57% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 105294166 25.81% 80.38% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 80053534 19.62% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 158101841 38.75% 38.76% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2126541 0.52% 39.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 39.28% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 33488456 8.21% 47.49% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 7847707 1.92% 49.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2841085 0.70% 50.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 16565313 4.06% 54.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 1591977 0.39% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 105357579 25.82% 80.39% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 80017262 19.61% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 407940469 # Type of FU issued -system.cpu.iq.rate 2.538391 # Inst issue rate -system.cpu.iq.fu_busy_cnt 11891095 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.029149 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 648130283 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 270005016 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 237809508 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 341327504 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 187383841 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 162964934 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 245490516 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 174307467 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 14797790 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 407971342 # Type of FU issued +system.cpu.iq.rate 2.535545 # Inst issue rate +system.cpu.iq.fu_busy_cnt 11873176 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.029103 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 648496700 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 270371889 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 237775030 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 341336618 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 187355366 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 162947679 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 245502336 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 174308601 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 14799025 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 12251671 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 123751 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 50882 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 8344155 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 12323611 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 124858 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 50857 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 8289031 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 260839 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 3 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 260769 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 122 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 6153073 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2493888 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 367103 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 441513906 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 235069 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 107006158 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 81864884 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 336 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 120 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 76 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 50882 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1249323 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 568752 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1818075 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 403380721 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 103538845 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 4559748 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 6192706 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2493954 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 366810 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 441694516 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 229015 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 107078098 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 81809760 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 334 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 117 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 78 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 50857 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1275804 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 567133 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1842937 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 403387908 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 103581364 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 4583434 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 24927480 # number of nop insts executed -system.cpu.iew.exec_refs 182596628 # number of memory reference insts executed -system.cpu.iew.exec_branches 47226669 # Number of branches executed -system.cpu.iew.exec_stores 79057783 # Number of stores executed -system.cpu.iew.exec_rate 2.510018 # Inst execution rate -system.cpu.iew.wb_sent 401610425 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 400774442 # cumulative count of insts written-back -system.cpu.iew.wb_producers 195308199 # num instructions producing a value -system.cpu.iew.wb_consumers 273451305 # num instructions consuming a value +system.cpu.iew.exec_nop 24938212 # number of nop insts executed +system.cpu.iew.exec_refs 182603691 # number of memory reference insts executed +system.cpu.iew.exec_branches 47210628 # Number of branches executed +system.cpu.iew.exec_stores 79022327 # Number of stores executed +system.cpu.iew.exec_rate 2.507059 # Inst execution rate +system.cpu.iew.wb_sent 401574040 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 400722709 # cumulative count of insts written-back +system.cpu.iew.wb_producers 195201608 # num instructions producing a value +system.cpu.iew.wb_consumers 273256469 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.493800 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.714234 # average fanout of values written-back +system.cpu.iew.wb_rate 2.490495 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.714353 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 42890401 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 43076400 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1605306 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 154440670 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.581345 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.965853 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1623178 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 154610948 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.578502 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.964409 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 58870445 38.12% 38.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 23396206 15.15% 53.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13280012 8.60% 61.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11680215 7.56% 69.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 8466998 5.48% 74.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 5501467 3.56% 78.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 5150112 3.33% 81.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3370011 2.18% 83.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 24725204 16.01% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 58949463 38.13% 38.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 23452675 15.17% 53.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13321237 8.62% 61.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11705960 7.57% 69.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 8475693 5.48% 74.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 5493357 3.55% 78.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 5136307 3.32% 81.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3345893 2.16% 84.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 24730363 16.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 154440670 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 154610948 # Number of insts commited each cycle system.cpu.commit.committedInsts 398664583 # Number of instructions committed system.cpu.commit.committedOps 398664583 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -309,70 +467,70 @@ system.cpu.commit.branches 44587533 # Nu system.cpu.commit.fp_insts 155295106 # Number of committed floating point instructions. system.cpu.commit.int_insts 316365839 # Number of committed integer instructions. system.cpu.commit.function_calls 8007752 # Number of function calls committed. -system.cpu.commit.bw_lim_events 24725204 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 24730363 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 571267473 # The number of ROB reads -system.cpu.rob.rob_writes 889277309 # The number of ROB writes -system.cpu.timesIdled 3039 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 114567 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 571618591 # The number of ROB reads +system.cpu.rob.rob_writes 889688372 # The number of ROB writes +system.cpu.timesIdled 2869 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 97180 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 375574808 # Number of Instructions Simulated system.cpu.committedOps 375574808 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 375574808 # Number of Instructions Simulated -system.cpu.cpi 0.427900 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.427900 # CPI: Total CPI of All Threads -system.cpu.ipc 2.336997 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.336997 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 402957504 # number of integer regfile reads -system.cpu.int_regfile_writes 172619998 # number of integer regfile writes -system.cpu.fp_regfile_reads 158343155 # number of floating regfile reads -system.cpu.fp_regfile_writes 105226626 # number of floating regfile writes +system.cpu.cpi 0.428412 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.428412 # CPI: Total CPI of All Threads +system.cpu.ipc 2.334201 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.334201 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 402943078 # number of integer regfile reads +system.cpu.int_regfile_writes 172629700 # number of integer regfile writes +system.cpu.fp_regfile_reads 158343488 # number of floating regfile reads +system.cpu.fp_regfile_writes 105222580 # number of floating regfile writes system.cpu.misc_regfile_reads 350572 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 2218 # number of replacements -system.cpu.icache.tagsinuse 1836.523631 # Cycle average of tags in use -system.cpu.icache.total_refs 52573018 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 4149 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 12671.250422 # Average number of references to valid blocks. +system.cpu.icache.replacements 2200 # number of replacements +system.cpu.icache.tagsinuse 1838.464064 # Cycle average of tags in use +system.cpu.icache.total_refs 52630329 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 4132 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 12737.252904 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1836.523631 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.896740 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.896740 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 52573018 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 52573018 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 52573018 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 52573018 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 52573018 # number of overall hits -system.cpu.icache.overall_hits::total 52573018 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5426 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5426 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5426 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5426 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5426 # number of overall misses -system.cpu.icache.overall_misses::total 5426 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 168571000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 168571000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 168571000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 168571000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 168571000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 168571000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 52578444 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 52578444 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 52578444 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 52578444 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 52578444 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 52578444 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000103 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000103 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000103 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000103 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000103 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000103 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 31067.268706 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 31067.268706 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 31067.268706 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 31067.268706 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 31067.268706 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 31067.268706 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1838.464064 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.897688 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.897688 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 52630329 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 52630329 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 52630329 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 52630329 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 52630329 # number of overall hits +system.cpu.icache.overall_hits::total 52630329 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5288 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5288 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5288 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5288 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5288 # number of overall misses +system.cpu.icache.overall_misses::total 5288 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 146095500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 146095500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 146095500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 146095500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 146095500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 146095500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 52635617 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 52635617 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 52635617 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 52635617 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 52635617 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 52635617 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000100 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000100 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000100 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000100 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000100 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000100 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27627.742057 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 27627.742057 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 27627.742057 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 27627.742057 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 27627.742057 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 27627.742057 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -381,284 +539,284 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1277 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1277 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1277 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1277 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1277 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1277 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4149 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 4149 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 4149 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 4149 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 4149 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 4149 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 129086500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 129086500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 129086500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 129086500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 129086500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 129086500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1156 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1156 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1156 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1156 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1156 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1156 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4132 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 4132 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 4132 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 4132 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 4132 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 4132 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 115307000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 115307000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 115307000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 115307000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 115307000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 115307000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000079 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000079 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000079 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 31112.677754 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 31112.677754 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 31112.677754 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 31112.677754 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 31112.677754 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 31112.677754 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27905.856728 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27905.856728 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27905.856728 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 27905.856728 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27905.856728 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 27905.856728 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 788 # number of replacements -system.cpu.dcache.tagsinuse 3297.853996 # Cycle average of tags in use -system.cpu.dcache.total_refs 161841661 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 4190 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 38625.694749 # Average number of references to valid blocks. +system.cpu.dcache.replacements 781 # number of replacements +system.cpu.dcache.tagsinuse 3295.904807 # Cycle average of tags in use +system.cpu.dcache.total_refs 161883653 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 4181 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 38718.883760 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3297.853996 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.805140 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.805140 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 88341162 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 88341162 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73500481 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73500481 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 18 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 18 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 161841643 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 161841643 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 161841643 # number of overall hits -system.cpu.dcache.overall_hits::total 161841643 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1802 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1802 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 20248 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 20248 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 22050 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 22050 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 22050 # number of overall misses -system.cpu.dcache.overall_misses::total 22050 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 62316500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 62316500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 625415500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 625415500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 687732000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 687732000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 687732000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 687732000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 88342964 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 88342964 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::cpu.data 3295.904807 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.804664 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.804664 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 88381720 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 88381720 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 73501913 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73501913 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 20 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 20 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 161883633 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 161883633 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 161883633 # number of overall hits +system.cpu.dcache.overall_hits::total 161883633 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1838 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1838 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 18816 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 18816 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 20654 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 20654 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 20654 # number of overall misses +system.cpu.dcache.overall_misses::total 20654 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 63964000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 63964000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 503501000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 503501000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 567465000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 567465000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 567465000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 567465000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 88383558 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 88383558 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 73520729 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 18 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 18 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 161863693 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 161863693 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 161863693 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 161863693 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000020 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000020 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000275 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000275 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000136 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000136 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000136 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000136 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34581.853496 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 34581.853496 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30887.766693 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 30887.766693 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31189.659864 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31189.659864 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31189.659864 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31189.659864 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 15 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 20 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 20 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 161904287 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 161904287 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 161904287 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 161904287 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000021 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000021 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000256 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000256 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000128 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000128 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000128 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000128 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34800.870511 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 34800.870511 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26759.194303 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 26759.194303 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 27474.823279 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 27474.823279 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 27474.823279 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 27474.823279 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 613 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 15 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 153.250000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 667 # number of writebacks -system.cpu.dcache.writebacks::total 667 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 813 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 813 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 17047 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 17047 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 17860 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 17860 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 17860 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 17860 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 989 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 989 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3201 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 3201 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4190 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4190 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4190 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4190 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 35672500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 35672500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 129053000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 129053000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 164725500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 164725500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 164725500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 164725500 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 659 # number of writebacks +system.cpu.dcache.writebacks::total 659 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 852 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 852 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 15621 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 15621 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 16473 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 16473 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 16473 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 16473 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 986 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 986 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3195 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 3195 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4181 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4181 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4181 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4181 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 35567000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 35567000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 111777000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 111777000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 147344000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 147344000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 147344000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 147344000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000011 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000044 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000043 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000026 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000026 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000026 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000026 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 36069.261881 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 36069.261881 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40316.463605 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40316.463605 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 39313.961814 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 39313.961814 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 39313.961814 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 39313.961814 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 36072.008114 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 36072.008114 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34984.976526 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34984.976526 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35241.329825 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 35241.329825 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35241.329825 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 35241.329825 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 4035.335685 # Cycle average of tags in use -system.cpu.l2cache.total_refs 887 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 4877 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.181874 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 4031.024226 # Cycle average of tags in use +system.cpu.l2cache.total_refs 872 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 4868 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.179129 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 371.767101 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 3005.985586 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 657.582998 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.011345 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.091735 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.020068 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.123149 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 665 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 130 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 795 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 667 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 667 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 69 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 69 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 665 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 199 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 864 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 665 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 199 # number of overall hits -system.cpu.l2cache.overall_hits::total 864 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3484 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 859 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 4343 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 3132 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 3132 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3484 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 3991 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 7475 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3484 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 3991 # number of overall misses -system.cpu.l2cache.overall_misses::total 7475 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 124255000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 34500500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 158755500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 125685500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 125685500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 124255000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 160186000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 284441000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 124255000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 160186000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 284441000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 4149 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 989 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 5138 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 667 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 667 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 3201 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 3201 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 4149 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 4190 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 8339 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 4149 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 4190 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 8339 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.839720 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.868554 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.845271 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.978444 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.978444 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.839720 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.952506 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.896390 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.839720 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.952506 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.896390 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35664.466131 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 40163.562282 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 36554.340318 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 40129.469987 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 40129.469987 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35664.466131 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 40136.807818 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 38052.307692 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35664.466131 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 40136.807818 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 38052.307692 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 7 # number of cycles access was blocked +system.cpu.l2cache.occ_blocks::writebacks 371.780085 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 3001.770453 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 657.473688 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.011346 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.091607 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.020065 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.123017 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 654 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 129 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 783 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 659 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 659 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 64 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 64 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 654 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 193 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 847 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 654 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 193 # number of overall hits +system.cpu.l2cache.overall_hits::total 847 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3478 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 857 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 4335 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 3131 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 3131 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3478 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 3988 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 7466 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3478 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 3988 # number of overall misses +system.cpu.l2cache.overall_misses::total 7466 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 110498000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 34399000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 144897000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 108412500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 108412500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 110498000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 142811500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 253309500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 110498000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 142811500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 253309500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 4132 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 986 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 5118 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 659 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 659 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 3195 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 3195 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 4132 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 4181 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 8313 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 4132 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 4181 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 8313 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.841723 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.869168 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.847011 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.979969 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.979969 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.841723 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.953839 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.898111 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.841723 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.953839 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.898111 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 31770.557792 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 40138.856476 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 33424.913495 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34625.519004 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34625.519004 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 31770.557792 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 35810.305918 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 33928.408786 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 31770.557792 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 35810.305918 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 33928.408786 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 578 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 7 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 144.500000 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3484 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 859 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 4343 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3132 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 3132 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3484 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 3991 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 7475 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3484 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 3991 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 7475 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 112975000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 31822500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 144797500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 115935000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 115935000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 112975000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 147757500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 260732500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 112975000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 147757500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 260732500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.839720 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.868554 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.845271 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.978444 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.978444 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.839720 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.952506 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.896390 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.839720 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.952506 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.896390 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32426.808266 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37045.983702 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33340.432880 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37016.283525 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37016.283525 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32426.808266 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37022.676021 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34880.602007 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32426.808266 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37022.676021 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34880.602007 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3478 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 857 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 4335 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3131 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 3131 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3478 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 3988 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 7466 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3478 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 3988 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 7466 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 98162814 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 31479970 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 129642784 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 98128686 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 98128686 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 98162814 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 129608656 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 227771470 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 98162814 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 129608656 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 227771470 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.841723 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.869168 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.847011 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.979969 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.979969 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.841723 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.953839 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.898111 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.841723 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.953839 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.898111 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 28223.925819 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 36732.753792 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 29906.063206 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31341.004791 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31341.004791 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 28223.925819 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 32499.662989 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 30507.831503 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 28223.925819 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 32499.662989 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 30507.831503 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |