diff options
Diffstat (limited to 'tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt')
| -rw-r--r-- | tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt | 21 |
1 files changed, 16 insertions, 5 deletions
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt index d9eeb4f16..68a991d52 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.064189 # Nu sim_ticks 64188759000 # Number of ticks simulated final_tick 64188759000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 189145 # Simulator instruction rate (inst/s) -host_op_rate 189145 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 32326376 # Simulator tick rate (ticks/s) -host_mem_usage 256256 # Number of bytes of host memory used -host_seconds 1985.65 # Real time elapsed on the host +host_inst_rate 392159 # Simulator instruction rate (inst/s) +host_op_rate 392159 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 67023124 # Simulator tick rate (ticks/s) +host_mem_usage 303292 # Number of bytes of host memory used +host_seconds 957.71 # Real time elapsed on the host sim_insts 375574794 # Number of instructions simulated sim_ops 375574794 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 64188759000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 220800 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 255360 # Number of bytes read from this memory system.physmem.bytes_read::total 476160 # Number of bytes read from this memory @@ -250,6 +251,7 @@ system.physmem_1.memoryStateTime::REF 2143180000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 684265000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 64188759000 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 47858697 # Number of BP lookups system.cpu.branchPred.condPredicted 27887013 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 573168 # Number of conditional branches incorrect @@ -297,6 +299,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 64188759000 # Cumulative time (in ticks) in various power states system.cpu.numCycles 128377521 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -590,6 +593,7 @@ system.cpu.fp_regfile_reads 154536644 # nu system.cpu.fp_regfile_writes 102074619 # number of floating regfile writes system.cpu.misc_regfile_reads 350572 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 64188759000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 776 # number of replacements system.cpu.dcache.tags.tagsinuse 3292.009184 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 152572889 # Total number of references to valid blocks. @@ -608,6 +612,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 3116 system.cpu.dcache.tags.occ_task_id_percent::1024 0.830078 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 305192990 # Number of tag accesses system.cpu.dcache.tags.data_accesses 305192990 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 64188759000 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 79071847 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 79071847 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 73501036 # number of WriteReq hits @@ -708,6 +713,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77606.321839 system.cpu.dcache.demand_avg_mshr_miss_latency::total 77606.321839 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77606.321839 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 77606.321839 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 64188759000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 2132 # number of replacements system.cpu.icache.tags.tagsinuse 1831.246133 # Cycle average of tags in use system.cpu.icache.tags.total_refs 46954666 # Total number of references to valid blocks. @@ -725,6 +731,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 1346 system.cpu.icache.tags.occ_task_id_percent::1024 0.941406 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 93924682 # Number of tag accesses system.cpu.icache.tags.data_accesses 93924682 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 64188759000 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 46954666 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 46954666 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 46954666 # number of demand (read+write) hits @@ -799,6 +806,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67833.374384 system.cpu.icache.demand_avg_mshr_miss_latency::total 67833.374384 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67833.374384 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 67833.374384 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 64188759000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 4001.708243 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3078 # Total number of references to valid blocks. @@ -820,6 +828,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4032 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.147919 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 97187 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 97187 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 64188759000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 655 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 655 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 2132 # number of WritebackClean hits @@ -960,6 +969,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 64188759000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 5048 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 655 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 2132 # Transaction distribution @@ -992,6 +1002,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 6090499 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 6264000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 64188759000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 4312 # Transaction distribution system.membus.trans_dist::ReadExReq 3128 # Transaction distribution system.membus.trans_dist::ReadExResp 3128 # Transaction distribution |