diff options
Diffstat (limited to 'tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt')
| -rw-r--r-- | tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt | 407 |
1 files changed, 253 insertions, 154 deletions
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt index 28785f469..e5ff3033e 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.089480 # Nu sim_ticks 89480174500 # Number of ticks simulated final_tick 89480174500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 190161 # Simulator instruction rate (inst/s) -host_tick_rate 45305657 # Simulator tick rate (ticks/s) -host_mem_usage 214676 # Number of bytes of host memory used -host_seconds 1975.03 # Real time elapsed on the host +host_inst_rate 246728 # Simulator instruction rate (inst/s) +host_op_rate 246728 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 58782597 # Simulator tick rate (ticks/s) +host_mem_usage 216860 # Number of bytes of host memory used +host_seconds 1522.22 # Real time elapsed on the host sim_insts 375574794 # Number of instructions simulated +sim_ops 375574794 # Number of ops (including micro ops) simulated system.physmem.bytes_read 475840 # Number of bytes read from this memory system.physmem.bytes_inst_read 219968 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory @@ -271,6 +273,7 @@ system.cpu.iew.wb_rate 2.269707 # in system.cpu.iew.wb_fanout 0.713332 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 398664569 # The number of committed instructions +system.cpu.commit.commitCommittedOps 398664569 # The number of committed instructions system.cpu.commit.commitSquashedInsts 60016815 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 3547729 # The number of times a branch was mispredicted @@ -291,7 +294,8 @@ system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100. system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::total 169731918 # Number of insts commited each cycle -system.cpu.commit.count 398664569 # Number of instructions committed +system.cpu.commit.committedInsts 398664569 # Number of instructions committed +system.cpu.commit.committedOps 398664569 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 168275214 # Number of memory references committed system.cpu.commit.loads 94754486 # Number of loads committed @@ -307,6 +311,7 @@ system.cpu.rob.rob_writes 926487800 # Th system.cpu.timesIdled 2712 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 121803 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 375574794 # Number of Instructions Simulated +system.cpu.committedOps 375574794 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 375574794 # Number of Instructions Simulated system.cpu.cpi 0.476497 # CPI: Cycles Per Instruction system.cpu.cpi_total 0.476497 # CPI: Total CPI of All Threads @@ -324,26 +329,39 @@ system.cpu.icache.total_refs 57898804 # To system.cpu.icache.sampled_refs 4037 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 14342.037156 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1834.326922 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.895667 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 57898804 # number of ReadReq hits -system.cpu.icache.demand_hits 57898804 # number of demand (read+write) hits -system.cpu.icache.overall_hits 57898804 # number of overall hits -system.cpu.icache.ReadReq_misses 5282 # number of ReadReq misses -system.cpu.icache.demand_misses 5282 # number of demand (read+write) misses -system.cpu.icache.overall_misses 5282 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 167914000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 167914000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 167914000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 57904086 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 57904086 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 57904086 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000091 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000091 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000091 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 31789.852329 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 31789.852329 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 31789.852329 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1834.326922 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.895667 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.895667 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 57898804 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 57898804 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 57898804 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 57898804 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 57898804 # number of overall hits +system.cpu.icache.overall_hits::total 57898804 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5282 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5282 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5282 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5282 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5282 # number of overall misses +system.cpu.icache.overall_misses::total 5282 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 167914000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 167914000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 167914000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 167914000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 167914000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 167914000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 57904086 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 57904086 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 57904086 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 57904086 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 57904086 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 57904086 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000091 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000091 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000091 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 31789.852329 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 31789.852329 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 31789.852329 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -352,27 +370,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 1245 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 1245 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 1245 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 4037 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 4037 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 4037 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 123459000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 123459000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 123459000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000070 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000070 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000070 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 30581.867724 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 30581.867724 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 30581.867724 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1245 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1245 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1245 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1245 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1245 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1245 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4037 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 4037 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 4037 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 4037 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 4037 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 4037 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 123459000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 123459000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 123459000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 123459000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 123459000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 123459000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000070 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000070 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000070 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 30581.867724 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 30581.867724 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 30581.867724 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 793 # number of replacements system.cpu.dcache.tagsinuse 3296.196945 # Cycle average of tags in use @@ -380,34 +401,53 @@ system.cpu.dcache.total_refs 164730953 # To system.cpu.dcache.sampled_refs 4193 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 39287.134033 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 3296.196945 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.804736 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 91229707 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 73501239 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 7 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits 164730946 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 164730946 # number of overall hits -system.cpu.dcache.ReadReq_misses 1678 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 19489 # number of WriteReq misses -system.cpu.dcache.demand_misses 21167 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 21167 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 55919500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 568883000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 624802500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 624802500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 91231385 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 73520728 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 7 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 164752113 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 164752113 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.000265 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.000128 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.000128 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 33325.089392 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 29189.953307 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 29517.763500 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 29517.763500 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 3296.196945 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.804736 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.804736 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 91229707 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 91229707 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 73501239 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73501239 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 7 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 7 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 164730946 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 164730946 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 164730946 # number of overall hits +system.cpu.dcache.overall_hits::total 164730946 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1678 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1678 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 19489 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 19489 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 21167 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 21167 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 21167 # number of overall misses +system.cpu.dcache.overall_misses::total 21167 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 55919500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 55919500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 568883000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 568883000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 624802500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 624802500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 624802500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 624802500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 91231385 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 91231385 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 73520728 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 73520728 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 7 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 7 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 164752113 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 164752113 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 164752113 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 164752113 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000018 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000265 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000128 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000128 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33325.089392 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29189.953307 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 29517.763500 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 29517.763500 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 13000 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked @@ -416,32 +456,40 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs 2600 system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 671 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 680 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 16294 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 16974 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 16974 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 998 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 3195 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 4193 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 4193 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 31703500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 113133500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 144837000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 144837000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000011 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000043 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 31767.034068 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35409.546166 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 34542.570952 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 34542.570952 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 671 # number of writebacks +system.cpu.dcache.writebacks::total 671 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 680 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 680 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16294 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16294 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 16974 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 16974 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 16974 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 16974 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 998 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 998 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3195 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 3195 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4193 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4193 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4193 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4193 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 31703500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 31703500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 113133500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 113133500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 144837000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 144837000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 144837000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 144837000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31767.034068 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35409.546166 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34542.570952 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34542.570952 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 10 # number of replacements system.cpu.l2cache.tagsinuse 4007.455925 # Cycle average of tags in use @@ -449,36 +497,75 @@ system.cpu.l2cache.total_refs 810 # To system.cpu.l2cache.sampled_refs 4847 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.167114 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 3629.785283 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 377.670641 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.110772 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.011526 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 730 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 671 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 65 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 795 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 795 # number of overall hits -system.cpu.l2cache.ReadReq_misses 4305 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 3130 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 7435 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 7435 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 148163500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 108392000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 256555500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 256555500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 5035 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 671 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 3195 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 8230 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 8230 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.855015 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.979656 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.903402 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.903402 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34416.608595 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34630.031949 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34506.455952 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34506.455952 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 377.670641 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2971.084033 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 658.701251 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.011526 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.090670 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.020102 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.122298 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 600 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 130 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 730 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 671 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 671 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 65 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 65 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 600 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 195 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 795 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 600 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 195 # number of overall hits +system.cpu.l2cache.overall_hits::total 795 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3437 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 868 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 4305 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 3130 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 3130 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3437 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 3998 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 7435 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3437 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 3998 # number of overall misses +system.cpu.l2cache.overall_misses::total 7435 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 118151500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 30012000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 148163500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 108392000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 108392000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 118151500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 138404000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 256555500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 118151500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 138404000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 256555500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 4037 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 998 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 5035 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 671 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 671 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 3195 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 3195 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 4037 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 4193 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 8230 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 4037 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 4193 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 8230 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.851375 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.869739 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.979656 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.851375 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.953494 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.851375 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.953494 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34376.345650 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34576.036866 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34630.031949 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34376.345650 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34618.309155 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34376.345650 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34618.309155 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -487,30 +574,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 4305 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 3130 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 7435 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 7435 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 134314000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 98534000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 232848000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 232848000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.855015 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.979656 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.903402 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.903402 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31199.535424 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31480.511182 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31317.821116 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31317.821116 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3437 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 868 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 4305 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3130 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 3130 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3437 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 3998 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 7435 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3437 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 3998 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 7435 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 107040000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 27274000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 134314000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 98534000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 98534000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 107040000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 125808000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 232848000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 107040000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 125808000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 232848000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.851375 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.869739 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.979656 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.851375 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.953494 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.851375 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.953494 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31143.439046 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31421.658986 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31480.511182 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31143.439046 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31467.733867 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31143.439046 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31467.733867 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |