diff options
Diffstat (limited to 'tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt')
| -rw-r--r-- | tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt | 79 |
1 files changed, 65 insertions, 14 deletions
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt index 852f5134d..f16fecb77 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt @@ -4,22 +4,29 @@ sim_seconds 0.567343 # Nu sim_ticks 567343170000 # Number of ticks simulated final_tick 567343170000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 766770 # Simulator instruction rate (inst/s) -host_op_rate 766770 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1091197730 # Simulator tick rate (ticks/s) -host_mem_usage 220456 # Number of bytes of host memory used -host_seconds 519.93 # Real time elapsed on the host +host_inst_rate 1377504 # Simulator instruction rate (inst/s) +host_op_rate 1377504 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1960338494 # Simulator tick rate (ticks/s) +host_mem_usage 220796 # Number of bytes of host memory used +host_seconds 289.41 # Real time elapsed on the host sim_insts 398664609 # Number of instructions simulated sim_ops 398664609 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 459520 # Number of bytes read from this memory -system.physmem.bytes_inst_read 205120 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 7180 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 809951 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 361545 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 809951 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 205120 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 254400 # Number of bytes read from this memory +system.physmem.bytes_read::total 459520 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 205120 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 205120 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3205 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3975 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7180 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 361545 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 448406 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 809951 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 361545 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 361545 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 361545 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 448406 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 809951 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -109,11 +116,17 @@ system.cpu.icache.demand_accesses::total 398664666 # nu system.cpu.icache.overall_accesses::cpu.inst 398664666 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 398664666 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000009 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000009 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000009 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000009 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000009 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000009 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 50648.516199 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 50648.516199 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 50648.516199 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 50648.516199 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 50648.516199 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 50648.516199 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -135,11 +148,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 175013000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 175013000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 175013000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000009 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000009 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 47648.516199 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 47648.516199 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 47648.516199 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 47648.516199 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47648.516199 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 47648.516199 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 764 # number of replacements system.cpu.dcache.tagsinuse 3288.912598 # Cycle average of tags in use @@ -183,13 +202,21 @@ system.cpu.dcache.demand_accesses::total 168275220 # nu system.cpu.dcache.overall_accesses::cpu.data 168275220 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 168275220 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000010 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000010 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000044 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000044 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50827.368421 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 50827.368421 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55212.991880 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55212.991880 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 54209.537572 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 54209.537572 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 54209.537572 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 54209.537572 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -217,13 +244,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 212622000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 212622000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 212622000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000044 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47827.368421 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47827.368421 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52212.991880 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52212.991880 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51209.537572 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 51209.537572 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51209.537572 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 51209.537572 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 13 # number of replacements system.cpu.l2cache.tagsinuse 3768.712262 # Cycle average of tags in use @@ -288,18 +323,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 4152 system.cpu.l2cache.overall_accesses::total 7825 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.872584 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.876842 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.873459 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.981262 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.981262 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.872584 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.957370 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.917572 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.872584 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.957370 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.917572 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -332,18 +375,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 159000000 system.cpu.l2cache.overall_mshr_miss_latency::total 287200000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.876842 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.873459 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.981262 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.981262 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.957370 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.917572 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.957370 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.917572 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |