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Diffstat (limited to 'tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt')
-rw-r--r--tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt210
1 files changed, 105 insertions, 105 deletions
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt
index 26c4b55f8..39d4d27ed 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.567335 # Nu
sim_ticks 567335093000 # Number of ticks simulated
final_tick 567335093000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1803555 # Simulator instruction rate (inst/s)
-host_op_rate 1803555 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2566617886 # Simulator tick rate (ticks/s)
-host_mem_usage 223016 # Number of bytes of host memory used
-host_seconds 221.04 # Real time elapsed on the host
+host_inst_rate 853902 # Simulator instruction rate (inst/s)
+host_op_rate 853902 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1215178011 # Simulator tick rate (ticks/s)
+host_mem_usage 278532 # Number of bytes of host memory used
+host_seconds 466.87 # Real time elapsed on the host
sim_insts 398664609 # Number of instructions simulated
sim_ops 398664609 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 205120 # Number of bytes read from this memory
@@ -160,106 +160,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 47648.516199
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47648.516199 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 47648.516199 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 764 # number of replacements
-system.cpu.dcache.tagsinuse 3288.930576 # Cycle average of tags in use
-system.cpu.dcache.total_refs 168271068 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 40527.713873 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 3288.930576 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.802962 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.802962 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 94753540 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 94753540 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 73517528 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 73517528 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 168271068 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 168271068 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 168271068 # number of overall hits
-system.cpu.dcache.overall_hits::total 168271068 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 950 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 950 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 3202 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 3202 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 4152 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 4152 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 4152 # number of overall misses
-system.cpu.dcache.overall_misses::total 4152 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 47084000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 47084000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 173590000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 173590000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 220674000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 220674000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 220674000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 220674000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 94754490 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 94754490 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 73520730 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 73520730 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 168275220 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 168275220 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 168275220 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 168275220 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000010 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.000010 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000044 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.000044 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49562.105263 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 49562.105263 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54212.991880 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 54212.991880 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 53148.843931 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 53148.843931 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 53148.843931 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 53148.843931 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 649 # number of writebacks
-system.cpu.dcache.writebacks::total 649 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 950 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 950 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3202 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 3202 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 4152 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 45184000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 45184000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 167186000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 167186000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 212370000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 212370000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 212370000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 212370000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000044 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47562.105263 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47562.105263 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52212.991880 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52212.991880 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51148.843931 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 51148.843931 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51148.843931 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 51148.843931 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 3772.485305 # Cycle average of tags in use
system.cpu.l2cache.total_refs 677 # Total number of references to valid blocks.
@@ -396,5 +296,105 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 764 # number of replacements
+system.cpu.dcache.tagsinuse 3288.930576 # Cycle average of tags in use
+system.cpu.dcache.total_refs 168271068 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 40527.713873 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 3288.930576 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.802962 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.802962 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 94753540 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 94753540 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 73517528 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 73517528 # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data 168271068 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 168271068 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 168271068 # number of overall hits
+system.cpu.dcache.overall_hits::total 168271068 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 950 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 950 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 3202 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 3202 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 4152 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 4152 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 4152 # number of overall misses
+system.cpu.dcache.overall_misses::total 4152 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 47084000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 47084000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 173590000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 173590000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 220674000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 220674000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 220674000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 220674000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 94754490 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 94754490 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 73520730 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 73520730 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 168275220 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 168275220 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 168275220 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 168275220 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000010 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.000010 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000044 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.000044 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49562.105263 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 49562.105263 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54212.991880 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 54212.991880 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 53148.843931 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 53148.843931 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 53148.843931 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 53148.843931 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks 649 # number of writebacks
+system.cpu.dcache.writebacks::total 649 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 950 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 950 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3202 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 3202 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 4152 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 45184000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 45184000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 167186000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 167186000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 212370000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 212370000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 212370000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 212370000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000044 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47562.105263 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47562.105263 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52212.991880 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52212.991880 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51148.843931 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 51148.843931 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51148.843931 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 51148.843931 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------