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-rw-r--r--tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini31
-rwxr-xr-xtests/long/se/30.eon/ref/alpha/tru64/simple-timing/simerr1
-rwxr-xr-xtests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout6
-rw-r--r--tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt40
4 files changed, 68 insertions, 10 deletions
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini
index 17feee0a3..b264a599b 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini
@@ -1,7 +1,9 @@
[root]
type=Root
children=system
+eventq_index=0
full_system=false
+sim_quantum=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
+eventq_index=0
init_param=0
kernel=
load_addr_mask=1099511627775
@@ -33,6 +36,7 @@ system_port=system.membus.slave[0]
[system.clk_domain]
type=SrcClockDomain
clock=1000
+eventq_index=0
voltage_domain=system.voltage_domain
[system.cpu]
@@ -45,6 +49,7 @@ do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
+eventq_index=0
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
@@ -71,6 +76,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+eventq_index=0
forward_snoops=true
hit_latency=2
is_top_level=true
@@ -79,6 +85,7 @@ mshrs=4
prefetch_on_access=false
prefetcher=Null
response_latency=2
+sequential_access=false
size=262144
system=system
tags=system.cpu.dcache.tags
@@ -93,11 +100,14 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
+eventq_index=0
hit_latency=2
+sequential_access=false
size=262144
[system.cpu.dtb]
type=AlphaTLB
+eventq_index=0
size=64
[system.cpu.icache]
@@ -106,6 +116,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+eventq_index=0
forward_snoops=true
hit_latency=2
is_top_level=true
@@ -114,6 +125,7 @@ mshrs=4
prefetch_on_access=false
prefetcher=Null
response_latency=2
+sequential_access=false
size=131072
system=system
tags=system.cpu.icache.tags
@@ -128,17 +140,23 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
+eventq_index=0
hit_latency=2
+sequential_access=false
size=131072
[system.cpu.interrupts]
type=AlphaInterrupts
+eventq_index=0
[system.cpu.isa]
type=AlphaISA
+eventq_index=0
+system=system
[system.cpu.itb]
type=AlphaTLB
+eventq_index=0
size=48
[system.cpu.l2cache]
@@ -147,6 +165,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
+eventq_index=0
forward_snoops=true
hit_latency=20
is_top_level=false
@@ -155,6 +174,7 @@ mshrs=20
prefetch_on_access=false
prefetcher=Null
response_latency=20
+sequential_access=false
size=2097152
system=system
tags=system.cpu.l2cache.tags
@@ -169,12 +189,15 @@ type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
+eventq_index=0
hit_latency=20
+sequential_access=false
size=2097152
[system.cpu.toL2Bus]
type=CoherentBus
clk_domain=system.cpu_clk_domain
+eventq_index=0
header_cycles=1
system=system
use_default_range=false
@@ -184,6 +207,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
[system.cpu.tracer]
type=ExeTracer
+eventq_index=0
[system.cpu.workload]
type=LiveProcess
@@ -193,7 +217,8 @@ egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon
+eventq_index=0
+executable=/dist/cpu2000/binaries/alpha/tru64/eon
gid=100
input=cin
max_stack_size=67108864
@@ -207,11 +232,13 @@ uid=100
[system.cpu_clk_domain]
type=SrcClockDomain
clock=500
+eventq_index=0
voltage_domain=system.voltage_domain
[system.membus]
type=CoherentBus
clk_domain=system.clk_domain
+eventq_index=0
header_cycles=1
system=system
use_default_range=false
@@ -224,6 +251,7 @@ type=SimpleMemory
bandwidth=73.000000
clk_domain=system.clk_domain
conf_table_reported=true
+eventq_index=0
in_addr_map=true
latency=30000
latency_var=0
@@ -233,5 +261,6 @@ port=system.membus.master[0]
[system.voltage_domain]
type=VoltageDomain
+eventq_index=0
voltage=1.000000
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simerr b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simerr
index 860580eeb..abe1622a9 100755
--- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simerr
+++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simerr
@@ -49,4 +49,3 @@ Writing to chair.cook.ppm
13 8 14
14 8 14
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
-hack: be nice to actually delete the event here
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout
index b94ac7377..ab67caf1c 100755
--- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout
@@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 24 2013 03:08:53
-gem5 started Sep 28 2013 09:53:14
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:27:55
+gem5 started Jan 22 2014 17:48:27
+gem5 executing on u200540-lin
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt
index 3ed6163c0..143a0b323 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt
@@ -4,13 +4,15 @@ sim_seconds 0.567335 # Nu
sim_ticks 567335093000 # Number of ticks simulated
final_tick 567335093000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1598767 # Simulator instruction rate (inst/s)
-host_op_rate 1598767 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2275187152 # Simulator tick rate (ticks/s)
-host_mem_usage 229960 # Number of bytes of host memory used
-host_seconds 249.36 # Real time elapsed on the host
+host_inst_rate 1478735 # Simulator instruction rate (inst/s)
+host_op_rate 1478735 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2104370306 # Simulator tick rate (ticks/s)
+host_mem_usage 235572 # Number of bytes of host memory used
+host_seconds 269.60 # Real time elapsed on the host
sim_insts 398664609 # Number of instructions simulated
sim_ops 398664609 # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage 1 # Voltage in Volts
+system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 205120 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 254016 # Number of bytes read from this memory
system.physmem.bytes_read::total 459136 # Number of bytes read from this memory
@@ -42,6 +44,7 @@ system.membus.reqLayer0.occupancy 7174000 # La
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 64566000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
+system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
@@ -106,6 +109,15 @@ system.cpu.icache.tags.warmup_cycle 0 # Cy
system.cpu.icache.tags.occ_blocks::cpu.inst 1795.138964 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.876533 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.876533 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024 1904 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1 142 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2 85 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3 251 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4 1375 # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024 0.929688 # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses 797333005 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 797333005 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 398660993 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 398660993 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 398660993 # number of demand (read+write) hits
@@ -188,6 +200,15 @@ system.cpu.l2cache.tags.occ_percent::writebacks 0.011339
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.084548 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.019241 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.115127 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024 4566 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1 135 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2 75 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3 497 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3787 # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024 0.139343 # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses 75560 # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses 75560 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst 468 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 123 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 591 # number of ReadReq hits
@@ -320,6 +341,15 @@ system.cpu.dcache.tags.warmup_cycle 0 # Cy
system.cpu.dcache.tags.occ_blocks::cpu.data 3288.930576 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.802962 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.802962 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024 3388 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 39 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3 210 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4 3112 # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024 0.827148 # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses 336554592 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 336554592 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 94753540 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 94753540 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 73517528 # number of WriteReq hits