summaryrefslogtreecommitdiff
path: root/tests/long/se/30.eon/ref/alpha
diff options
context:
space:
mode:
Diffstat (limited to 'tests/long/se/30.eon/ref/alpha')
-rw-r--r--tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini240
-rwxr-xr-xtests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simerr52
-rwxr-xr-xtests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout14
-rw-r--r--tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt314
-rw-r--r--tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini535
-rwxr-xr-xtests/long/se/30.eon/ref/alpha/tru64/o3-timing/simerr52
-rwxr-xr-xtests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout14
-rw-r--r--tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt516
-rw-r--r--tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini102
-rwxr-xr-xtests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simerr52
-rwxr-xr-xtests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simout14
-rw-r--r--tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt77
-rw-r--r--tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini205
-rwxr-xr-xtests/long/se/30.eon/ref/alpha/tru64/simple-timing/simerr52
-rwxr-xr-xtests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout14
-rw-r--r--tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt265
16 files changed, 2518 insertions, 0 deletions
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini
new file mode 100644
index 000000000..16e4d1756
--- /dev/null
+++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini
@@ -0,0 +1,240 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=InOrderCPU
+children=dcache dtb icache itb l2cache toL2Bus tracer workload
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+activity=0
+cachePorts=2
+checker=Null
+choiceCtrBits=2
+choicePredictorSize=8192
+clock=500
+cpu_id=0
+dataMemPort=dcache_port
+defer_registration=false
+div16Latency=1
+div16RepeatRate=1
+div24Latency=1
+div24RepeatRate=1
+div32Latency=1
+div32RepeatRate=1
+div8Latency=1
+div8RepeatRate=1
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+fetchBuffSize=4
+fetchMemPort=icache_port
+functionTrace=false
+functionTraceStart=0
+function_trace=false
+function_trace_start=0
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+itb=system.cpu.itb
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+memBlockSize=64
+multLatency=1
+multRepeatRate=1
+numThreads=1
+phase=0
+predType=tournament
+progress_interval=0
+stageTracing=false
+stageWidth=4
+system=system
+threadModel=SMT
+tracer=system.cpu.tracer
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=262144
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.dtb]
+type=AlphaTLB
+size=64
+
+[system.cpu.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=131072
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.itb]
+type=AlphaTLB
+size=48
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=false
+latency=10000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=100000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=2097152
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[2]
+
+[system.cpu.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
+cwd=build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/inorder-timing
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simerr b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simerr
new file mode 100755
index 000000000..860580eeb
--- /dev/null
+++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simerr
@@ -0,0 +1,52 @@
+warn: Sockets disabled, not accepting gdb connections
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+getting pixel output filename pixels_out.cook
+opening control file chair.control.cook
+opening camera file chair.camera
+opening surfaces file chair.surfaces
+reading data
+processing 8parts
+Grid measure is 6 by 3.0001 by 6
+cell dimension is 0.863065
+Creating grid for list of length 21
+Grid size = 7 by 4 by 7
+Total occupancy = 236
+reading control stream
+reading camera stream
+Writing to chair.cook.ppm
+calculating 15 by 15 image with 196 samples
+col 0. . .
+col 1. . .
+col 2. . .
+col 3. . .
+col 4. . .
+col 5. . .
+col 6. . .
+col 7. . .
+col 8. . .
+col 9. . .
+col 10. . .
+col 11. . .
+col 12. . .
+col 13. . .
+col 14. . .
+Writing to chair.cook.ppm
+0 8 14
+1 8 14
+2 8 14
+3 8 14
+4 8 14
+5 8 14
+6 8 14
+7 8 14
+8 8 14
+9 8 14
+10 8 14
+11 8 14
+12 8 14
+13 8 14
+14 8 14
+warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout
new file mode 100755
index 000000000..1c2a18294
--- /dev/null
+++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout
@@ -0,0 +1,14 @@
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 05:24:12
+gem5 executing on zizzer
+command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/inorder-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+info: Increasing stack size by one page.
+Eon, Version 1.1
+info: Increasing stack size by one page.
+OO-style eon Time= 0.133333
+Exiting @ tick 139995113500 because target called exit()
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt
new file mode 100644
index 000000000..a04efd18a
--- /dev/null
+++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt
@@ -0,0 +1,314 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 0.139995 # Number of seconds simulated
+sim_ticks 139995113500 # Number of ticks simulated
+final_tick 139995113500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 118986 # Simulator instruction rate (inst/s)
+host_tick_rate 41783300 # Simulator tick rate (ticks/s)
+host_mem_usage 214012 # Number of bytes of host memory used
+host_seconds 3350.50 # Real time elapsed on the host
+sim_insts 398664595 # Number of instructions simulated
+system.physmem.bytes_read 469184 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 214784 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 0 # Number of bytes written to this memory
+system.physmem.num_reads 7331 # Number of read requests responded to by this memory
+system.physmem.num_writes 0 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 3351431 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 1534225 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total 3351431 # Total bandwidth to/from this memory (bytes/s)
+system.cpu.dtb.fetch_hits 0 # ITB hits
+system.cpu.dtb.fetch_misses 0 # ITB misses
+system.cpu.dtb.fetch_acv 0 # ITB acv
+system.cpu.dtb.fetch_accesses 0 # ITB accesses
+system.cpu.dtb.read_hits 94755013 # DTB read hits
+system.cpu.dtb.read_misses 21 # DTB read misses
+system.cpu.dtb.read_acv 0 # DTB read access violations
+system.cpu.dtb.read_accesses 94755034 # DTB read accesses
+system.cpu.dtb.write_hits 73522045 # DTB write hits
+system.cpu.dtb.write_misses 35 # DTB write misses
+system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.write_accesses 73522080 # DTB write accesses
+system.cpu.dtb.data_hits 168277058 # DTB hits
+system.cpu.dtb.data_misses 56 # DTB misses
+system.cpu.dtb.data_acv 0 # DTB access violations
+system.cpu.dtb.data_accesses 168277114 # DTB accesses
+system.cpu.itb.fetch_hits 48859849 # ITB hits
+system.cpu.itb.fetch_misses 44521 # ITB misses
+system.cpu.itb.fetch_acv 0 # ITB acv
+system.cpu.itb.fetch_accesses 48904370 # ITB accesses
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.read_acv 0 # DTB read access violations
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.itb.write_acv 0 # DTB write access violations
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.data_hits 0 # DTB hits
+system.cpu.itb.data_misses 0 # DTB misses
+system.cpu.itb.data_acv 0 # DTB access violations
+system.cpu.itb.data_accesses 0 # DTB accesses
+system.cpu.workload.num_syscalls 215 # Number of system calls
+system.cpu.numCycles 279990228 # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.contextSwitches 1 # Number of context switches
+system.cpu.threadCycles 279561038 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
+system.cpu.timesIdled 6809 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 13513618 # Number of cycles cpu's stages were not processed
+system.cpu.runCycles 266476610 # Number of cycles cpu stages are processed.
+system.cpu.activity 95.173539 # Percentage of cycles cpu is active
+system.cpu.comLoads 94754489 # Number of Load instructions committed
+system.cpu.comStores 73520729 # Number of Store instructions committed
+system.cpu.comBranches 44587532 # Number of Branches instructions committed
+system.cpu.comNops 23089775 # Number of Nop instructions committed
+system.cpu.comNonSpec 215 # Number of Non-Speculative instructions committed
+system.cpu.comInts 112239074 # Number of Integer instructions committed
+system.cpu.comFloats 50439198 # Number of Floating Point instructions committed
+system.cpu.committedInsts 398664595 # Number of Instructions Simulated (Per-Thread)
+system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread)
+system.cpu.committedInsts_total 398664595 # Number of Instructions Simulated (Total)
+system.cpu.cpi 0.702320 # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.smt_cpi no_value # CPI: Total SMT-CPI
+system.cpu.cpi_total 0.702320 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.423852 # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.smt_ipc no_value # IPC: Total SMT-IPC
+system.cpu.ipc_total 1.423852 # IPC: Total IPC of All Threads
+system.cpu.branch_predictor.lookups 53456377 # Number of BP lookups
+system.cpu.branch_predictor.condPredicted 30648707 # Number of conditional branches predicted
+system.cpu.branch_predictor.condIncorrect 15206922 # Number of conditional branches incorrect
+system.cpu.branch_predictor.BTBLookups 35068414 # Number of BTB lookups
+system.cpu.branch_predictor.BTBHits 15659516 # Number of BTB hits
+system.cpu.branch_predictor.usedRAS 8007516 # Number of times the RAS was used to get a target.
+system.cpu.branch_predictor.RASInCorrect 20 # Number of incorrect RAS predictions.
+system.cpu.branch_predictor.BTBHitPct 44.654189 # BTB Hit Percentage
+system.cpu.branch_predictor.predictedTaken 29689183 # Number of Branches Predicted As Taken (True).
+system.cpu.branch_predictor.predictedNotTaken 23767194 # Number of Branches Predicted As Not Taken (False).
+system.cpu.regfile_manager.intRegFileReads 280275252 # Number of Reads from Int. Register File
+system.cpu.regfile_manager.intRegFileWrites 159335859 # Number of Writes to Int. Register File
+system.cpu.regfile_manager.intRegFileAccesses 439611111 # Total Accesses (Read+Write) to the Int. Register File
+system.cpu.regfile_manager.floatRegFileReads 119572386 # Number of Reads from FP Register File
+system.cpu.regfile_manager.floatRegFileWrites 100196481 # Number of Writes to FP Register File
+system.cpu.regfile_manager.floatRegFileAccesses 219768867 # Total Accesses (Read+Write) to the FP Register File
+system.cpu.regfile_manager.regForwards 100597400 # Number of Registers Read Through Forwarding Logic
+system.cpu.agen_unit.agens 168369236 # Number of Address Generations
+system.cpu.execution_unit.predictedTakenIncorrect 14604498 # Number of Branches Incorrectly Predicted As Taken.
+system.cpu.execution_unit.predictedNotTakenIncorrect 601765 # Number of Branches Incorrectly Predicted As Not Taken).
+system.cpu.execution_unit.mispredicted 15206263 # Number of Branches Incorrectly Predicted
+system.cpu.execution_unit.predicted 29381288 # Number of Branches Incorrectly Predicted
+system.cpu.execution_unit.mispredictPct 34.104279 # Percentage of Incorrect Branches Predicts
+system.cpu.execution_unit.executions 205417549 # Number of Instructions Executed.
+system.cpu.mult_div_unit.multiplies 2124324 # Number of Multipy Operations Executed
+system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
+system.cpu.stage0.idleCycles 78021134 # Number of cycles 0 instructions are processed.
+system.cpu.stage0.runCycles 201969094 # Number of cycles 1+ instructions are processed.
+system.cpu.stage0.utilization 72.134337 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage1.idleCycles 107567321 # Number of cycles 0 instructions are processed.
+system.cpu.stage1.runCycles 172422907 # Number of cycles 1+ instructions are processed.
+system.cpu.stage1.utilization 61.581759 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage2.idleCycles 102759298 # Number of cycles 0 instructions are processed.
+system.cpu.stage2.runCycles 177230930 # Number of cycles 1+ instructions are processed.
+system.cpu.stage2.utilization 63.298970 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage3.idleCycles 181219893 # Number of cycles 0 instructions are processed.
+system.cpu.stage3.runCycles 98770335 # Number of cycles 1+ instructions are processed.
+system.cpu.stage3.utilization 35.276351 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.idleCycles 90498113 # Number of cycles 0 instructions are processed.
+system.cpu.stage4.runCycles 189492115 # Number of cycles 1+ instructions are processed.
+system.cpu.stage4.utilization 67.678117 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.icache.replacements 1970 # number of replacements
+system.cpu.icache.tagsinuse 1829.847469 # Cycle average of tags in use
+system.cpu.icache.total_refs 48855472 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 3897 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 12536.687708 # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0 1829.847469 # Average occupied blocks per context
+system.cpu.icache.occ_percent::0 0.893480 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits 48855472 # number of ReadReq hits
+system.cpu.icache.demand_hits 48855472 # number of demand (read+write) hits
+system.cpu.icache.overall_hits 48855472 # number of overall hits
+system.cpu.icache.ReadReq_misses 4376 # number of ReadReq misses
+system.cpu.icache.demand_misses 4376 # number of demand (read+write) misses
+system.cpu.icache.overall_misses 4376 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency 214318500 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency 214318500 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency 214318500 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses 48859848 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses 48859848 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses 48859848 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate 0.000090 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate 0.000090 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate 0.000090 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 48975.891225 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 48975.891225 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 48975.891225 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets 45000 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets 45000 # average number of cycles each access was blocked
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits 479 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits 479 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits 479 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses 3897 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses 3897 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses 3897 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency 185285000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency 185285000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 185285000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000080 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate 0.000080 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate 0.000080 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 47545.547857 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 47545.547857 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 47545.547857 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 764 # number of replacements
+system.cpu.dcache.tagsinuse 3284.892021 # Cycle average of tags in use
+system.cpu.dcache.total_refs 168261959 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 40525.519990 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0 3284.892021 # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0 0.801976 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits 94753265 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits 73508694 # number of WriteReq hits
+system.cpu.dcache.demand_hits 168261959 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits 168261959 # number of overall hits
+system.cpu.dcache.ReadReq_misses 1224 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses 12035 # number of WriteReq misses
+system.cpu.dcache.demand_misses 13259 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses 13259 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency 63830500 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency 626731500 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency 690562000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency 690562000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses 94754489 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses 73520729 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses 168275218 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses 168275218 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate 0.000013 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate 0.000164 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate 0.000079 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate 0.000079 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 52149.101307 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 52075.737432 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 52082.509993 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 52082.509993 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 82468500 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 1848 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 44625.811688 # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks 649 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits 274 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits 8833 # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits 9107 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits 9107 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses 950 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses 3202 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses 4152 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses 4152 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 46185000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency 169537500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 215722500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 215722500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.000044 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48615.789474 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52947.376640 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 51956.286127 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 51956.286127 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.replacements 13 # number of replacements
+system.cpu.l2cache.tagsinuse 3900.004949 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 729 # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 4720 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 0.154449 # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0 3529.472340 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 370.532609 # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0 0.107711 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1 0.011308 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits 658 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits 649 # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits 60 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits 718 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits 718 # number of overall hits
+system.cpu.l2cache.ReadReq_misses 4186 # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses 3145 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses 7331 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses 7331 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency 219209500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency 164966000 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency 384175500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency 384175500 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses 4844 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses 649 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses 3205 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses 8049 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses 8049 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate 0.864162 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate 0.981279 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate 0.910796 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate 0.910796 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 52367.295748 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52453.418124 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 52404.242259 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 52404.242259 # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.writebacks 0 # number of writebacks
+system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses 4186 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses 3145 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses 7331 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses 7331 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 168226500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 126764000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency 294990500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency 294990500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.864162 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.981279 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate 0.910796 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate 0.910796 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40187.888199 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40306.518283 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 40238.780521 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 40238.780521 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+
+---------- End Simulation Statistics ----------
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini
new file mode 100644
index 000000000..0fce2844b
--- /dev/null
+++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini
@@ -0,0 +1,535 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=DerivO3CPU
+children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
+BTBEntries=4096
+BTBTagSize=16
+LFSTSize=1024
+LQEntries=32
+LSQCheckLoads=true
+LSQDepCheckShift=4
+RASSize=16
+SQEntries=32
+SSITSize=1024
+activity=0
+backComSize=5
+cachePorts=200
+checker=Null
+choiceCtrBits=2
+choicePredictorSize=8192
+clock=500
+commitToDecodeDelay=1
+commitToFetchDelay=1
+commitToIEWDelay=1
+commitToRenameDelay=1
+commitWidth=8
+cpu_id=0
+decodeToFetchDelay=1
+decodeToRenameDelay=1
+decodeWidth=8
+defer_registration=false
+dispatchWidth=8
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+fetchToDecodeDelay=1
+fetchTrapLatency=1
+fetchWidth=8
+forwardComSize=5
+fuPool=system.cpu.fuPool
+function_trace=false
+function_trace_start=0
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+iewToCommitDelay=1
+iewToDecodeDelay=1
+iewToFetchDelay=1
+iewToRenameDelay=1
+instShiftAmt=2
+issueToExecuteDelay=1
+issueWidth=8
+itb=system.cpu.itb
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numIQEntries=64
+numPhysFloatRegs=256
+numPhysIntRegs=256
+numROBEntries=192
+numRobs=1
+numThreads=1
+phase=0
+predType=tournament
+progress_interval=0
+renameToDecodeDelay=1
+renameToFetchDelay=1
+renameToIEWDelay=2
+renameToROBDelay=1
+renameWidth=8
+smtCommitPolicy=RoundRobin
+smtFetchPolicy=SingleThread
+smtIQPolicy=Partitioned
+smtIQThreshold=100
+smtLSQPolicy=Partitioned
+smtLSQThreshold=100
+smtNumFetchingThreads=1
+smtROBPolicy=Partitioned
+smtROBThreshold=100
+squashWidth=8
+store_set_clear_period=250000
+system=system
+tracer=system.cpu.tracer
+trapLatency=13
+wbDepth=1
+wbWidth=8
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=262144
+subblock_size=0
+tgts_per_mshr=20
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.dtb]
+type=AlphaTLB
+size=64
+
+[system.cpu.fuPool]
+type=FUPool
+children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
+
+[system.cpu.fuPool.FUList0]
+type=FUDesc
+children=opList
+count=6
+opList=system.cpu.fuPool.FUList0.opList
+
+[system.cpu.fuPool.FUList0.opList]
+type=OpDesc
+issueLat=1
+opClass=IntAlu
+opLat=1
+
+[system.cpu.fuPool.FUList1]
+type=FUDesc
+children=opList0 opList1
+count=2
+opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
+
+[system.cpu.fuPool.FUList1.opList0]
+type=OpDesc
+issueLat=1
+opClass=IntMult
+opLat=3
+
+[system.cpu.fuPool.FUList1.opList1]
+type=OpDesc
+issueLat=19
+opClass=IntDiv
+opLat=20
+
+[system.cpu.fuPool.FUList2]
+type=FUDesc
+children=opList0 opList1 opList2
+count=4
+opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
+
+[system.cpu.fuPool.FUList2.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatAdd
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList1]
+type=OpDesc
+issueLat=1
+opClass=FloatCmp
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList2]
+type=OpDesc
+issueLat=1
+opClass=FloatCvt
+opLat=2
+
+[system.cpu.fuPool.FUList3]
+type=FUDesc
+children=opList0 opList1 opList2
+count=2
+opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
+
+[system.cpu.fuPool.FUList3.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatMult
+opLat=4
+
+[system.cpu.fuPool.FUList3.opList1]
+type=OpDesc
+issueLat=12
+opClass=FloatDiv
+opLat=12
+
+[system.cpu.fuPool.FUList3.opList2]
+type=OpDesc
+issueLat=24
+opClass=FloatSqrt
+opLat=24
+
+[system.cpu.fuPool.FUList4]
+type=FUDesc
+children=opList
+count=0
+opList=system.cpu.fuPool.FUList4.opList
+
+[system.cpu.fuPool.FUList4.opList]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList5]
+type=FUDesc
+children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
+count=4
+opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
+
+[system.cpu.fuPool.FUList5.opList00]
+type=OpDesc
+issueLat=1
+opClass=SimdAdd
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList01]
+type=OpDesc
+issueLat=1
+opClass=SimdAddAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList02]
+type=OpDesc
+issueLat=1
+opClass=SimdAlu
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList03]
+type=OpDesc
+issueLat=1
+opClass=SimdCmp
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList04]
+type=OpDesc
+issueLat=1
+opClass=SimdCvt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList05]
+type=OpDesc
+issueLat=1
+opClass=SimdMisc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList06]
+type=OpDesc
+issueLat=1
+opClass=SimdMult
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList07]
+type=OpDesc
+issueLat=1
+opClass=SimdMultAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList08]
+type=OpDesc
+issueLat=1
+opClass=SimdShift
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList09]
+type=OpDesc
+issueLat=1
+opClass=SimdShiftAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList10]
+type=OpDesc
+issueLat=1
+opClass=SimdSqrt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList11]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatAdd
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList12]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatAlu
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList13]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatCmp
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList14]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatCvt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList15]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatDiv
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList16]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMisc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList17]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMult
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList18]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMultAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList19]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatSqrt
+opLat=1
+
+[system.cpu.fuPool.FUList6]
+type=FUDesc
+children=opList
+count=0
+opList=system.cpu.fuPool.FUList6.opList
+
+[system.cpu.fuPool.FUList6.opList]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList7]
+type=FUDesc
+children=opList0 opList1
+count=4
+opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
+
+[system.cpu.fuPool.FUList7.opList0]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList7.opList1]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList8]
+type=FUDesc
+children=opList
+count=1
+opList=system.cpu.fuPool.FUList8.opList
+
+[system.cpu.fuPool.FUList8.opList]
+type=OpDesc
+issueLat=3
+opClass=IprAccess
+opLat=3
+
+[system.cpu.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=131072
+subblock_size=0
+tgts_per_mshr=20
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.itb]
+type=AlphaTLB
+size=48
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=false
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=2097152
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[2]
+
+[system.cpu.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
+cwd=build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/o3-timing
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simerr b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simerr
new file mode 100755
index 000000000..860580eeb
--- /dev/null
+++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simerr
@@ -0,0 +1,52 @@
+warn: Sockets disabled, not accepting gdb connections
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+getting pixel output filename pixels_out.cook
+opening control file chair.control.cook
+opening camera file chair.camera
+opening surfaces file chair.surfaces
+reading data
+processing 8parts
+Grid measure is 6 by 3.0001 by 6
+cell dimension is 0.863065
+Creating grid for list of length 21
+Grid size = 7 by 4 by 7
+Total occupancy = 236
+reading control stream
+reading camera stream
+Writing to chair.cook.ppm
+calculating 15 by 15 image with 196 samples
+col 0. . .
+col 1. . .
+col 2. . .
+col 3. . .
+col 4. . .
+col 5. . .
+col 6. . .
+col 7. . .
+col 8. . .
+col 9. . .
+col 10. . .
+col 11. . .
+col 12. . .
+col 13. . .
+col 14. . .
+Writing to chair.cook.ppm
+0 8 14
+1 8 14
+2 8 14
+3 8 14
+4 8 14
+5 8 14
+6 8 14
+7 8 14
+8 8 14
+9 8 14
+10 8 14
+11 8 14
+12 8 14
+13 8 14
+14 8 14
+warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout
new file mode 100755
index 000000000..137fd0ee8
--- /dev/null
+++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout
@@ -0,0 +1,14 @@
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 05:24:12
+gem5 executing on zizzer
+command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/o3-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+info: Increasing stack size by one page.
+Eon, Version 1.1
+info: Increasing stack size by one page.
+OO-style eon Time= 0.083333
+Exiting @ tick 89480174500 because target called exit()
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt
new file mode 100644
index 000000000..28785f469
--- /dev/null
+++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt
@@ -0,0 +1,516 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 0.089480 # Number of seconds simulated
+sim_ticks 89480174500 # Number of ticks simulated
+final_tick 89480174500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 190161 # Simulator instruction rate (inst/s)
+host_tick_rate 45305657 # Simulator tick rate (ticks/s)
+host_mem_usage 214676 # Number of bytes of host memory used
+host_seconds 1975.03 # Real time elapsed on the host
+sim_insts 375574794 # Number of instructions simulated
+system.physmem.bytes_read 475840 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 219968 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 0 # Number of bytes written to this memory
+system.physmem.num_reads 7435 # Number of read requests responded to by this memory
+system.physmem.num_writes 0 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 5317826 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 2458288 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total 5317826 # Total bandwidth to/from this memory (bytes/s)
+system.cpu.dtb.fetch_hits 0 # ITB hits
+system.cpu.dtb.fetch_misses 0 # ITB misses
+system.cpu.dtb.fetch_acv 0 # ITB acv
+system.cpu.dtb.fetch_accesses 0 # ITB accesses
+system.cpu.dtb.read_hits 105444914 # DTB read hits
+system.cpu.dtb.read_misses 94699 # DTB read misses
+system.cpu.dtb.read_acv 48617 # DTB read access violations
+system.cpu.dtb.read_accesses 105539613 # DTB read accesses
+system.cpu.dtb.write_hits 79763652 # DTB write hits
+system.cpu.dtb.write_misses 1536 # DTB write misses
+system.cpu.dtb.write_acv 1 # DTB write access violations
+system.cpu.dtb.write_accesses 79765188 # DTB write accesses
+system.cpu.dtb.data_hits 185208566 # DTB hits
+system.cpu.dtb.data_misses 96235 # DTB misses
+system.cpu.dtb.data_acv 48618 # DTB access violations
+system.cpu.dtb.data_accesses 185304801 # DTB accesses
+system.cpu.itb.fetch_hits 57904086 # ITB hits
+system.cpu.itb.fetch_misses 346 # ITB misses
+system.cpu.itb.fetch_acv 0 # ITB acv
+system.cpu.itb.fetch_accesses 57904432 # ITB accesses
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.read_acv 0 # DTB read access violations
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.itb.write_acv 0 # DTB write access violations
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.data_hits 0 # DTB hits
+system.cpu.itb.data_misses 0 # DTB misses
+system.cpu.itb.data_acv 0 # DTB access violations
+system.cpu.itb.data_accesses 0 # DTB accesses
+system.cpu.workload.num_syscalls 215 # Number of system calls
+system.cpu.numCycles 178960351 # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.BPredUnit.lookups 56765606 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 33143039 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 3552012 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 40427205 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 32022628 # Number of BTB hits
+system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.BPredUnit.usedRAS 10686505 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 1330 # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 59866357 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 502938652 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 56765606 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 42709133 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 93526616 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 12701088 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 16326839 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 180 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 7643 # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines 57904086 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 1110763 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 178838548 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.812250 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.245901 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 85311932 47.70% 47.70% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 8035871 4.49% 52.20% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 9868460 5.52% 57.71% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 6372149 3.56% 61.28% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 13508487 7.55% 68.83% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 9517347 5.32% 74.15% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 5905302 3.30% 77.46% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 3555081 1.99% 79.44% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 36763919 20.56% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total 178838548 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.317197 # Number of branch fetches per cycle
+system.cpu.fetch.rate 2.810336 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 65738845 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 12641259 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 87702735 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 3649079 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 9106630 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 10252982 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 4580 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 491283130 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 12139 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 9106630 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 70077435 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 4396073 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 392991 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 87026850 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 7838569 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 478183111 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 34338 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 6474620 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 310467420 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 626927534 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 331115388 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 295812146 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 259532319 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 50935101 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 38371 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 296 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 21811876 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 110641644 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 85552281 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 8662202 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 5906832 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 433013718 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 258 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 418626838 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 2003473 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 56038444 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 32198216 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 43 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 178838548 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 2.340809 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 2.008173 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 44336411 24.79% 24.79% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 29007268 16.22% 41.01% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 27775406 15.53% 56.54% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 26238037 14.67% 71.21% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 22251353 12.44% 83.66% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 15664112 8.76% 92.41% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 8263195 4.62% 97.03% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 3972623 2.22% 99.26% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 1330143 0.74% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 178838548 # Number of insts issued each cycle
+system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 135690 1.14% 1.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 1.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 1.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 41926 0.35% 1.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 2442 0.02% 1.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 8992 0.08% 1.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 1877041 15.76% 17.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 1762283 14.79% 32.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 32.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 32.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 5120089 42.98% 75.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 2964035 24.88% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
+system.cpu.iq.FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 164031789 39.18% 39.19% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 2126165 0.51% 39.70% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 39.70% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 33716465 8.05% 47.75% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 7893369 1.89% 49.64% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 2899949 0.69% 50.33% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 16711518 3.99% 54.32% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 1573138 0.38% 54.70% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.70% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 108174365 25.84% 80.54% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 81466499 19.46% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::total 418626838 # Type of FU issued
+system.cpu.iq.rate 2.339216 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 11912498 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.028456 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 681277012 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 289109429 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 241633599 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 348731183 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 199993522 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 164553982 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 252486483 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 178019272 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 13980098 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread0.squashedLoads 15887158 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 143607 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 50570 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 12031553 # Number of stores squashed
+system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread0.rescheduledLoads 233419 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
+system.cpu.iew.iewSquashCycles 9106630 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 2382208 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 372749 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 458676643 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 2278358 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 110641644 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 85552281 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 258 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 129 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 14 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 50570 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 3441219 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 544657 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 3985876 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 409944817 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 105588265 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 8682021 # Number of squashed instructions skipped in execute
+system.cpu.iew.exec_swp 0 # number of swp insts executed
+system.cpu.iew.exec_nop 25662667 # number of nop insts executed
+system.cpu.iew.exec_refs 185353481 # number of memory reference insts executed
+system.cpu.iew.exec_branches 48120403 # Number of branches executed
+system.cpu.iew.exec_stores 79765216 # Number of stores executed
+system.cpu.iew.exec_rate 2.290702 # Inst execution rate
+system.cpu.iew.wb_sent 407421919 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 406187581 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 197894075 # num instructions producing a value
+system.cpu.iew.wb_consumers 277422150 # num instructions consuming a value
+system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
+system.cpu.iew.wb_rate 2.269707 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.713332 # average fanout of values written-back
+system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.commit.commitCommittedInsts 398664569 # The number of committed instructions
+system.cpu.commit.commitSquashedInsts 60016815 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 3547729 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 169731918 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 2.348790 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.858024 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 70140218 41.32% 41.32% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 25651558 15.11% 56.44% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 14667534 8.64% 65.08% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 12267165 7.23% 72.31% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 9098146 5.36% 77.67% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 6161287 3.63% 81.30% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 5543706 3.27% 84.56% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 3203239 1.89% 86.45% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 22999065 13.55% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 169731918 # Number of insts commited each cycle
+system.cpu.commit.count 398664569 # Number of instructions committed
+system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
+system.cpu.commit.refs 168275214 # Number of memory references committed
+system.cpu.commit.loads 94754486 # Number of loads committed
+system.cpu.commit.membars 0 # Number of memory barriers committed
+system.cpu.commit.branches 44587530 # Number of branches committed
+system.cpu.commit.fp_insts 155295106 # Number of committed floating point instructions.
+system.cpu.commit.int_insts 316365825 # Number of committed integer instructions.
+system.cpu.commit.function_calls 8007752 # Number of function calls committed.
+system.cpu.commit.bw_lim_events 22999065 # number cycles where commit BW limit reached
+system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
+system.cpu.rob.rob_reads 605411260 # The number of ROB reads
+system.cpu.rob.rob_writes 926487800 # The number of ROB writes
+system.cpu.timesIdled 2712 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 121803 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts 375574794 # Number of Instructions Simulated
+system.cpu.committedInsts_total 375574794 # Number of Instructions Simulated
+system.cpu.cpi 0.476497 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.476497 # CPI: Total CPI of All Threads
+system.cpu.ipc 2.098648 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 2.098648 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 409675274 # number of integer regfile reads
+system.cpu.int_regfile_writes 175727060 # number of integer regfile writes
+system.cpu.fp_regfile_reads 159328411 # number of floating regfile reads
+system.cpu.fp_regfile_writes 105866122 # number of floating regfile writes
+system.cpu.misc_regfile_reads 350572 # number of misc regfile reads
+system.cpu.misc_regfile_writes 1 # number of misc regfile writes
+system.cpu.icache.replacements 2110 # number of replacements
+system.cpu.icache.tagsinuse 1834.326922 # Cycle average of tags in use
+system.cpu.icache.total_refs 57898804 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 4037 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 14342.037156 # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0 1834.326922 # Average occupied blocks per context
+system.cpu.icache.occ_percent::0 0.895667 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits 57898804 # number of ReadReq hits
+system.cpu.icache.demand_hits 57898804 # number of demand (read+write) hits
+system.cpu.icache.overall_hits 57898804 # number of overall hits
+system.cpu.icache.ReadReq_misses 5282 # number of ReadReq misses
+system.cpu.icache.demand_misses 5282 # number of demand (read+write) misses
+system.cpu.icache.overall_misses 5282 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency 167914000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency 167914000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency 167914000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses 57904086 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses 57904086 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses 57904086 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate 0.000091 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate 0.000091 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate 0.000091 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 31789.852329 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 31789.852329 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 31789.852329 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits 1245 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits 1245 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits 1245 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses 4037 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses 4037 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses 4037 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency 123459000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency 123459000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 123459000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000070 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate 0.000070 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate 0.000070 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 30581.867724 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 30581.867724 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 30581.867724 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 793 # number of replacements
+system.cpu.dcache.tagsinuse 3296.196945 # Cycle average of tags in use
+system.cpu.dcache.total_refs 164730953 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 4193 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 39287.134033 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0 3296.196945 # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0 0.804736 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits 91229707 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits 73501239 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits 7 # number of LoadLockedReq hits
+system.cpu.dcache.demand_hits 164730946 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits 164730946 # number of overall hits
+system.cpu.dcache.ReadReq_misses 1678 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses 19489 # number of WriteReq misses
+system.cpu.dcache.demand_misses 21167 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses 21167 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency 55919500 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency 568883000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency 624802500 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency 624802500 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses 91231385 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses 73520728 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses 7 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses 164752113 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses 164752113 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate 0.000265 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate 0.000128 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate 0.000128 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 33325.089392 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 29189.953307 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 29517.763500 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 29517.763500 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 13000 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 2600 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks 671 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits 680 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits 16294 # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits 16974 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits 16974 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses 998 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses 3195 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses 4193 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses 4193 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 31703500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency 113133500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 144837000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 144837000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.000011 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.000043 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 31767.034068 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35409.546166 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 34542.570952 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 34542.570952 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.replacements 10 # number of replacements
+system.cpu.l2cache.tagsinuse 4007.455925 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 810 # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 4847 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 0.167114 # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0 3629.785283 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 377.670641 # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0 0.110772 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1 0.011526 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits 730 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits 671 # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits 65 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits 795 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits 795 # number of overall hits
+system.cpu.l2cache.ReadReq_misses 4305 # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses 3130 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses 7435 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses 7435 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency 148163500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency 108392000 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency 256555500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency 256555500 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses 5035 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses 671 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses 3195 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses 8230 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses 8230 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate 0.855015 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate 0.979656 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate 0.903402 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate 0.903402 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 34416.608595 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34630.031949 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34506.455952 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34506.455952 # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.writebacks 0 # number of writebacks
+system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses 4305 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses 3130 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses 7435 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses 7435 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 134314000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 98534000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency 232848000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency 232848000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.855015 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.979656 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate 0.903402 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate 0.903402 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31199.535424 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31480.511182 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31317.821116 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31317.821116 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+
+---------- End Simulation Statistics ----------
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini
new file mode 100644
index 000000000..8310ba9e4
--- /dev/null
+++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini
@@ -0,0 +1,102 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=AtomicSimpleCPU
+children=dtb itb tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+simulate_data_stalls=false
+simulate_inst_stalls=false
+system=system
+tracer=system.cpu.tracer
+width=1
+workload=system.cpu.workload
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
+
+[system.cpu.dtb]
+type=AlphaTLB
+size=64
+
+[system.cpu.itb]
+type=AlphaTLB
+size=48
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
+cwd=build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/simple-atomic
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simerr b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simerr
new file mode 100755
index 000000000..860580eeb
--- /dev/null
+++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simerr
@@ -0,0 +1,52 @@
+warn: Sockets disabled, not accepting gdb connections
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+getting pixel output filename pixels_out.cook
+opening control file chair.control.cook
+opening camera file chair.camera
+opening surfaces file chair.surfaces
+reading data
+processing 8parts
+Grid measure is 6 by 3.0001 by 6
+cell dimension is 0.863065
+Creating grid for list of length 21
+Grid size = 7 by 4 by 7
+Total occupancy = 236
+reading control stream
+reading camera stream
+Writing to chair.cook.ppm
+calculating 15 by 15 image with 196 samples
+col 0. . .
+col 1. . .
+col 2. . .
+col 3. . .
+col 4. . .
+col 5. . .
+col 6. . .
+col 7. . .
+col 8. . .
+col 9. . .
+col 10. . .
+col 11. . .
+col 12. . .
+col 13. . .
+col 14. . .
+Writing to chair.cook.ppm
+0 8 14
+1 8 14
+2 8 14
+3 8 14
+4 8 14
+5 8 14
+6 8 14
+7 8 14
+8 8 14
+9 8 14
+10 8 14
+11 8 14
+12 8 14
+13 8 14
+14 8 14
+warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simout b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simout
new file mode 100755
index 000000000..3a628f576
--- /dev/null
+++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simout
@@ -0,0 +1,14 @@
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 05:24:12
+gem5 executing on zizzer
+command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/simple-atomic
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+info: Increasing stack size by one page.
+Eon, Version 1.1
+info: Increasing stack size by one page.
+OO-style eon Time= 0.183333
+Exiting @ tick 199332411500 because target called exit()
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt
new file mode 100644
index 000000000..3ed2b47f1
--- /dev/null
+++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt
@@ -0,0 +1,77 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 0.199332 # Number of seconds simulated
+sim_ticks 199332411500 # Number of ticks simulated
+final_tick 199332411500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 3927016 # Simulator instruction rate (inst/s)
+host_tick_rate 1963508553 # Simulator tick rate (ticks/s)
+host_mem_usage 204908 # Number of bytes of host memory used
+host_seconds 101.52 # Real time elapsed on the host
+sim_insts 398664595 # Number of instructions simulated
+system.physmem.bytes_read 2257107875 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 1594658604 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 492356798 # Number of bytes written to this memory
+system.physmem.num_reads 493419140 # Number of read requests responded to by this memory
+system.physmem.num_writes 73520729 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 11323336020 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 7999996548 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 2470028804 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 13793364824 # Total bandwidth to/from this memory (bytes/s)
+system.cpu.dtb.fetch_hits 0 # ITB hits
+system.cpu.dtb.fetch_misses 0 # ITB misses
+system.cpu.dtb.fetch_acv 0 # ITB acv
+system.cpu.dtb.fetch_accesses 0 # ITB accesses
+system.cpu.dtb.read_hits 94754489 # DTB read hits
+system.cpu.dtb.read_misses 21 # DTB read misses
+system.cpu.dtb.read_acv 0 # DTB read access violations
+system.cpu.dtb.read_accesses 94754510 # DTB read accesses
+system.cpu.dtb.write_hits 73520729 # DTB write hits
+system.cpu.dtb.write_misses 35 # DTB write misses
+system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.write_accesses 73520764 # DTB write accesses
+system.cpu.dtb.data_hits 168275218 # DTB hits
+system.cpu.dtb.data_misses 56 # DTB misses
+system.cpu.dtb.data_acv 0 # DTB access violations
+system.cpu.dtb.data_accesses 168275274 # DTB accesses
+system.cpu.itb.fetch_hits 398664651 # ITB hits
+system.cpu.itb.fetch_misses 173 # ITB misses
+system.cpu.itb.fetch_acv 0 # ITB acv
+system.cpu.itb.fetch_accesses 398664824 # ITB accesses
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.read_acv 0 # DTB read access violations
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.itb.write_acv 0 # DTB write access violations
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.data_hits 0 # DTB hits
+system.cpu.itb.data_misses 0 # DTB misses
+system.cpu.itb.data_acv 0 # DTB access violations
+system.cpu.itb.data_accesses 0 # DTB accesses
+system.cpu.workload.num_syscalls 215 # Number of system calls
+system.cpu.numCycles 398664824 # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.num_insts 398664595 # Number of instructions executed
+system.cpu.num_int_alu_accesses 316365907 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 155295119 # Number of float alu accesses
+system.cpu.num_func_calls 16015498 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 25997787 # number of instructions that are conditional controls
+system.cpu.num_int_insts 316365907 # number of integer instructions
+system.cpu.num_fp_insts 155295119 # number of float instructions
+system.cpu.num_int_register_reads 372938760 # number of times the integer registers were read
+system.cpu.num_int_register_writes 159335860 # number of times the integer registers were written
+system.cpu.num_fp_register_reads 151776196 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 100196481 # number of times the floating registers were written
+system.cpu.num_mem_refs 168275274 # number of memory refs
+system.cpu.num_load_insts 94754510 # Number of load instructions
+system.cpu.num_store_insts 73520764 # Number of store instructions
+system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.num_busy_cycles 398664824 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+
+---------- End Simulation Statistics ----------
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini
new file mode 100644
index 000000000..63aac5a1a
--- /dev/null
+++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini
@@ -0,0 +1,205 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=TimingSimpleCPU
+children=dcache dtb icache itb l2cache toL2Bus tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+system=system
+tracer=system.cpu.tracer
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=262144
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.dtb]
+type=AlphaTLB
+size=64
+
+[system.cpu.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=131072
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.itb]
+type=AlphaTLB
+size=48
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=false
+latency=10000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=100000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=2097152
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[2]
+
+[system.cpu.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
+cwd=build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/simple-timing
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simerr b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simerr
new file mode 100755
index 000000000..860580eeb
--- /dev/null
+++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simerr
@@ -0,0 +1,52 @@
+warn: Sockets disabled, not accepting gdb connections
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+getting pixel output filename pixels_out.cook
+opening control file chair.control.cook
+opening camera file chair.camera
+opening surfaces file chair.surfaces
+reading data
+processing 8parts
+Grid measure is 6 by 3.0001 by 6
+cell dimension is 0.863065
+Creating grid for list of length 21
+Grid size = 7 by 4 by 7
+Total occupancy = 236
+reading control stream
+reading camera stream
+Writing to chair.cook.ppm
+calculating 15 by 15 image with 196 samples
+col 0. . .
+col 1. . .
+col 2. . .
+col 3. . .
+col 4. . .
+col 5. . .
+col 6. . .
+col 7. . .
+col 8. . .
+col 9. . .
+col 10. . .
+col 11. . .
+col 12. . .
+col 13. . .
+col 14. . .
+Writing to chair.cook.ppm
+0 8 14
+1 8 14
+2 8 14
+3 8 14
+4 8 14
+5 8 14
+6 8 14
+7 8 14
+8 8 14
+9 8 14
+10 8 14
+11 8 14
+12 8 14
+13 8 14
+14 8 14
+warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout
new file mode 100755
index 000000000..06075d86e
--- /dev/null
+++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout
@@ -0,0 +1,14 @@
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 05:24:12
+gem5 executing on zizzer
+command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/simple-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+info: Increasing stack size by one page.
+Eon, Version 1.1
+info: Increasing stack size by one page.
+OO-style eon Time= 0.566667
+Exiting @ tick 567343170000 because target called exit()
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt
new file mode 100644
index 000000000..af7a7f90d
--- /dev/null
+++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt
@@ -0,0 +1,265 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 0.567343 # Number of seconds simulated
+sim_ticks 567343170000 # Number of ticks simulated
+final_tick 567343170000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 1814376 # Simulator instruction rate (inst/s)
+host_tick_rate 2582053806 # Simulator tick rate (ticks/s)
+host_mem_usage 213620 # Number of bytes of host memory used
+host_seconds 219.73 # Real time elapsed on the host
+sim_insts 398664609 # Number of instructions simulated
+system.physmem.bytes_read 459520 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 205120 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 0 # Number of bytes written to this memory
+system.physmem.num_reads 7180 # Number of read requests responded to by this memory
+system.physmem.num_writes 0 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 809951 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 361545 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total 809951 # Total bandwidth to/from this memory (bytes/s)
+system.cpu.dtb.fetch_hits 0 # ITB hits
+system.cpu.dtb.fetch_misses 0 # ITB misses
+system.cpu.dtb.fetch_acv 0 # ITB acv
+system.cpu.dtb.fetch_accesses 0 # ITB accesses
+system.cpu.dtb.read_hits 94754490 # DTB read hits
+system.cpu.dtb.read_misses 21 # DTB read misses
+system.cpu.dtb.read_acv 0 # DTB read access violations
+system.cpu.dtb.read_accesses 94754511 # DTB read accesses
+system.cpu.dtb.write_hits 73520730 # DTB write hits
+system.cpu.dtb.write_misses 35 # DTB write misses
+system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.write_accesses 73520765 # DTB write accesses
+system.cpu.dtb.data_hits 168275220 # DTB hits
+system.cpu.dtb.data_misses 56 # DTB misses
+system.cpu.dtb.data_acv 0 # DTB access violations
+system.cpu.dtb.data_accesses 168275276 # DTB accesses
+system.cpu.itb.fetch_hits 398664666 # ITB hits
+system.cpu.itb.fetch_misses 173 # ITB misses
+system.cpu.itb.fetch_acv 0 # ITB acv
+system.cpu.itb.fetch_accesses 398664839 # ITB accesses
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.read_acv 0 # DTB read access violations
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.itb.write_acv 0 # DTB write access violations
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.data_hits 0 # DTB hits
+system.cpu.itb.data_misses 0 # DTB misses
+system.cpu.itb.data_acv 0 # DTB access violations
+system.cpu.itb.data_accesses 0 # DTB accesses
+system.cpu.workload.num_syscalls 215 # Number of system calls
+system.cpu.numCycles 1134686340 # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.num_insts 398664609 # Number of instructions executed
+system.cpu.num_int_alu_accesses 316365921 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 155295119 # Number of float alu accesses
+system.cpu.num_func_calls 16015498 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 25997790 # number of instructions that are conditional controls
+system.cpu.num_int_insts 316365921 # number of integer instructions
+system.cpu.num_fp_insts 155295119 # number of float instructions
+system.cpu.num_int_register_reads 372938779 # number of times the integer registers were read
+system.cpu.num_int_register_writes 159335870 # number of times the integer registers were written
+system.cpu.num_fp_register_reads 151776196 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 100196481 # number of times the floating registers were written
+system.cpu.num_mem_refs 168275276 # number of memory refs
+system.cpu.num_load_insts 94754511 # Number of load instructions
+system.cpu.num_store_insts 73520765 # Number of store instructions
+system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.num_busy_cycles 1134686340 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.icache.replacements 1769 # number of replacements
+system.cpu.icache.tagsinuse 1795.131074 # Cycle average of tags in use
+system.cpu.icache.total_refs 398660993 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 3673 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 108538.250204 # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0 1795.131074 # Average occupied blocks per context
+system.cpu.icache.occ_percent::0 0.876529 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits 398660993 # number of ReadReq hits
+system.cpu.icache.demand_hits 398660993 # number of demand (read+write) hits
+system.cpu.icache.overall_hits 398660993 # number of overall hits
+system.cpu.icache.ReadReq_misses 3673 # number of ReadReq misses
+system.cpu.icache.demand_misses 3673 # number of demand (read+write) misses
+system.cpu.icache.overall_misses 3673 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency 186032000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency 186032000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency 186032000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses 398664666 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses 398664666 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses 398664666 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate 0.000009 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate 0.000009 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate 0.000009 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 50648.516199 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 50648.516199 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 50648.516199 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses 3673 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses 3673 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses 3673 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency 175013000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency 175013000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 175013000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000009 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate 0.000009 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate 0.000009 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 47648.516199 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 47648.516199 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 47648.516199 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 764 # number of replacements
+system.cpu.dcache.tagsinuse 3288.912598 # Cycle average of tags in use
+system.cpu.dcache.total_refs 168271068 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 40527.713873 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0 3288.912598 # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0 0.802957 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits 94753540 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits 73517528 # number of WriteReq hits
+system.cpu.dcache.demand_hits 168271068 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits 168271068 # number of overall hits
+system.cpu.dcache.ReadReq_misses 950 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses 3202 # number of WriteReq misses
+system.cpu.dcache.demand_misses 4152 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses 4152 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency 48286000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency 176792000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency 225078000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency 225078000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses 94754490 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses 73520730 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses 168275220 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses 168275220 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate 0.000010 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate 0.000044 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 50827.368421 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 55212.991880 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 54209.537572 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 54209.537572 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks 649 # number of writebacks
+system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses 950 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses 3202 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses 4152 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses 4152 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 45436000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency 167186000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 212622000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 212622000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.000044 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 47827.368421 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52212.991880 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 51209.537572 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 51209.537572 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.replacements 13 # number of replacements
+system.cpu.l2cache.tagsinuse 3768.712262 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 656 # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 4572 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 0.143482 # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0 3397.175455 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 371.536808 # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0 0.103674 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1 0.011338 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits 585 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits 649 # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits 60 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits 645 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits 645 # number of overall hits
+system.cpu.l2cache.ReadReq_misses 4038 # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses 3142 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses 7180 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses 7180 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency 209976000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency 163384000 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency 373360000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency 373360000 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses 4623 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses 649 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses 3202 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses 7825 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses 7825 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate 0.873459 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate 0.981262 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate 0.917572 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate 0.917572 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.writebacks 0 # number of writebacks
+system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses 4038 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses 3142 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses 7180 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses 7180 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 161520000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 125680000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency 287200000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency 287200000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.873459 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.981262 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate 0.917572 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate 0.917572 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+
+---------- End Simulation Statistics ----------