diff options
Diffstat (limited to 'tests/long/se/30.eon/ref/alpha')
3 files changed, 660 insertions, 639 deletions
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt index e60710ec5..55abb5639 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.225711 # Nu sim_ticks 225710988500 # Number of ticks simulated final_tick 225710988500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 311102 # Simulator instruction rate (inst/s) -host_op_rate 311102 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 176136084 # Simulator tick rate (ticks/s) -host_mem_usage 304484 # Number of bytes of host memory used -host_seconds 1281.46 # Real time elapsed on the host +host_inst_rate 329346 # Simulator instruction rate (inst/s) +host_op_rate 329346 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 186465123 # Simulator tick rate (ticks/s) +host_mem_usage 304340 # Number of bytes of host memory used +host_seconds 1210.47 # Real time elapsed on the host sim_insts 398664665 # Number of instructions simulated sim_ops 398664665 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -482,6 +482,8 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks::writebacks 3187 # number of writebacks +system.cpu.icache.writebacks::total 3187 # number of writebacks system.cpu.icache.ReadReq_mshr_misses::cpu.inst 5165 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 5165 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 5165 # number of demand (read+write) MSHR misses @@ -528,8 +530,10 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4439 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.160828 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 114772 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 114772 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 654 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 654 # number of Writeback hits +system.cpu.l2cache.WritebackDirty_hits::writebacks 654 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 654 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 3187 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 3187 # number of WritebackClean hits system.cpu.l2cache.ReadExReq_hits::cpu.data 61 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 61 # number of ReadExReq hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1273 # number of ReadCleanReq hits @@ -566,8 +570,10 @@ system.cpu.l2cache.demand_miss_latency::total 593982000 system.cpu.l2cache.overall_miss_latency::cpu.inst 291102500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 302879500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 593982000 # number of overall miss cycles -system.cpu.l2cache.Writeback_accesses::writebacks 654 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 654 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::writebacks 654 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 654 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 3187 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 3187 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 3198 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 3198 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 5165 # number of ReadCleanReq accesses(hits+misses) @@ -668,8 +674,9 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 6132 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 654 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 3304 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 654 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 3187 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 117 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 3198 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 3198 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 5165 # Transaction distribution @@ -677,22 +684,22 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 967 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 13517 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9101 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 22618 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 330560 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 534528 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 308416 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 638976 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 842944 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 13288 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 9330 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 13288 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 9330 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 13288 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 7298000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 9330 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 10485000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 7747500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt index 0e0bba79f..b6e4d84e4 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.067874 # Number of seconds simulated -sim_ticks 67874346000 # Number of ticks simulated -final_tick 67874346000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.067897 # Number of seconds simulated +sim_ticks 67896839000 # Number of ticks simulated +final_tick 67896839000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 238872 # Simulator instruction rate (inst/s) -host_op_rate 238872 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 43169272 # Simulator tick rate (ticks/s) -host_mem_usage 305488 # Number of bytes of host memory used -host_seconds 1572.28 # Real time elapsed on the host +host_inst_rate 250075 # Simulator instruction rate (inst/s) +host_op_rate 250075 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 45208847 # Simulator tick rate (ticks/s) +host_mem_usage 305364 # Number of bytes of host memory used +host_seconds 1501.85 # Real time elapsed on the host sim_insts 375574808 # Number of instructions simulated sim_ops 375574808 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 220544 # Nu system.physmem.num_reads::cpu.inst 3446 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 3989 # Number of read requests responded to by this memory system.physmem.num_reads::total 7435 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 3249298 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3761303 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 7010602 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 3249298 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 3249298 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 3249298 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3761303 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7010602 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 3248222 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3760057 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 7008279 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 3248222 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 3248222 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 3248222 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3760057 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7008279 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 7435 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 7435 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 67874250500 # Total gap between requests +system.physmem.totGap 67896729500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,9 +90,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4258 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1860 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 924 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4260 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1857 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 925 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 329 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 62 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see @@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1352 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 350.437870 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 208.390396 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 346.239962 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 445 32.91% 32.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 293 21.67% 54.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 153 11.32% 65.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 95 7.03% 72.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 63 4.66% 77.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 39 2.88% 80.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 40 2.96% 83.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 30 2.22% 85.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 194 14.35% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1352 # Bytes accessed per row activation -system.physmem.totQLat 65565000 # Total ticks spent queuing -system.physmem.totMemAccLat 204971250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 1351 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 351.928942 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 210.322228 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 345.388131 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 435 32.20% 32.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 296 21.91% 54.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 157 11.62% 65.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 94 6.96% 72.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 63 4.66% 77.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 44 3.26% 80.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 40 2.96% 83.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 30 2.22% 85.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 192 14.21% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1351 # Bytes accessed per row activation +system.physmem.totQLat 64430000 # Total ticks spent queuing +system.physmem.totMemAccLat 203836250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 37175000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8818.43 # Average queueing delay per DRAM burst +system.physmem.avgQLat 8665.77 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27568.43 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 27415.77 # Average memory access latency per DRAM burst system.physmem.avgRdBW 7.01 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 7.01 # Average system read bandwidth in MiByte/s @@ -216,70 +216,70 @@ system.physmem.busUtilRead 0.05 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 6075 # Number of row buffer hits during reads +system.physmem.readRowHits 6082 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.71 # Row buffer hit rate for reads +system.physmem.readRowHitRate 81.80 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 9129018.22 # Average gap between requests -system.physmem.pageHitRate 81.71 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 5866560 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3201000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 32260800 # Energy for read commands per rank (pJ) +system.physmem.avgGap 9132041.63 # Average gap between requests +system.physmem.pageHitRate 81.80 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 5851440 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3192750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 32416800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 4433117520 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2086073460 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 38893911750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 45454431090 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.698264 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 64700624500 # Time in different power states -system.physmem_0.memoryStateTime::REF 2266420000 # Time in different power states +system.physmem_0.refreshEnergy 4434643200 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2090127870 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 38904370500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 45470602560 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.706043 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 64718030250 # Time in different power states +system.physmem_0.memoryStateTime::REF 2267200000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 905970500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 911143500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 4354560 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2376000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 25482600 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 4362120 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2380125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 25529400 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 4433117520 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1937209410 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 39024494250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 45427034340 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.294616 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 64919021500 # Time in different power states -system.physmem_1.memoryStateTime::REF 2266420000 # Time in different power states +system.physmem_1.refreshEnergy 4434643200 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1924310025 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 39049824750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 45441049620 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.270777 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 64961032000 # Time in different power states +system.physmem_1.memoryStateTime::REF 2267200000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 687756000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 668141750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 50012521 # Number of BP lookups -system.cpu.branchPred.condPredicted 28997086 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 979524 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 24735831 # Number of BTB lookups -system.cpu.branchPred.BTBHits 22942844 # Number of BTB hits +system.cpu.branchPred.lookups 50014651 # Number of BP lookups +system.cpu.branchPred.condPredicted 28998018 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 978942 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 24722016 # Number of BTB lookups +system.cpu.branchPred.BTBHits 22941909 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.751458 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 9100143 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 92.799507 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 9101024 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 303 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 102391599 # DTB read hits -system.cpu.dtb.read_misses 62990 # DTB read misses +system.cpu.dtb.read_hits 102396635 # DTB read hits +system.cpu.dtb.read_misses 63118 # DTB read misses system.cpu.dtb.read_acv 49453 # DTB read access violations -system.cpu.dtb.read_accesses 102454589 # DTB read accesses -system.cpu.dtb.write_hits 78819200 # DTB write hits +system.cpu.dtb.read_accesses 102459753 # DTB read accesses +system.cpu.dtb.write_hits 78818401 # DTB write hits system.cpu.dtb.write_misses 1456 # DTB write misses system.cpu.dtb.write_acv 2 # DTB write access violations -system.cpu.dtb.write_accesses 78820656 # DTB write accesses -system.cpu.dtb.data_hits 181210799 # DTB hits -system.cpu.dtb.data_misses 64446 # DTB misses +system.cpu.dtb.write_accesses 78819857 # DTB write accesses +system.cpu.dtb.data_hits 181215036 # DTB hits +system.cpu.dtb.data_misses 64574 # DTB misses system.cpu.dtb.data_acv 49455 # DTB access violations -system.cpu.dtb.data_accesses 181275245 # DTB accesses -system.cpu.itb.fetch_hits 49841893 # ITB hits +system.cpu.dtb.data_accesses 181279610 # DTB accesses +system.cpu.itb.fetch_hits 49842949 # ITB hits system.cpu.itb.fetch_misses 342 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 49842235 # ITB accesses +system.cpu.itb.fetch_accesses 49843291 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -293,140 +293,140 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 135748695 # number of cpu cycles simulated +system.cpu.numCycles 135793681 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 50498280 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 448284151 # Number of instructions fetch has processed -system.cpu.fetch.Branches 50012521 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 32042987 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 83907127 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2061462 # Number of cycles fetch has spent squashing +system.cpu.fetch.icacheStallCycles 50500103 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 448292718 # Number of instructions fetch has processed +system.cpu.fetch.Branches 50014651 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 32042933 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 83951008 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2060866 # Number of cycles fetch has spent squashing system.cpu.fetch.TlbCycles 4 # Number of cycles fetch has spent waiting for tlb system.cpu.fetch.MiscStallCycles 172 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 13448 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 46 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 49841893 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 439921 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 135449808 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.309596 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.352335 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 49842949 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 438776 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 135495214 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.308550 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.352263 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 56539159 41.74% 41.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4401809 3.25% 44.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 7053804 5.21% 50.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 5366390 3.96% 54.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 11526105 8.51% 62.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 7792927 5.75% 68.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5844960 4.32% 72.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1860483 1.37% 74.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 35064171 25.89% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 56579471 41.76% 41.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4403688 3.25% 45.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 7055956 5.21% 50.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 5366912 3.96% 54.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 11526073 8.51% 62.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 7794072 5.75% 68.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5845240 4.31% 72.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1860126 1.37% 74.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 35063676 25.88% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 135449808 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.368420 # Number of branch fetches per cycle -system.cpu.fetch.rate 3.302309 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 43878250 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 15711242 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 70556820 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 4276924 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1026572 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 9420233 # Number of times decode resolved a branch +system.cpu.fetch.rateDist::total 135495214 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.368314 # Number of branch fetches per cycle +system.cpu.fetch.rate 3.301278 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 43850651 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 15792236 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 70529676 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 4296377 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1026274 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 9420515 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 4199 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 443516613 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 443538757 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 13825 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1026572 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 45656178 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 5038667 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 519602 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 72948338 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 10260451 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 440529832 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 437774 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2529018 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 2798103 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 3728351 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 287391913 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 579992044 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 412277767 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 167714276 # Number of floating rename lookups +system.cpu.rename.SquashCycles 1026274 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 45639997 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 5068254 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 519346 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 72928908 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 10312435 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 440551913 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 438641 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2536044 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 2850928 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 3712864 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 287405500 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 580024697 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 412290195 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 167734501 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259532329 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 27859584 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 37459 # count of serializing insts renamed +system.cpu.rename.UndoneMaps 27873171 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 37458 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 301 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 15899092 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 104653375 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 80643825 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 12436283 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 9680421 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 409213494 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.skidInsts 16037778 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 104660927 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 80646144 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 12483488 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 9717177 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 409234709 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 295 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 402403006 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 455901 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 33638980 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 16018200 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 402404750 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 453779 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 33660195 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 16045960 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 80 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 135449808 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.970864 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.211480 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 135495214 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.969882 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.211663 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 21699625 16.02% 16.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 19301136 14.25% 30.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 22441860 16.57% 46.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 18632936 13.76% 60.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 19381094 14.31% 74.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 13936411 10.29% 85.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 9566467 7.06% 92.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 6208123 4.58% 96.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 4282156 3.16% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 21727779 16.04% 16.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 19323046 14.26% 30.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 22437590 16.56% 46.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 18638995 13.76% 60.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 19382000 14.30% 74.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 13933331 10.28% 85.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 9554257 7.05% 92.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 6216386 4.59% 96.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 4281830 3.16% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 135449808 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 135495214 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 249921 1.26% 1.26% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 1.26% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 142099 0.71% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 92744 0.47% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 4235 0.02% 2.46% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 3484759 17.51% 19.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 1673016 8.41% 28.37% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 28.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 28.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.37% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9313907 46.79% 75.16% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4943226 24.84% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 249431 1.25% 1.25% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 1.25% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.25% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 142108 0.71% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 93369 0.47% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 4363 0.02% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 3491173 17.54% 19.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 1672209 8.40% 28.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 28.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 28.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.39% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9312767 46.78% 75.18% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4941825 24.82% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 151496219 37.65% 37.66% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2128363 0.53% 38.19% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 151497707 37.65% 37.66% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2128305 0.53% 38.19% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 38.19% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 37051349 9.21% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 7361129 1.83% 49.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2793884 0.69% 49.92% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 16753499 4.16% 54.08% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 1596248 0.40% 54.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 37050665 9.21% 47.39% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 7361267 1.83% 49.22% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2793686 0.69% 49.92% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 16753119 4.16% 54.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 1596202 0.40% 54.48% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.48% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.48% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.48% # Type of FU issued @@ -448,84 +448,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.48% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.48% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.48% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.48% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 103848617 25.81% 80.28% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 79340117 19.72% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 103852879 25.81% 80.28% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 79337339 19.72% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 402403006 # Type of FU issued -system.cpu.iq.rate 2.964323 # Inst issue rate -system.cpu.iq.fu_busy_cnt 19903907 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.049463 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 615743047 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 258422157 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 234653025 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 344872581 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 184503638 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 162319054 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 242850926 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 179422406 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 19947233 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 402404750 # Type of FU issued +system.cpu.iq.rate 2.963354 # Inst issue rate +system.cpu.iq.fu_busy_cnt 19907245 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.049471 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 615781749 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 258431172 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 234656399 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 344883989 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 184537520 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 162320770 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 242844978 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 179433436 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 19957407 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 9898888 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 123887 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 73372 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 7123096 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 9906440 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 125316 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 73841 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 7125415 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 383831 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 383693 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 3808 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1026572 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 3903842 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 90265 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 434136051 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 99585 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 104653375 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 80643825 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 1026274 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 3908203 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 111577 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 434157595 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 99580 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 104660927 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 80646144 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 295 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 7679 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 82299 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 73372 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 826459 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 307772 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1134231 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 399253806 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 102504065 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3149200 # Number of squashed instructions skipped in execute +system.cpu.iew.iewIQFullEvents 8166 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 103056 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 73841 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 825839 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 307783 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1133622 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 399257785 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 102509229 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3146965 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 24922262 # number of nop insts executed -system.cpu.iew.exec_refs 181324750 # number of memory reference insts executed -system.cpu.iew.exec_branches 46546315 # Number of branches executed -system.cpu.iew.exec_stores 78820685 # Number of stores executed -system.cpu.iew.exec_rate 2.941124 # Inst execution rate -system.cpu.iew.wb_sent 397727618 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 396972079 # cumulative count of insts written-back -system.cpu.iew.wb_producers 196558282 # num instructions producing a value -system.cpu.iew.wb_consumers 281889088 # num instructions consuming a value +system.cpu.iew.exec_nop 24922591 # number of nop insts executed +system.cpu.iew.exec_refs 181329115 # number of memory reference insts executed +system.cpu.iew.exec_branches 46548281 # Number of branches executed +system.cpu.iew.exec_stores 78819886 # Number of stores executed +system.cpu.iew.exec_rate 2.940179 # Inst execution rate +system.cpu.iew.wb_sent 397733168 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 396977169 # cumulative count of insts written-back +system.cpu.iew.wb_producers 196565794 # num instructions producing a value +system.cpu.iew.wb_consumers 281908418 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.924316 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.697289 # average fanout of values written-back +system.cpu.iew.wb_rate 2.923385 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.697268 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 35472304 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 35494113 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 975365 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 130528765 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 3.054228 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 3.231390 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 974783 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 130571429 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 3.053230 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 3.231493 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 46472448 35.60% 35.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 17656165 13.53% 49.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 9417491 7.21% 56.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8632138 6.61% 62.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 6273043 4.81% 67.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 4304526 3.30% 71.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 4966466 3.80% 74.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 2588480 1.98% 76.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 30218008 23.15% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 46510589 35.62% 35.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 17663753 13.53% 49.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 9427402 7.22% 56.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8631802 6.61% 62.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 6252911 4.79% 67.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 4309640 3.30% 71.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 4961322 3.80% 74.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 2589236 1.98% 76.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 30224774 23.15% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 130528765 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 130571429 # Number of insts commited each cycle system.cpu.commit.committedInsts 398664583 # Number of instructions committed system.cpu.commit.committedOps 398664583 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -571,32 +571,32 @@ system.cpu.commit.op_class_0::MemWrite 73520729 18.44% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 398664583 # Class of committed instruction -system.cpu.commit.bw_lim_events 30218008 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 534444667 # The number of ROB reads -system.cpu.rob.rob_writes 873208037 # The number of ROB writes -system.cpu.timesIdled 3160 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 298887 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 30224774 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 534502374 # The number of ROB reads +system.cpu.rob.rob_writes 873254462 # The number of ROB writes +system.cpu.timesIdled 3162 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 298467 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 375574808 # Number of Instructions Simulated system.cpu.committedOps 375574808 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.361442 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.361442 # CPI: Total CPI of All Threads -system.cpu.ipc 2.766692 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.766692 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 399091287 # number of integer regfile reads -system.cpu.int_regfile_writes 169885620 # number of integer regfile writes -system.cpu.fp_regfile_reads 156870882 # number of floating regfile reads -system.cpu.fp_regfile_writes 104904950 # number of floating regfile writes +system.cpu.cpi 0.361562 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.361562 # CPI: Total CPI of All Threads +system.cpu.ipc 2.765775 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.765775 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 399095542 # number of integer regfile reads +system.cpu.int_regfile_writes 169885767 # number of integer regfile writes +system.cpu.fp_regfile_reads 156866113 # number of floating regfile reads +system.cpu.fp_regfile_writes 104908933 # number of floating regfile writes system.cpu.misc_regfile_reads 350572 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.dcache.tags.replacements 777 # number of replacements -system.cpu.dcache.tags.tagsinuse 3293.050932 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 155556653 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 3293.060025 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 155551655 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4177 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37241.238449 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37240.041896 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3293.050932 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.803968 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.803968 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 3293.060025 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.803970 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.803970 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3400 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id @@ -604,44 +604,44 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 212 system.cpu.dcache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 3114 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.830078 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 311160441 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 311160441 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 82055589 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 82055589 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73501058 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73501058 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 311150441 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 311150441 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 82050592 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 82050592 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 73501057 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73501057 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 6 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 6 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 155556647 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 155556647 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 155556647 # number of overall hits -system.cpu.dcache.overall_hits::total 155556647 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1808 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1808 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 19671 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 19671 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 21479 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 21479 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 21479 # number of overall misses -system.cpu.dcache.overall_misses::total 21479 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 128709000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 128709000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1198982453 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1198982453 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1327691453 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1327691453 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1327691453 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1327691453 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 82057397 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 82057397 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 155551649 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 155551649 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 155551649 # number of overall hits +system.cpu.dcache.overall_hits::total 155551649 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1805 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1805 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 19672 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 19672 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 21477 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 21477 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 21477 # number of overall misses +system.cpu.dcache.overall_misses::total 21477 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 128536500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 128536500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1197114453 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1197114453 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 1325650953 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1325650953 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1325650953 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1325650953 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 82052397 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 82052397 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 73520729 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 6 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 6 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 155578126 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 155578126 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 155578126 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 155578126 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 155573126 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 155573126 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 155573126 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 155573126 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000022 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000268 # miss rate for WriteReq accesses @@ -650,32 +650,32 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000138 system.cpu.dcache.demand_miss_rate::total 0.000138 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000138 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000138 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71188.606195 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 71188.606195 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60951.779421 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 60951.779421 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 61813.466782 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 61813.466782 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 61813.466782 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 61813.466782 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 49798 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71211.357341 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 71211.357341 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60853.723719 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 60853.723719 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 61724.214415 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 61724.214415 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 61724.214415 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 61724.214415 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 49394 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 86 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 748 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 66.574866 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 66.034759 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 86 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 656 # number of writebacks system.cpu.dcache.writebacks::total 656 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 820 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 820 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16482 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16482 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 17302 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 17302 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 17302 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 17302 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 817 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 817 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16483 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16483 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 17300 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 17300 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 17300 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 17300 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 988 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 988 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3189 # number of WriteReq MSHR misses @@ -684,14 +684,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4177 system.cpu.dcache.demand_mshr_misses::total 4177 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4177 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4177 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75199500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 75199500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 250368000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 250368000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 325567500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 325567500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 325567500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 325567500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 74845500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 74845500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 249448500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 249448500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 324294000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 324294000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 324294000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 324294000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000012 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000012 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for WriteReq accesses @@ -700,130 +700,134 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76112.854251 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76112.854251 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78509.877705 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78509.877705 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77942.901604 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 77942.901604 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77942.901604 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 77942.901604 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75754.554656 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75754.554656 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78221.542803 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78221.542803 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77638.017716 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 77638.017716 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77638.017716 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 77638.017716 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 2126 # number of replacements -system.cpu.icache.tags.tagsinuse 1833.088267 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 49836296 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1833.091155 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 49837345 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 4054 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 12293.116922 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 12293.375678 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1833.088267 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.895063 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.895063 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1833.091155 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.895064 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.895064 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1928 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 167 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 287 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1353 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.941406 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 99687840 # Number of tag accesses -system.cpu.icache.tags.data_accesses 99687840 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 49836296 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 49836296 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 49836296 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 49836296 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 49836296 # number of overall hits -system.cpu.icache.overall_hits::total 49836296 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5597 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5597 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5597 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5597 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5597 # number of overall misses -system.cpu.icache.overall_misses::total 5597 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 364082499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 364082499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 364082499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 364082499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 364082499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 364082499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 49841893 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 49841893 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 49841893 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 49841893 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 49841893 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 49841893 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 99689952 # Number of tag accesses +system.cpu.icache.tags.data_accesses 99689952 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 49837345 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 49837345 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 49837345 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 49837345 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 49837345 # number of overall hits +system.cpu.icache.overall_hits::total 49837345 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5604 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5604 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5604 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5604 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5604 # number of overall misses +system.cpu.icache.overall_misses::total 5604 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 365347499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 365347499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 365347499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 365347499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 365347499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 365347499 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 49842949 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 49842949 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 49842949 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 49842949 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 49842949 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 49842949 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000112 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000112 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000112 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000112 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000112 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000112 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 65049.579954 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 65049.579954 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 65049.579954 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 65049.579954 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 65049.579954 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 65049.579954 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 650 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 65194.057637 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 65194.057637 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 65194.057637 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 65194.057637 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 65194.057637 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 65194.057637 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 644 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 7 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 92.857143 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 92 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1543 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1543 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1543 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1543 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1543 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1543 # number of overall MSHR hits +system.cpu.icache.writebacks::writebacks 2126 # number of writebacks +system.cpu.icache.writebacks::total 2126 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1550 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1550 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1550 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1550 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1550 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1550 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4054 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 4054 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 4054 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 4054 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 4054 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 4054 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 273657000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 273657000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 273657000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 273657000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 273657000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 273657000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 273942500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 273942500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 273942500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 273942500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 273942500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 273942500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000081 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000081 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000081 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000081 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000081 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000081 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67502.960039 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67502.960039 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67502.960039 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 67502.960039 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67502.960039 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 67502.960039 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67573.384312 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67573.384312 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67573.384312 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 67573.384312 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67573.384312 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 67573.384312 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 4002.026272 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 4002.038570 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3073 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 4841 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.634786 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 371.009955 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2970.733849 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 660.282469 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 371.011804 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2970.742908 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 660.283858 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.011322 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.090660 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.020150 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.122132 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.122133 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 4841 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 146 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 137 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 147 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 136 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 528 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4030 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.147736 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 97102 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 97102 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 656 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 656 # number of Writeback hits +system.cpu.l2cache.WritebackDirty_hits::writebacks 656 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 656 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 2126 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 2126 # number of WritebackClean hits system.cpu.l2cache.ReadExReq_hits::cpu.data 60 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 60 # number of ReadExReq hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 608 # number of ReadCleanReq hits @@ -848,20 +852,22 @@ system.cpu.l2cache.demand_misses::total 7435 # nu system.cpu.l2cache.overall_misses::cpu.inst 3446 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 3989 # number of overall misses system.cpu.l2cache.overall_misses::total 7435 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 244858000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 244858000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 261180500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 261180500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 72283000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 72283000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 261180500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 317141000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 578321500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 261180500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 317141000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 578321500 # number of overall miss cycles -system.cpu.l2cache.Writeback_accesses::writebacks 656 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 656 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 243935500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 243935500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 261376000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 261376000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 71927500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 71927500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 261376000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 315863000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 577239000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 261376000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 315863000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 577239000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 656 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 656 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 2126 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 2126 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 3189 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 3189 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 4054 # number of ReadCleanReq accesses(hits+misses) @@ -886,18 +892,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.903292 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.850025 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.954992 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.903292 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78254.394375 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78254.394375 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75792.367963 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75792.367963 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 84050 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 84050 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75792.367963 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79503.885686 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 77783.658373 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75792.367963 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79503.885686 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 77783.658373 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77959.571748 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77959.571748 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75849.100406 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75849.100406 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83636.627907 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83636.627907 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75849.100406 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79183.504638 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 77638.063215 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75849.100406 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79183.504638 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 77638.063215 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -918,18 +924,18 @@ system.cpu.l2cache.demand_mshr_misses::total 7435 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3446 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 3989 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7435 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 213568000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 213568000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 226720500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 226720500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 63683000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 63683000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 226720500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 277251000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 503971500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 226720500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 277251000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 503971500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 212645500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 212645500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 226916000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 226916000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 63327500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 63327500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 226916000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 275973000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 502889000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 226916000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 275973000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 502889000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.981185 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.981185 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.850025 # mshr miss rate for ReadCleanReq accesses @@ -942,18 +948,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.903292 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.850025 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.954992 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.903292 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68254.394375 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68254.394375 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65792.367963 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65792.367963 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74050 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74050 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65792.367963 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69503.885686 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67783.658373 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65792.367963 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69503.885686 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67783.658373 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67959.571748 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67959.571748 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65849.100406 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65849.100406 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73636.627907 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73636.627907 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65849.100406 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69183.504638 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67638.063215 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65849.100406 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69183.504638 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67638.063215 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 11134 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 2903 # Number of requests hitting in the snoop filter with a single holder of the requested data. @@ -962,8 +968,9 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 5042 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 656 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 2247 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 656 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 2126 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 121 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 3189 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 3189 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 4054 # Transaction distribution @@ -971,22 +978,22 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 988 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10234 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9131 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 19365 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 259456 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 395520 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 309312 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 568768 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 704832 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 11134 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 8231 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 11134 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 8231 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 11134 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 6223000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 8231 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 8349000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 6081000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) @@ -1011,9 +1018,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 7435 # Request fanout histogram -system.membus.reqLayer0.occupancy 9180000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 9238500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 39204250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 39203500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt index b9717df42..8253a646b 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.567335 # Number of seconds simulated -sim_ticks 567335097500 # Number of ticks simulated -final_tick 567335097500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.567385 # Number of seconds simulated +sim_ticks 567385356500 # Number of ticks simulated +final_tick 567385356500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1348015 # Simulator instruction rate (inst/s) -host_op_rate 1348015 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1918345002 # Simulator tick rate (ticks/s) -host_mem_usage 301916 # Number of bytes of host memory used -host_seconds 295.74 # Real time elapsed on the host +host_inst_rate 1390819 # Simulator instruction rate (inst/s) +host_op_rate 1390819 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1979434182 # Simulator tick rate (ticks/s) +host_mem_usage 302276 # Number of bytes of host memory used +host_seconds 286.64 # Real time elapsed on the host sim_insts 398664609 # Number of instructions simulated sim_ops 398664609 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 205120 # Nu system.physmem.num_reads::cpu.inst 3205 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 3969 # Number of read requests responded to by this memory system.physmem.num_reads::total 7174 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 361550 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 447735 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 809285 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 361550 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 361550 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 361550 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 447735 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 809285 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 361518 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 447696 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 809214 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 361518 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 361518 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 361518 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 447696 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 809214 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -63,7 +63,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 1134670195 # number of cpu cycles simulated +system.cpu.numCycles 1134770713 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 398664609 # Number of instructions committed @@ -82,7 +82,7 @@ system.cpu.num_mem_refs 168275276 # nu system.cpu.num_load_insts 94754511 # Number of load instructions system.cpu.num_store_insts 73520765 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 1134670195 # Number of busy cycles +system.cpu.num_busy_cycles 1134770713 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 44587535 # Number of branches fetched @@ -122,14 +122,14 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 398664665 # Class of executed instruction system.cpu.dcache.tags.replacements 764 # number of replacements -system.cpu.dcache.tags.tagsinuse 3288.930558 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 3288.807028 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 168271068 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4152 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 40527.713873 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3288.930558 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.802962 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.802962 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 3288.807028 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.802931 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.802931 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3388 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 39 # Occupied blocks per task id @@ -155,14 +155,14 @@ system.cpu.dcache.demand_misses::cpu.data 4152 # n system.cpu.dcache.demand_misses::total 4152 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 4152 # number of overall misses system.cpu.dcache.overall_misses::total 4152 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 47084000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 47084000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 173590000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 173590000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 220674000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 220674000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 220674000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 220674000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 52888500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 52888500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 195593000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 195593000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 248481500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 248481500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 248481500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 248481500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 94754490 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 94754490 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520730 # number of WriteReq accesses(hits+misses) @@ -179,14 +179,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49562.105263 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 49562.105263 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54212.991880 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 54212.991880 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 53148.843931 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 53148.843931 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 53148.843931 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 53148.843931 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55672.105263 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 55672.105263 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61084.634603 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 61084.634603 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 59846.218690 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 59846.218690 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 59846.218690 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 59846.218690 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -205,14 +205,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4152 system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 46134000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 46134000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 170388000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 170388000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 216522000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 216522000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 216522000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 216522000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 51938500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 51938500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 192391000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 192391000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 244329500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 244329500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 244329500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 244329500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses @@ -221,28 +221,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48562.105263 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48562.105263 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53212.991880 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53212.991880 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52148.843931 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 52148.843931 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52148.843931 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 52148.843931 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54672.105263 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54672.105263 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60084.634603 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60084.634603 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58846.218690 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 58846.218690 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58846.218690 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 58846.218690 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1769 # number of replacements -system.cpu.icache.tags.tagsinuse 1795.138955 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1795.084430 # Cycle average of tags in use system.cpu.icache.tags.total_refs 398660993 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 3673 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 108538.250204 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1795.138955 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.876533 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.876533 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1795.084430 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.876506 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.876506 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1904 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 142 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 85 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 138 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 90 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 251 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1375 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.929688 # Percentage of cache occupancy per task id @@ -260,12 +260,12 @@ system.cpu.icache.demand_misses::cpu.inst 3673 # n system.cpu.icache.demand_misses::total 3673 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 3673 # number of overall misses system.cpu.icache.overall_misses::total 3673 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 182363500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 182363500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 182363500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 182363500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 182363500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 182363500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 204815000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 204815000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 204815000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 204815000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 204815000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 204815000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 398664666 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 398664666 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 398664666 # number of demand (read+write) accesses @@ -278,12 +278,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000009 system.cpu.icache.demand_miss_rate::total 0.000009 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000009 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000009 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49649.741356 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 49649.741356 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 49649.741356 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 49649.741356 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 49649.741356 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 49649.741356 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55762.319630 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 55762.319630 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 55762.319630 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 55762.319630 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 55762.319630 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 55762.319630 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -292,55 +292,59 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks::writebacks 1769 # number of writebacks +system.cpu.icache.writebacks::total 1769 # number of writebacks system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3673 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 3673 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 3673 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 3673 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 3673 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 3673 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 178690500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 178690500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 178690500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 178690500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 178690500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 178690500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 201142000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 201142000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 201142000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 201142000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 201142000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 201142000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000009 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000009 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48649.741356 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48649.741356 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48649.741356 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 48649.741356 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48649.741356 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 48649.741356 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54762.319630 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54762.319630 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54762.319630 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 54762.319630 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54762.319630 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 54762.319630 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 3772.485272 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 3772.330397 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2561 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 4566 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.560885 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 371.540218 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2770.469899 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 630.475155 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.011339 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.084548 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.019241 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.115127 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 371.516873 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2770.363420 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 630.450105 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.011338 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.084545 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.019240 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.115122 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 4566 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 135 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 75 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 134 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 77 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 497 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3787 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.139343 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 90632 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 90632 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 649 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 649 # number of Writeback hits +system.cpu.l2cache.WritebackDirty_hits::writebacks 649 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 649 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 1769 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 1769 # number of WritebackClean hits system.cpu.l2cache.ReadExReq_hits::cpu.data 60 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 60 # number of ReadExReq hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 468 # number of ReadCleanReq hits @@ -365,20 +369,22 @@ system.cpu.l2cache.demand_misses::total 7174 # nu system.cpu.l2cache.overall_misses::cpu.inst 3205 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 3969 # number of overall misses system.cpu.l2cache.overall_misses::total 7174 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 164955000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 164955000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 168265000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 168265000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 43417500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 43417500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 168265000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 208372500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 376637500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 168265000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 208372500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 376637500 # number of overall miss cycles -system.cpu.l2cache.Writeback_accesses::writebacks 649 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 649 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 186953000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 186953000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 190709000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 190709000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 49213500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 49213500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 190709000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 236166500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 426875500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 190709000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 236166500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 426875500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 649 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 649 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 1769 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 1769 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 3202 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 3202 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 3673 # number of ReadCleanReq accesses(hits+misses) @@ -403,18 +409,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.916805 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.872584 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.955925 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.916805 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52500.780031 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52500.780031 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52500.780031 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52500.348481 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52500.780031 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52500.348481 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59501.273074 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59501.273074 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59503.588144 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59503.588144 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59508.464329 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59508.464329 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59503.588144 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59502.771479 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 59503.136326 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59503.588144 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59502.771479 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 59503.136326 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -435,18 +441,18 @@ system.cpu.l2cache.demand_mshr_misses::total 7174 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3205 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 3969 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7174 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 133535000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 133535000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 136215000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 136215000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 35147500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 35147500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 136215000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 168682500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 304897500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 136215000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 168682500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 304897500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 155533000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 155533000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 158659000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 158659000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 40943500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 40943500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 158659000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 196476500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 355135500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 158659000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 196476500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 355135500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.981262 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.981262 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for ReadCleanReq accesses @@ -459,18 +465,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.916805 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.916805 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42500.780031 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42500.780031 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42500.780031 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42500.348481 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42500.780031 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42500.348481 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49501.273074 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49501.273074 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49503.588144 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49503.588144 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49508.464329 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49508.464329 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49503.588144 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49502.771479 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49503.136326 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49503.588144 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49502.771479 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49503.136326 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 10358 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 2533 # Number of requests hitting in the snoop filter with a single holder of the requested data. @@ -479,8 +485,9 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 4623 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 649 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 1884 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 649 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1769 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 115 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 3202 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 3202 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 3673 # Transaction distribution @@ -488,22 +495,22 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 950 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9115 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9068 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 18183 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 235072 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 348288 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 307264 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 542336 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 655552 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 10358 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 7825 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 10358 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 7825 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 10358 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5828000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 7825 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 7597000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 5509500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) @@ -528,9 +535,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 7174 # Request fanout histogram -system.membus.reqLayer0.occupancy 7176500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 7196500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 35872500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 35870000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |