diff options
Diffstat (limited to 'tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt')
| -rw-r--r-- | tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt | 708 |
1 files changed, 353 insertions, 355 deletions
diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt index dd174365b..32197bf04 100644 --- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt @@ -1,42 +1,42 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.216828 # Number of seconds simulated -sim_ticks 216828260500 # Number of ticks simulated -final_tick 216828260500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.216865 # Number of seconds simulated +sim_ticks 216864820000 # Number of ticks simulated +final_tick 216864820000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 113548 # Simulator instruction rate (inst/s) -host_op_rate 136327 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 90171945 # Simulator tick rate (ticks/s) -host_mem_usage 309844 # Number of bytes of host memory used -host_seconds 2404.61 # Real time elapsed on the host +host_inst_rate 175540 # Simulator instruction rate (inst/s) +host_op_rate 210755 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 139425507 # Simulator tick rate (ticks/s) +host_mem_usage 321524 # Number of bytes of host memory used +host_seconds 1555.42 # Real time elapsed on the host sim_insts 273037856 # Number of instructions simulated sim_ops 327812213 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 219072 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 219008 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 266368 # Number of bytes read from this memory -system.physmem.bytes_read::total 485440 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 219072 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 219072 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3423 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 485376 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 219008 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 219008 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3422 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 4162 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7585 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1010348 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1228475 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2238823 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1010348 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1010348 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1010348 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1228475 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2238823 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7585 # Number of read requests accepted +system.physmem.num_reads::total 7584 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1009883 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1228267 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2238150 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1009883 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1009883 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1009883 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1228267 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2238150 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7584 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 7585 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 7584 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 485440 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 485376 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 485440 # Total read bytes from the system interface side +system.physmem.bytesReadSys 485376 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -53,7 +53,7 @@ system.physmem.perBankRdBursts::8 209 # Pe system.physmem.perBankRdBursts::9 311 # Per bank write bursts system.physmem.perBankRdBursts::10 342 # Per bank write bursts system.physmem.perBankRdBursts::11 428 # Per bank write bursts -system.physmem.perBankRdBursts::12 554 # Per bank write bursts +system.physmem.perBankRdBursts::12 553 # Per bank write bursts system.physmem.perBankRdBursts::13 706 # Per bank write bursts system.physmem.perBankRdBursts::14 637 # Per bank write bursts system.physmem.perBankRdBursts::15 541 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 216828031000 # Total gap between requests +system.physmem.totGap 216864583500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 7585 # Read request sizes (log2) +system.physmem.readPktSize::6 7584 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,9 +90,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 6628 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 896 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 61 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 6626 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 898 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 60 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1505 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 321.360797 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 189.304771 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 333.736324 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 549 36.48% 36.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 346 22.99% 59.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 165 10.96% 70.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 68 4.52% 74.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 70 4.65% 79.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 58 3.85% 83.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 34 2.26% 85.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 33 2.19% 87.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 182 12.09% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1505 # Bytes accessed per row activation -system.physmem.totQLat 50845500 # Total ticks spent queuing -system.physmem.totMemAccLat 193064250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 37925000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6703.43 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1523 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 317.772817 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 188.476979 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 330.358112 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 549 36.05% 36.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 352 23.11% 59.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 179 11.75% 70.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 73 4.79% 75.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 70 4.60% 80.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 53 3.48% 83.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 37 2.43% 86.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 29 1.90% 88.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 181 11.88% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1523 # Bytes accessed per row activation +system.physmem.totQLat 53728750 # Total ticks spent queuing +system.physmem.totMemAccLat 195928750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 37920000 # Total ticks spent in databus transfers +system.physmem.avgQLat 7084.49 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25453.43 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25834.49 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.24 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.24 # Average system read bandwidth in MiByte/s @@ -216,48 +216,48 @@ system.physmem.busUtilRead 0.02 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 6073 # Number of row buffer hits during reads +system.physmem.readRowHits 6056 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.07 # Row buffer hit rate for reads +system.physmem.readRowHitRate 79.85 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 28586424.65 # Average gap between requests -system.physmem.pageHitRate 80.07 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 5012280 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2734875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 29905200 # Energy for read commands per rank (pJ) +system.physmem.avgGap 28595013.65 # Average gap between requests +system.physmem.pageHitRate 79.85 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 5027400 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2743125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 29952000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 14161870320 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 5652564030 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 125135988750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 144988075455 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.690273 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 208174326250 # Time in different power states -system.physmem_0.memoryStateTime::REF 7240220000 # Time in different power states +system.physmem_0.refreshEnergy 14164413120 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 5668320825 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 125145525750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 145015982220 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.698913 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 208188918000 # Time in different power states +system.physmem_0.memoryStateTime::REF 7241520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1410814750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1432738500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 6342840 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3460875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 29000400 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 6486480 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3539250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 29031600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 14161870320 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 5745534165 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 125054436000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 145000644600 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.748242 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 208036674250 # Time in different power states -system.physmem_1.memoryStateTime::REF 7240220000 # Time in different power states +system.physmem_1.refreshEnergy 14164413120 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 5831746380 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 125002170000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 145037386830 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.797614 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 207947266000 # Time in different power states +system.physmem_1.memoryStateTime::REF 7241520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1549163250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1674122750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 33221230 # Number of BP lookups -system.cpu.branchPred.condPredicted 17174007 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1583983 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 17995686 # Number of BTB lookups -system.cpu.branchPred.BTBHits 15666979 # Number of BTB hits +system.cpu.branchPred.lookups 33219592 # Number of BP lookups +system.cpu.branchPred.condPredicted 17177082 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1581285 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 17974979 # Number of BTB lookups +system.cpu.branchPred.BTBHits 15661112 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 87.059638 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 6611215 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 87.127290 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 6612085 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -377,75 +377,75 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 433656521 # number of cpu cycles simulated +system.cpu.numCycles 433729640 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 273037856 # Number of instructions committed system.cpu.committedOps 327812213 # Number of ops (including micro ops) committed -system.cpu.discardedOps 4064410 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 4054235 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.588265 # CPI: cycles per instruction -system.cpu.ipc 0.629618 # IPC: instructions per cycle -system.cpu.tickCycles 430211127 # Number of cycles that the object actually ticked -system.cpu.idleCycles 3445394 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.588533 # CPI: cycles per instruction +system.cpu.ipc 0.629512 # IPC: instructions per cycle +system.cpu.tickCycles 430193160 # Number of cycles that the object actually ticked +system.cpu.idleCycles 3536480 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 1354 # number of replacements -system.cpu.dcache.tags.tagsinuse 3086.009488 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 168783807 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 3085.768991 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168782225 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4511 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37416.051208 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37415.700510 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3086.009488 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.753420 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.753420 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 3085.768991 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.753362 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.753362 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3157 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 672 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 2432 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.770752 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 337586705 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 337586705 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 86714567 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 86714567 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 82047450 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 82047450 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 337583521 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 337583521 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 86712977 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 86712977 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 82047458 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 82047458 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 168762017 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168762017 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168762017 # number of overall hits -system.cpu.dcache.overall_hits::total 168762017 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2063 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2063 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5227 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5227 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 7290 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 7290 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 7290 # number of overall misses -system.cpu.dcache.overall_misses::total 7290 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 126489706 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 126489706 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 360451750 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 360451750 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 486941456 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 486941456 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 486941456 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 486941456 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 86716630 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 86716630 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 168760435 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168760435 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168760435 # number of overall hits +system.cpu.dcache.overall_hits::total 168760435 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2061 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2061 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5219 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5219 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 7280 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 7280 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 7280 # number of overall misses +system.cpu.dcache.overall_misses::total 7280 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 137684956 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 137684956 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 400150250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 400150250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 537835206 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 537835206 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 537835206 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 537835206 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 86715038 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 86715038 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 168769307 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 168769307 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 168769307 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 168769307 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 168767715 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 168767715 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 168767715 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 168767715 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000024 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000024 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000064 # miss rate for WriteReq accesses @@ -454,14 +454,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000043 system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000043 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61313.478429 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 61313.478429 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 68959.584848 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 68959.584848 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 66795.810151 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 66795.810151 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 66795.810151 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 66795.810151 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66804.927705 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 66804.927705 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76671.824104 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 76671.824104 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 73878.462363 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 73878.462363 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 73878.462363 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 73878.462363 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -472,14 +472,14 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 1010 # number of writebacks system.cpu.dcache.writebacks::total 1010 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 422 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 422 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2357 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2357 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2779 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2779 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2779 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2779 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 420 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 420 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2349 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2349 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2769 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2769 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2769 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2769 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1641 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 1641 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2870 # number of WriteReq MSHR misses @@ -488,14 +488,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4511 system.cpu.dcache.demand_mshr_misses::total 4511 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4511 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4511 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 100259792 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 100259792 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 197855250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 197855250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 298115042 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 298115042 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 298115042 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 298115042 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 109745542 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 109745542 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 219964750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 219964750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 329710292 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 329710292 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 329710292 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 329710292 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses @@ -504,69 +504,69 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61096.765387 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61096.765387 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 68939.111498 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68939.111498 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66086.242962 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 66086.242962 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66086.242962 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 66086.242962 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66877.234613 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66877.234613 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76642.770035 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76642.770035 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73090.288628 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 73090.288628 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73090.288628 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 73090.288628 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 36927 # number of replacements -system.cpu.icache.tags.tagsinuse 1924.993634 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 73270394 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 38864 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1885.302439 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 36897 # number of replacements +system.cpu.icache.tags.tagsinuse 1924.852609 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 73252005 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 38834 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1886.285343 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1924.993634 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.939938 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.939938 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1924.852609 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.939869 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.939869 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1937 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 84 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 88 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 34 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 275 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1487 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.945801 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 146657382 # Number of tag accesses -system.cpu.icache.tags.data_accesses 146657382 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 73270394 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 73270394 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 73270394 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 73270394 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 73270394 # number of overall hits -system.cpu.icache.overall_hits::total 73270394 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 38865 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 38865 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 38865 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 38865 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 38865 # number of overall misses -system.cpu.icache.overall_misses::total 38865 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 703218247 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 703218247 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 703218247 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 703218247 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 703218247 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 703218247 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 73309259 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 73309259 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 73309259 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 73309259 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 73309259 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 73309259 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 146620514 # Number of tag accesses +system.cpu.icache.tags.data_accesses 146620514 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 73252005 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 73252005 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 73252005 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 73252005 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 73252005 # number of overall hits +system.cpu.icache.overall_hits::total 73252005 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 38835 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 38835 # 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number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 73290840 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 73290840 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 73290840 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 73290840 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000530 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000530 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000530 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000530 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000530 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000530 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18093.869729 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 18093.869729 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 18093.869729 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 18093.869729 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 18093.869729 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 18093.869729 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18757.737814 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 18757.737814 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 18757.737814 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 18757.737814 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 18757.737814 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 18757.737814 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 266925500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 482055750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 215130250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 266925500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 482055750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.088116 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.797075 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.116798 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.116859 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994425 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994425 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.088074 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.088116 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.922634 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.174866 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.088074 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.174964 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.088116 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922634 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.174866 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54762.562080 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58889.143731 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55903.455929 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55650.227751 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55650.227751 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54762.562080 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56668.128304 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55808.174028 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54762.562080 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56668.128304 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55808.174028 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.174964 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62866.817650 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65544.533639 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63607.293869 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63487.473721 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63487.473721 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62866.817650 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64133.950024 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63562.203323 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62866.817650 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64133.950024 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63562.203323 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 40506 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 40505 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 40476 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 40475 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 1010 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 2870 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 2870 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 77729 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 77669 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10032 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 87761 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2487296 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 87701 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2485376 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 353344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2840640 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2838720 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 44386 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 44356 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 44386 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 44356 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 44386 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 23203000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 44356 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 23188000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 58996747 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 58975248 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 7500458 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 7577708 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.trans_dist::ReadReq 4731 # Transaction distribution -system.membus.trans_dist::ReadResp 4731 # Transaction distribution +system.membus.trans_dist::ReadReq 4730 # Transaction distribution +system.membus.trans_dist::ReadResp 4730 # Transaction distribution system.membus.trans_dist::ReadExReq 2854 # Transaction distribution system.membus.trans_dist::ReadExResp 2854 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15170 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 15170 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485440 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 485440 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15168 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 15168 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485376 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 485376 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 7585 # Request fanout histogram +system.membus.snoop_fanout::samples 7584 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 7585 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 7584 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 7585 # Request fanout histogram -system.membus.reqLayer0.occupancy 8964000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 7584 # Request fanout histogram +system.membus.reqLayer0.occupancy 8969500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 71030500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 40264250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |