diff options
Diffstat (limited to 'tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt')
| -rw-r--r-- | tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt | 861 |
1 files changed, 450 insertions, 411 deletions
diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt index 84e6b72bf..078507389 100644 --- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt @@ -1,62 +1,62 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.215512 # Number of seconds simulated -sim_ticks 215512229500 # Number of ticks simulated -final_tick 215512229500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.211715 # Number of seconds simulated +sim_ticks 211714953000 # Number of ticks simulated +final_tick 211714953000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 167901 # Simulator instruction rate (inst/s) -host_op_rate 201584 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 132526721 # Simulator tick rate (ticks/s) -host_mem_usage 327404 # Number of bytes of host memory used -host_seconds 1626.18 # Real time elapsed on the host +host_inst_rate 192926 # Simulator instruction rate (inst/s) +host_op_rate 231629 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 149595583 # Simulator tick rate (ticks/s) +host_mem_usage 280180 # Number of bytes of host memory used +host_seconds 1415.25 # Real time elapsed on the host sim_insts 273037857 # Number of instructions simulated sim_ops 327812214 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 218880 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 266368 # Number of bytes read from this memory -system.physmem.bytes_read::total 485248 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 218880 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 218880 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3420 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 4162 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7582 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1015627 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1235976 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2251603 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1015627 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1015627 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1015627 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1235976 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2251603 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7582 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 219072 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 266432 # Number of bytes read from this memory +system.physmem.bytes_read::total 485504 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 219072 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 219072 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3423 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 4163 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7586 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1034750 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1258447 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2293197 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1034750 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1034750 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1034750 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1258447 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2293197 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7586 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 7582 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 7586 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 485248 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 485504 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 485248 # Total read bytes from the system interface side +system.physmem.bytesReadSys 485504 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 630 # Per bank write bursts -system.physmem.perBankRdBursts::1 844 # Per bank write bursts +system.physmem.perBankRdBursts::1 846 # Per bank write bursts system.physmem.perBankRdBursts::2 628 # Per bank write bursts system.physmem.perBankRdBursts::3 541 # Per bank write bursts system.physmem.perBankRdBursts::4 466 # Per bank write bursts system.physmem.perBankRdBursts::5 349 # Per bank write bursts system.physmem.perBankRdBursts::6 171 # Per bank write bursts system.physmem.perBankRdBursts::7 228 # Per bank write bursts -system.physmem.perBankRdBursts::8 209 # Per bank write bursts +system.physmem.perBankRdBursts::8 208 # Per bank write bursts system.physmem.perBankRdBursts::9 310 # Per bank write bursts -system.physmem.perBankRdBursts::10 342 # Per bank write bursts +system.physmem.perBankRdBursts::10 343 # Per bank write bursts system.physmem.perBankRdBursts::11 428 # Per bank write bursts system.physmem.perBankRdBursts::12 553 # Per bank write bursts system.physmem.perBankRdBursts::13 705 # Per bank write bursts system.physmem.perBankRdBursts::14 638 # Per bank write bursts -system.physmem.perBankRdBursts::15 540 # Per bank write bursts +system.physmem.perBankRdBursts::15 542 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 215511990500 # Total gap between requests +system.physmem.totGap 211714708500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 7582 # Read request sizes (log2) +system.physmem.readPktSize::6 7586 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,9 +90,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 6627 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 894 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 61 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 6629 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 897 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 60 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -186,29 +186,29 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1510 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 320.169536 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 189.396997 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 331.756940 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 550 36.42% 36.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 336 22.25% 58.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 179 11.85% 70.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 73 4.83% 75.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 74 4.90% 80.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 52 3.44% 83.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 33 2.19% 85.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 29 1.92% 87.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 184 12.19% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1510 # Bytes accessed per row activation -system.physmem.totQLat 54741000 # Total ticks spent queuing -system.physmem.totMemAccLat 196903500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 37910000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7219.86 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1530 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 316.067974 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 186.296863 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 330.878934 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 560 36.60% 36.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 363 23.73% 60.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 160 10.46% 70.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 74 4.84% 75.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 70 4.58% 80.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 59 3.86% 84.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 34 2.22% 86.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 28 1.83% 88.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 182 11.90% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1530 # Bytes accessed per row activation +system.physmem.totQLat 52630500 # Total ticks spent queuing +system.physmem.totMemAccLat 194868000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 37930000 # Total ticks spent in databus transfers +system.physmem.avgQLat 6937.85 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25969.86 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.25 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 25687.85 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.29 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.25 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.29 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage @@ -216,49 +216,53 @@ system.physmem.busUtilRead 0.02 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 6065 # Number of row buffer hits during reads +system.physmem.readRowHits 6048 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.99 # Row buffer hit rate for reads +system.physmem.readRowHitRate 79.73 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 28424161.24 # Average gap between requests -system.physmem.pageHitRate 79.99 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 5019840 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2739000 # Energy for precharge commands per rank (pJ) +system.physmem.avgGap 27908609.08 # Average gap between requests +system.physmem.pageHitRate 79.73 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 5080320 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2772000 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 29905200 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 14075923680 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 5641560180 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 124356115500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 144111263400 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.704665 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 206876360250 # Time in different power states -system.physmem_0.memoryStateTime::REF 7196280000 # Time in different power states +system.physmem_0.refreshEnergy 13827746400 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 5529396150 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 122174691000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 141569591070 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.700877 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 203247000500 # Time in different power states +system.physmem_0.memoryStateTime::REF 7069400000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1436474750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1392729000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 6373080 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3477375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 28977000 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 6463800 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3526875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 28992600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 14075923680 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 5809762620 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 124208569500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 144133083255 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.805913 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 206629350750 # Time in different power states -system.physmem_1.memoryStateTime::REF 7196280000 # Time in different power states +system.physmem_1.refreshEnergy 13827746400 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 5726317185 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 122001953250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 141595000110 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.820896 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 202960400000 # Time in different power states +system.physmem_1.memoryStateTime::REF 7069400000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1684213750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1682763000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 32816919 # Number of BP lookups -system.cpu.branchPred.condPredicted 16892731 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1463888 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 17497038 # Number of BTB lookups -system.cpu.branchPred.BTBHits 15468343 # Number of BTB hits +system.cpu.branchPred.lookups 32413931 # Number of BP lookups +system.cpu.branchPred.condPredicted 16919661 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 738142 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 17496692 # Number of BTB lookups +system.cpu.branchPred.BTBHits 12856502 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 88.405495 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 6575577 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 73.479615 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 6512761 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 3 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 2303892 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 2264485 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 39407 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 128263 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -377,81 +381,116 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 431024459 # number of cpu cycles simulated +system.cpu.numCycles 423429906 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 273037857 # Number of instructions committed system.cpu.committedOps 327812214 # Number of ops (including micro ops) committed -system.cpu.discardedOps 3889164 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 2127081 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.578625 # CPI: cycles per instruction -system.cpu.ipc 0.633463 # IPC: instructions per cycle -system.cpu.tickCycles 427416966 # Number of cycles that the object actually ticked -system.cpu.idleCycles 3607493 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 1354 # number of replacements -system.cpu.dcache.tags.tagsinuse 3085.807941 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 168714884 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 4511 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37400.772334 # Average number of references to valid blocks. +system.cpu.cpi 1.550810 # CPI: cycles per instruction +system.cpu.ipc 0.644824 # IPC: instructions per cycle +system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction +system.cpu.op_class_0::IntAlu 104312544 31.82% 31.82% # Class of committed instruction +system.cpu.op_class_0::IntMult 2145905 0.65% 32.48% # Class of committed instruction +system.cpu.op_class_0::IntDiv 0 0.00% 32.48% # Class of committed instruction +system.cpu.op_class_0::FloatAdd 0 0.00% 32.48% # Class of committed instruction +system.cpu.op_class_0::FloatCmp 0 0.00% 32.48% # Class of committed instruction +system.cpu.op_class_0::FloatCvt 0 0.00% 32.48% # Class of committed instruction +system.cpu.op_class_0::FloatMult 0 0.00% 32.48% # Class of committed instruction +system.cpu.op_class_0::FloatDiv 0 0.00% 32.48% # Class of committed instruction +system.cpu.op_class_0::FloatSqrt 0 0.00% 32.48% # Class of committed instruction +system.cpu.op_class_0::SimdAdd 0 0.00% 32.48% # Class of committed instruction +system.cpu.op_class_0::SimdAddAcc 0 0.00% 32.48% # Class of committed instruction +system.cpu.op_class_0::SimdAlu 0 0.00% 32.48% # Class of committed instruction +system.cpu.op_class_0::SimdCmp 0 0.00% 32.48% # Class of committed instruction +system.cpu.op_class_0::SimdCvt 0 0.00% 32.48% # Class of committed instruction +system.cpu.op_class_0::SimdMisc 0 0.00% 32.48% # Class of committed instruction +system.cpu.op_class_0::SimdMult 0 0.00% 32.48% # Class of committed instruction +system.cpu.op_class_0::SimdMultAcc 0 0.00% 32.48% # Class of committed instruction +system.cpu.op_class_0::SimdShift 0 0.00% 32.48% # Class of committed instruction +system.cpu.op_class_0::SimdShiftAcc 0 0.00% 32.48% # Class of committed instruction +system.cpu.op_class_0::SimdSqrt 0 0.00% 32.48% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAdd 6594343 2.01% 34.49% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAlu 0 0.00% 34.49% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCmp 7943502 2.42% 36.91% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCvt 3118180 0.95% 37.86% # Class of committed instruction +system.cpu.op_class_0::SimdFloatDiv 1563217 0.48% 38.34% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMisc 19652356 6.00% 44.33% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMult 7136937 2.18% 46.51% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of committed instruction +system.cpu.op_class_0::SimdFloatSqrt 175285 0.05% 48.72% # Class of committed instruction +system.cpu.op_class_0::MemRead 85732248 26.15% 74.87% # Class of committed instruction +system.cpu.op_class_0::MemWrite 82375599 25.13% 100.00% # Class of committed instruction +system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::total 327812214 # Class of committed instruction +system.cpu.tickCycles 420106568 # Number of cycles that the object actually ticked +system.cpu.idleCycles 3323338 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 1355 # number of replacements +system.cpu.dcache.tags.tagsinuse 3085.570959 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168654881 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 4512 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37379.184619 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3085.807941 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.753371 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.753371 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 3085.570959 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.753313 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.753313 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3157 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 672 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 2432 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 2431 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.770752 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 337448859 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 337448859 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 86582109 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 86582109 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 337328856 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 337328856 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 86522107 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 86522107 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 82047451 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 82047451 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 63534 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 63534 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 63533 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 63533 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 168629560 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168629560 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168693094 # number of overall hits -system.cpu.dcache.overall_hits::total 168693094 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2059 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2059 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 168569558 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168569558 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168633091 # number of overall hits +system.cpu.dcache.overall_hits::total 168633091 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2060 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2060 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 5226 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 5226 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 5 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 5 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 7285 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 7285 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 7290 # number of overall misses -system.cpu.dcache.overall_misses::total 7290 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 138607500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 138607500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 393622500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 393622500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 532230000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 532230000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 532230000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 532230000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 86584168 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 86584168 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 7286 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 7286 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 7291 # number of overall misses +system.cpu.dcache.overall_misses::total 7291 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 136635000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 136635000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 394688000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 394688000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 531323000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 531323000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 531323000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 531323000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 86524167 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 86524167 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 63539 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 63539 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 63538 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 63538 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 168636845 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 168636845 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 168700384 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 168700384 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 168576844 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 168576844 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 168640382 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 168640382 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000024 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000024 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000064 # miss rate for WriteReq accesses @@ -462,14 +501,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000043 system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000043 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67317.872754 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 67317.872754 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75320.034443 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 75320.034443 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 73058.339053 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 73058.339053 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 73008.230453 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 73008.230453 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66327.669903 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 66327.669903 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75523.918867 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 75523.918867 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 72923.826517 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 72923.826517 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 72873.817035 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 72873.817035 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -488,26 +527,26 @@ system.cpu.dcache.demand_mshr_hits::cpu.data 2777 system.cpu.dcache.demand_mshr_hits::total 2777 # number of demand (read+write) MSHR hits system.cpu.dcache.overall_mshr_hits::cpu.data 2777 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 2777 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1638 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1638 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1639 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1639 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2870 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 2870 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4508 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4508 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4511 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4511 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 111882000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 111882000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 219521500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 219521500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 238000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 238000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 331403500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 331403500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 331641500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 331641500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 4509 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4509 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4512 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4512 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 109916500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 109916500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 219842000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 219842000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 481000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 481000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 329758500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 329758500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 330239500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 330239500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses @@ -518,71 +557,71 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68304.029304 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68304.029304 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76488.327526 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76488.327526 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 79333.333333 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 79333.333333 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73514.529725 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 73514.529725 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73518.399468 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 73518.399468 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67063.148261 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67063.148261 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76600 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76600 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 160333.333333 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 160333.333333 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73133.399867 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 73133.399867 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73191.378546 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 73191.378546 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 36871 # number of replacements -system.cpu.icache.tags.tagsinuse 1923.837997 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 72548794 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 38807 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1869.477002 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 38168 # number of replacements +system.cpu.icache.tags.tagsinuse 1923.744161 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 69641436 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 40104 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1736.520946 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1923.837997 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.939374 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.939374 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1923.744161 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.939328 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.939328 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1936 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 86 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 34 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 84 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 33 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 276 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1485 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1483 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.945312 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 145214011 # Number of tag accesses -system.cpu.icache.tags.data_accesses 145214011 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 72548794 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 72548794 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 72548794 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 72548794 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 72548794 # number of overall hits -system.cpu.icache.overall_hits::total 72548794 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 38808 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 38808 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 38808 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 38808 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 38808 # number of overall misses -system.cpu.icache.overall_misses::total 38808 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 741346000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 741346000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 741346000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 741346000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 741346000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 741346000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 72587602 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 72587602 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 72587602 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 72587602 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 72587602 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 72587602 # 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average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 19102.916924 # average overall miss latency +system.cpu.icache.tags.tag_accesses 139403186 # Number of tag accesses +system.cpu.icache.tags.data_accesses 139403186 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 69641436 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 69641436 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 69641436 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 69641436 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 69641436 # number of overall hits +system.cpu.icache.overall_hits::total 69641436 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 40105 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 40105 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 40105 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 40105 # 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average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 18888.617379 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 18888.617379 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 18888.617379 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 18888.617379 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -591,135 +630,135 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 36871 # 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average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75337.245971 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75355.493863 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75355.493863 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78820.740741 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78820.740741 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75355.493863 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76455.875357 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 75962.103331 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75355.493863 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76455.875357 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 75962.103331 # average overall miss latency +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.085401 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.085401 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.822777 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.822777 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.085401 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.931959 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.171011 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.085401 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.931959 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.171011 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75450.070077 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75450.070077 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75095.912409 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75095.912409 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77486.676536 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77486.676536 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75095.912409 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76104.399524 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75651.703801 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75095.912409 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76104.399524 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75651.703801 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -740,113 +779,113 @@ system.cpu.l2cache.overall_mshr_hits::cpu.data 42 system.cpu.l2cache.overall_mshr_hits::total 44 # number of overall MSHR hits system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2854 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 2854 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3420 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3420 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1308 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1308 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3420 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 4162 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 7582 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3420 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 4162 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 7582 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 186472500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 186472500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 223532000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 223532000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 90324000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 90324000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 223532000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 276796500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 500328500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 223532000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 276796500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 500328500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3423 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3423 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1309 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1309 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3423 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 4163 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 7586 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3423 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 4163 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 7586 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 186794500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 186794500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 222839000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 222839000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 88850500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 88850500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 222839000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 275645000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 498484000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 222839000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 275645000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 498484000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994425 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994425 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.088126 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.088126 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.797075 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.797075 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.088126 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.922634 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.175027 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.088126 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922634 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.175027 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65337.245971 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65337.245971 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65360.233918 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65360.233918 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69055.045872 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69055.045872 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65360.233918 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66505.646324 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65988.987075 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65360.233918 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66505.646324 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65988.987075 # average overall mshr miss latency +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.085351 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.085351 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.797199 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.797199 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.085351 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.922651 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.170025 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.085351 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922651 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.170025 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65450.070077 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65450.070077 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65100.496640 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65100.496640 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67876.623377 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67876.623377 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65100.496640 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66213.067499 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65711.046665 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65100.496640 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66213.067499 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65711.046665 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 81544 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 38329 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 15017 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 84140 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 39625 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 15034 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 40448 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 41746 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 1010 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 36871 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 344 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 38168 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 345 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 2870 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 2870 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 38808 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1641 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 114486 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10376 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 124862 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4843392 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 353344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 5196736 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadCleanReq 40105 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1642 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 118377 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10379 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 128756 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5009408 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 353408 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 5362816 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 43319 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.349062 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.476679 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 44617 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.339243 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.473458 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 28198 65.09% 65.09% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 15121 34.91% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 29481 66.08% 66.08% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 15136 33.92% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 43319 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 78653000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 44617 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 81248000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 58211498 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 60156998 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 6787957 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 6789457 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.trans_dist::ReadResp 4728 # Transaction distribution +system.membus.trans_dist::ReadResp 4732 # Transaction distribution system.membus.trans_dist::ReadExReq 2854 # Transaction distribution system.membus.trans_dist::ReadExResp 2854 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 4728 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15164 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 15164 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485248 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 485248 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 4732 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15172 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 15172 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485504 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 485504 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 7582 # Request fanout histogram +system.membus.snoop_fanout::samples 7586 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 7582 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 7586 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 7582 # Request fanout histogram -system.membus.reqLayer0.occupancy 8861000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 7586 # Request fanout histogram +system.membus.reqLayer0.occupancy 8883500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 40239750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 40266000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |