diff options
Diffstat (limited to 'tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt')
| -rw-r--r-- | tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt | 426 |
1 files changed, 221 insertions, 205 deletions
diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt index 32197bf04..048a31a06 100644 --- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.216865 # Nu sim_ticks 216864820000 # Number of ticks simulated final_tick 216864820000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 175540 # Simulator instruction rate (inst/s) -host_op_rate 210755 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 139425507 # Simulator tick rate (ticks/s) -host_mem_usage 321524 # Number of bytes of host memory used -host_seconds 1555.42 # Real time elapsed on the host +host_inst_rate 114758 # Simulator instruction rate (inst/s) +host_op_rate 137779 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 91148248 # Simulator tick rate (ticks/s) +host_mem_usage 250616 # Number of bytes of host memory used +host_seconds 2379.25 # Real time elapsed on the host sim_insts 273037856 # Number of instructions simulated sim_ops 327812213 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -90,8 +90,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 6626 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 898 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 6625 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 899 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 60 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1523 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 317.772817 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 188.476979 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 330.358112 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 549 36.05% 36.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 352 23.11% 59.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 179 11.75% 70.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 73 4.79% 75.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 70 4.60% 80.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 53 3.48% 83.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 37 2.43% 86.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 29 1.90% 88.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 181 11.88% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1523 # Bytes accessed per row activation -system.physmem.totQLat 53728750 # Total ticks spent queuing -system.physmem.totMemAccLat 195928750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 1521 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 318.190664 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 188.796192 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 330.520878 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 546 35.90% 35.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 355 23.34% 59.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 175 11.51% 70.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 75 4.93% 75.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 71 4.67% 80.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 52 3.42% 83.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 37 2.43% 86.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 29 1.91% 88.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 181 11.90% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1521 # Bytes accessed per row activation +system.physmem.totQLat 53624000 # Total ticks spent queuing +system.physmem.totMemAccLat 195824000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 37920000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7084.49 # Average queueing delay per DRAM burst +system.physmem.avgQLat 7070.68 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25834.49 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25820.68 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.24 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.24 # Average system read bandwidth in MiByte/s @@ -216,48 +216,48 @@ system.physmem.busUtilRead 0.02 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 6056 # Number of row buffer hits during reads +system.physmem.readRowHits 6058 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.85 # Row buffer hit rate for reads +system.physmem.readRowHitRate 79.88 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 28595013.65 # Average gap between requests -system.physmem.pageHitRate 79.85 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 5027400 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2743125 # Energy for precharge commands per rank (pJ) +system.physmem.pageHitRate 79.88 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 5012280 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2734875 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 29952000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 14164413120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 5668320825 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 125145525750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 145015982220 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.698913 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 208188918000 # Time in different power states +system.physmem_0.actBackEnergy 5663385765 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 125149854750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 145015352790 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.696011 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 208196147750 # Time in different power states system.physmem_0.memoryStateTime::REF 7241520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1432738500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1425508750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 6486480 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 3539250 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 29031600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 14164413120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 5831746380 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 125002170000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 145037386830 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.797614 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 207947266000 # Time in different power states +system.physmem_1.actBackEnergy 5827279860 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 125006088000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 145036838310 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.795085 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 207953796500 # Time in different power states system.physmem_1.memoryStateTime::REF 7241520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1674122750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1667592250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 33219592 # Number of BP lookups +system.cpu.branchPred.lookups 33219593 # Number of BP lookups system.cpu.branchPred.condPredicted 17177082 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 1581285 # Number of conditional branches incorrect system.cpu.branchPred.BTBLookups 17974979 # Number of BTB lookups system.cpu.branchPred.BTBHits 15661112 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 87.127290 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 6612085 # Number of times the RAS was used to get a target. +system.cpu.branchPred.usedRAS 6612086 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -382,19 +382,19 @@ system.cpu.numWorkItemsStarted 0 # nu system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 273037856 # Number of instructions committed system.cpu.committedOps 327812213 # Number of ops (including micro ops) committed -system.cpu.discardedOps 4054235 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 4054236 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching system.cpu.cpi 1.588533 # CPI: cycles per instruction system.cpu.ipc 0.629512 # IPC: instructions per cycle -system.cpu.tickCycles 430193160 # Number of cycles that the object actually ticked -system.cpu.idleCycles 3536480 # Total number of cycles that the object has spent stopped +system.cpu.tickCycles 430193126 # Number of cycles that the object actually ticked +system.cpu.idleCycles 3536514 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 1354 # number of replacements -system.cpu.dcache.tags.tagsinuse 3085.768991 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 168782225 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 3085.769078 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168782221 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4511 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37415.700510 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37415.699623 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3085.768991 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 3085.769078 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.753362 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.753362 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3157 # Occupied blocks per task id @@ -406,62 +406,70 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 2432 system.cpu.dcache.tags.occ_task_id_percent::1024 0.770752 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 337583521 # Number of tag accesses system.cpu.dcache.tags.data_accesses 337583521 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 86712977 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 86712977 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 86649433 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 86649433 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 82047458 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 82047458 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 63540 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 63540 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 168760435 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168760435 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168760435 # number of overall hits -system.cpu.dcache.overall_hits::total 168760435 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2061 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2061 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 168696891 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168696891 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168760431 # number of overall hits +system.cpu.dcache.overall_hits::total 168760431 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2059 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2059 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 5219 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 5219 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 7280 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 7280 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 7280 # number of overall misses -system.cpu.dcache.overall_misses::total 7280 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 137684956 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 137684956 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 400150250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 400150250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 537835206 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 537835206 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 537835206 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 537835206 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 86715038 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 86715038 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_misses::cpu.data 6 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 6 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 7278 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 7278 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 7284 # number of overall misses +system.cpu.dcache.overall_misses::total 7284 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 136977706 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 136977706 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 400661500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 400661500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 537639206 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 537639206 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 537639206 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 537639206 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 86651492 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 86651492 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 63546 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 63546 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 168767715 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 168767715 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 168704169 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 168704169 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 168767715 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 168767715 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000024 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000024 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000064 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.000064 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000094 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.000094 # miss rate for SoftPFReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000043 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000043 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66804.927705 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 66804.927705 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76671.824104 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 76671.824104 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 73878.462363 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 73878.462363 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 73878.462363 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 73878.462363 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66526.326372 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 66526.326372 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76769.783483 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 76769.783483 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 73871.833746 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 73871.833746 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 73810.983800 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 73810.983800 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -472,56 +480,64 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 1010 # number of writebacks system.cpu.dcache.writebacks::total 1010 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 420 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 420 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 422 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 422 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2349 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 2349 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2769 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2769 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2769 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2769 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1641 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1641 # number of ReadReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 2771 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2771 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2771 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2771 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1637 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1637 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2870 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 2870 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4511 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4511 # number of demand (read+write) MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 4 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 4 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4507 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4507 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4511 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4511 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 109745542 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 109745542 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 219964750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 219964750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 329710292 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 329710292 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 329710292 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 329710292 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 109140792 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 109140792 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 220213500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 220213500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 320750 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 320750 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 329354292 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 329354292 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 329675042 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 329675042 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000063 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000063 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66877.234613 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66877.234613 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76642.770035 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76642.770035 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73090.288628 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 73090.288628 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73090.288628 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 73090.288628 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66671.222969 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66671.222969 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76729.442509 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76729.442509 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 80187.500000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 80187.500000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73076.168627 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 73076.168627 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73082.474396 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 73082.474396 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 36897 # number of replacements -system.cpu.icache.tags.tagsinuse 1924.852609 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 73252005 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1924.852858 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 73252007 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 38834 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1886.285343 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 1886.285394 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1924.852609 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.939869 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.939869 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1924.852858 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.939870 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.939870 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1937 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 88 # Occupied blocks per task id @@ -529,44 +545,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 34 system.cpu.icache.tags.age_task_id_blocks_1024::3 275 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1487 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.945801 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 146620514 # Number of tag accesses -system.cpu.icache.tags.data_accesses 146620514 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 73252005 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 73252005 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 73252005 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 73252005 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 73252005 # number of overall hits -system.cpu.icache.overall_hits::total 73252005 # number of overall hits +system.cpu.icache.tags.tag_accesses 146620518 # Number of tag accesses +system.cpu.icache.tags.data_accesses 146620518 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 73252007 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 73252007 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 73252007 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 73252007 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 73252007 # number of overall hits +system.cpu.icache.overall_hits::total 73252007 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 38835 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 38835 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 38835 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 38835 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 38835 # number of overall misses system.cpu.icache.overall_misses::total 38835 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 728456748 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 728456748 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 728456748 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 728456748 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 728456748 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 728456748 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 73290840 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 73290840 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 73290840 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 73290840 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 73290840 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 73290840 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 728387498 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 728387498 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 728387498 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 728387498 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 728387498 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 728387498 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 73290842 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 73290842 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 73290842 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 73290842 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 73290842 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 73290842 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000530 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000530 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000530 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000530 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000530 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000530 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18757.737814 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 18757.737814 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 18757.737814 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 18757.737814 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 18757.737814 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 18757.737814 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18755.954629 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 18755.954629 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 18755.954629 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 18755.954629 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 18755.954629 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 18755.954629 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -581,34 +597,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 38835 system.cpu.icache.demand_mshr_misses::total 38835 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 38835 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 38835 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 668757252 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 668757252 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 668757252 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 668757252 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 668757252 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 668757252 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 668686502 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 668686502 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 668686502 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 668686502 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 668686502 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 668686502 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000530 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000530 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000530 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000530 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000530 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000530 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17220.477713 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17220.477713 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17220.477713 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 17220.477713 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17220.477713 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 17220.477713 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17218.655903 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17218.655903 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17218.655903 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 17218.655903 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17218.655903 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 17218.655903 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 4197.194159 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 4197.194738 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 35781 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 5646 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 6.337407 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 353.722028 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3165.177467 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 678.294664 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 353.722054 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3165.177954 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 678.294730 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.010795 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.096594 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.020700 # Average percentage of cache occupancy @@ -646,17 +662,17 @@ system.cpu.l2cache.demand_misses::total 7628 # nu system.cpu.l2cache.overall_misses::cpu.inst 3424 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 4204 # number of overall misses system.cpu.l2cache.overall_misses::total 7628 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 258115750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 105039500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 363155250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 216891750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 216891750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 258115750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 321931250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 580047000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 258115750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 321931250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 580047000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 258045000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 104755500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 362800500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 217140500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 217140500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 258045000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 321896000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 579941000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 258045000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 321896000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 579941000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 38835 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 1641 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 40476 # number of ReadReq accesses(hits+misses) @@ -681,17 +697,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.175979 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.088168 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.931944 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.175979 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75384.272780 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77807.037037 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 76069.386259 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75995.707779 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75995.707779 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75384.272780 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76577.366794 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 76041.819612 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75384.272780 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76577.366794 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 76041.819612 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75363.609813 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77596.666667 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 75995.077503 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76082.866153 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76082.866153 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75363.609813 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76568.981922 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 76027.923440 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75363.609813 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76568.981922 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 76027.923440 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -720,17 +736,17 @@ system.cpu.l2cache.demand_mshr_misses::total 7584 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3422 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 4162 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7584 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 215130250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 85732250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 300862500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 181193250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 181193250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 215130250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 266925500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 482055750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 215130250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 266925500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 482055750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 215060000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 85447750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 300507750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 181443000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 181443000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 215060000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 266890750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 481950750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 215060000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 266890750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 481950750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.088116 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.797075 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.116859 # mshr miss rate for ReadReq accesses @@ -742,17 +758,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.174964 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.088116 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922634 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.174964 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62866.817650 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65544.533639 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63607.293869 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63487.473721 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63487.473721 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62866.817650 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64133.950024 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63562.203323 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62866.817650 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64133.950024 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63562.203323 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62846.288720 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65327.025994 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63532.293869 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63574.982481 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63574.982481 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62846.288720 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64125.600673 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63548.358386 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62846.288720 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64125.600673 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63548.358386 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 40476 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 40475 # Transaction distribution @@ -781,9 +797,9 @@ system.cpu.toL2Bus.snoop_fanout::max_value 3 # system.cpu.toL2Bus.snoop_fanout::total 44356 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 23188000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 58975248 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 58975998 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 7577708 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 7577458 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.membus.trans_dist::ReadReq 4730 # Transaction distribution system.membus.trans_dist::ReadResp 4730 # Transaction distribution @@ -804,9 +820,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 7584 # Request fanout histogram -system.membus.reqLayer0.occupancy 8969500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 8969000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 40264250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 40262750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |