diff options
Diffstat (limited to 'tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt')
| -rw-r--r-- | tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt | 1592 |
1 files changed, 798 insertions, 794 deletions
diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index 01e70293e..3bab29953 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -1,67 +1,67 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.111754 # Number of seconds simulated -sim_ticks 111753553500 # Number of ticks simulated -final_tick 111753553500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.120480 # Number of seconds simulated +sim_ticks 120480458500 # Number of ticks simulated +final_tick 120480458500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 142273 # Simulator instruction rate (inst/s) -host_op_rate 170814 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 58231903 # Simulator tick rate (ticks/s) -host_mem_usage 288696 # Number of bytes of host memory used -host_seconds 1919.11 # Real time elapsed on the host -sim_insts 273037220 # Number of instructions simulated -sim_ops 327811602 # Number of ops (including micro ops) simulated +host_inst_rate 129515 # Simulator instruction rate (inst/s) +host_op_rate 155497 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 57149813 # Simulator tick rate (ticks/s) +host_mem_usage 293332 # Number of bytes of host memory used +host_seconds 2108.15 # Real time elapsed on the host +sim_insts 273037218 # Number of instructions simulated +sim_ops 327811600 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 620544 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 4626112 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 168832 # Number of bytes read from this memory -system.physmem.bytes_read::total 5415488 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 620544 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 620544 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 9696 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 72283 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 2638 # Number of read requests responded to by this memory -system.physmem.num_reads::total 84617 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 5552790 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 41395659 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 1510753 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 48459202 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 5552790 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 5552790 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 5552790 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 41395659 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 1510753 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 48459202 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 84617 # Number of read requests accepted +system.physmem.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 1888064 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 14651392 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 167808 # Number of bytes read from this memory +system.physmem.bytes_read::total 16707264 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1888064 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1888064 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 29501 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 228928 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 2622 # Number of read requests responded to by this memory +system.physmem.num_reads::total 261051 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 15671122 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 121608037 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 1392823 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 138671982 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 15671122 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 15671122 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 15671122 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 121608037 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 1392823 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 138671982 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 261052 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 84617 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 261052 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 5415488 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 16707328 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 5415488 # Total read bytes from the system interface side +system.physmem.bytesReadSys 16707328 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 956 # Per bank write bursts -system.physmem.perBankRdBursts::1 811 # Per bank write bursts -system.physmem.perBankRdBursts::2 834 # Per bank write bursts -system.physmem.perBankRdBursts::3 2907 # Per bank write bursts -system.physmem.perBankRdBursts::4 10637 # Per bank write bursts -system.physmem.perBankRdBursts::5 59817 # Per bank write bursts -system.physmem.perBankRdBursts::6 152 # Per bank write bursts -system.physmem.perBankRdBursts::7 259 # Per bank write bursts -system.physmem.perBankRdBursts::8 225 # Per bank write bursts -system.physmem.perBankRdBursts::9 303 # Per bank write bursts -system.physmem.perBankRdBursts::10 3870 # Per bank write bursts -system.physmem.perBankRdBursts::11 811 # Per bank write bursts -system.physmem.perBankRdBursts::12 1141 # Per bank write bursts -system.physmem.perBankRdBursts::13 693 # Per bank write bursts -system.physmem.perBankRdBursts::14 638 # Per bank write bursts -system.physmem.perBankRdBursts::15 563 # Per bank write bursts +system.physmem.perBankRdBursts::0 1258 # Per bank write bursts +system.physmem.perBankRdBursts::1 69992 # Per bank write bursts +system.physmem.perBankRdBursts::2 1296 # Per bank write bursts +system.physmem.perBankRdBursts::3 10757 # Per bank write bursts +system.physmem.perBankRdBursts::4 42908 # Per bank write bursts +system.physmem.perBankRdBursts::5 121820 # Per bank write bursts +system.physmem.perBankRdBursts::6 160 # Per bank write bursts +system.physmem.perBankRdBursts::7 266 # Per bank write bursts +system.physmem.perBankRdBursts::8 224 # Per bank write bursts +system.physmem.perBankRdBursts::9 562 # Per bank write bursts +system.physmem.perBankRdBursts::10 7776 # Per bank write bursts +system.physmem.perBankRdBursts::11 812 # Per bank write bursts +system.physmem.perBankRdBursts::12 1213 # Per bank write bursts +system.physmem.perBankRdBursts::13 743 # Per bank write bursts +system.physmem.perBankRdBursts::14 656 # Per bank write bursts +system.physmem.perBankRdBursts::15 609 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -80,14 +80,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 111753395000 # Total gap between requests +system.physmem.totGap 120480449000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 84617 # Read request sizes (log2) +system.physmem.readPktSize::6 261052 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -95,19 +95,19 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 64967 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 17796 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 465 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 204297 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 43283 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 12075 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 298 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 226 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 234 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 208 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 173 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 172 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 172 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 53 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 182 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 216 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 113 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 58 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 31 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 21 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 22 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 18 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 18 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see @@ -191,86 +191,86 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 21291 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 254.217463 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 213.921670 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 155.515771 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 2572 12.08% 12.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 7102 33.36% 45.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8141 38.24% 83.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1445 6.79% 90.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1060 4.98% 95.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 699 3.28% 98.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 33 0.15% 98.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 27 0.13% 99.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 212 1.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 21291 # Bytes accessed per row activation -system.physmem.totQLat 818886094 # Total ticks spent queuing -system.physmem.totMemAccLat 2405454844 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 423085000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9677.56 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 67045 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 249.160415 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 181.717328 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 205.520754 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 18369 27.40% 27.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 21159 31.56% 58.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 11457 17.09% 76.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 6629 9.89% 85.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 4618 6.89% 92.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2220 3.31% 96.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1372 2.05% 98.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 491 0.73% 98.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 730 1.09% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 67045 # Bytes accessed per row activation +system.physmem.totQLat 2500931533 # Total ticks spent queuing +system.physmem.totMemAccLat 7395656533 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1305260000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9580.20 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28427.56 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 48.46 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 28330.20 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 138.67 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 48.46 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 138.67 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.38 # Data bus utilization in percentage -system.physmem.busUtilRead 0.38 # Data bus utilization in percentage for reads +system.physmem.busUtil 1.08 # Data bus utilization in percentage +system.physmem.busUtilRead 1.08 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.36 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.60 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 63316 # Number of row buffer hits during reads +system.physmem.readRowHits 193998 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 74.83 # Row buffer hit rate for reads +system.physmem.readRowHitRate 74.31 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 1320696.73 # Average gap between requests -system.physmem.pageHitRate 74.83 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 137093040 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 74802750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 595467600 # Energy for read commands per rank (pJ) +system.physmem.avgGap 461518.97 # Average gap between requests +system.physmem.pageHitRate 74.31 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 469687680 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 256278000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1937777400 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 7298853120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 61580578995 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 13031079750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 82717875255 # Total energy per rank (pJ) -system.physmem_0.averagePower 740.214288 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 21327892271 # Time in different power states -system.physmem_0.memoryStateTime::REF 3731520000 # Time in different power states +system.physmem_0.refreshEnergy 7868948880 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 73664414550 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 7668236250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 91865342760 # Total energy per rank (pJ) +system.physmem_0.averagePower 762.514125 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 12350213739 # Time in different power states +system.physmem_0.memoryStateTime::REF 4022980000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 86689152979 # Time in different power states +system.physmem_0.memoryStateTime::ACT 104104852261 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 23821560 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 12997875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 64092600 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 37134720 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 20262000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 98069400 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 7298853120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 10878672015 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 57506417250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 75784854420 # Total energy per rank (pJ) -system.physmem_1.averagePower 678.173227 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 95612479879 # Time in different power states -system.physmem_1.memoryStateTime::REF 3731520000 # Time in different power states +system.physmem_1.refreshEnergy 7868948880 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 16939770435 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 57426696000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 82390881435 # Total energy per rank (pJ) +system.physmem_1.averagePower 683.872818 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 95444315624 # Time in different power states +system.physmem_1.memoryStateTime::REF 4022980000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 12405217621 # Time in different power states +system.physmem_1.memoryStateTime::ACT 21009739880 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 35971731 # Number of BP lookups -system.cpu.branchPred.condPredicted 19265386 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 984189 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 17894968 # Number of BTB lookups -system.cpu.branchPred.BTBHits 13923402 # Number of BTB hits +system.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 35971487 # Number of BP lookups +system.cpu.branchPred.condPredicted 19266966 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 984300 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 17894295 # Number of BTB lookups +system.cpu.branchPred.BTBHits 13923321 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 77.806241 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 6951964 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 4431 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 2517343 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 2473442 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 43901 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 128855 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 77.808715 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 6951891 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 4417 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 2517210 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 2473355 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 43855 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 128902 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -300,7 +300,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -330,7 +330,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -360,7 +360,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -391,131 +391,131 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 111753553500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 223507108 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 120480458500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 240960918 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 12083599 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 309381854 # Number of instructions fetch has processed -system.cpu.fetch.Branches 35971731 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 23348808 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 209499863 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1989645 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 1258 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.icacheStallCycles 12852393 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 309387545 # Number of instructions fetch has processed +system.cpu.fetch.Branches 35971487 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 23348567 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 224289895 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1990323 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 1871 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 93 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 2666 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 82203342 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 33398 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 222582301 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.671920 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.267628 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 3026 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 82204082 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 34266 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 238142439 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.562665 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.293284 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 62373241 28.02% 28.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 40203334 18.06% 46.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 28080746 12.62% 58.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 91924980 41.30% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 77933727 32.73% 32.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 40203358 16.88% 49.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 28082672 11.79% 61.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 91922682 38.60% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 222582301 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.160942 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.384215 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 26238985 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 73050782 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 98117127 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 24314460 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 860947 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 6686817 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 134221 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 348541423 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3410145 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 860947 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 42548430 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 23450678 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 285531 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 105165670 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 50271045 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 344601348 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 1453656 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 7084396 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 85832 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 7483674 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 23725025 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 3279176 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 394880845 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2218133140 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 335914250 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 192916662 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 372230051 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 22650794 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 11588 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 11554 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 57533645 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 89989968 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 84391268 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1975718 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1902358 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 343283622 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 22608 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 339469619 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 966789 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 15494628 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 37288530 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 488 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 222582301 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.525142 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.109331 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 238142439 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.149283 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.283974 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 26809492 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 87975457 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 98235303 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 24260898 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 861289 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 6686645 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 134215 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 348536073 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3411178 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 861289 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 43087679 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 34729777 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 287359 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 105264108 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 53912227 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 344595535 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 1451317 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 7117459 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 85486 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 7456793 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 27429966 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 3277218 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 394867605 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2218081796 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 335910446 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 192911530 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 372230048 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 22637557 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 11606 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 11573 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 57394706 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 89984018 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 84392471 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1976841 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1898355 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 343274386 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 22623 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 339465004 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 967637 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 15485409 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 37250778 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 503 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 238142439 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.425470 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.136916 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 42440680 19.07% 19.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 76122495 34.20% 53.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 59389973 26.68% 79.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 34692267 15.59% 95.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 9226095 4.15% 99.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 678749 0.30% 99.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 32042 0.01% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 57979720 24.35% 24.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 76155774 31.98% 56.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 59457503 24.97% 81.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 34550396 14.51% 95.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 9286722 3.90% 99.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 677796 0.28% 99.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 34528 0.01% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 222582301 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 238142439 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9228112 7.75% 7.75% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 7358 0.01% 7.75% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 7.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 7.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 7.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 7.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 237798 0.20% 7.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 147681 0.12% 8.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 70485 0.06% 8.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 67886 0.06% 8.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 638269 0.54% 8.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 297789 0.25% 8.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 542439 0.46% 9.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.44% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 51542568 43.28% 52.71% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 56315471 47.29% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9217758 7.75% 7.75% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 7319 0.01% 7.76% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 7.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 7.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 7.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 7.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 238781 0.20% 7.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 138932 0.12% 8.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 70694 0.06% 8.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 68373 0.06% 8.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 637081 0.54% 8.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 296736 0.25% 8.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 541785 0.46% 9.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.43% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 51510154 43.32% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 56187310 47.25% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 108184507 31.87% 31.87% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2148145 0.63% 32.50% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 108183295 31.87% 31.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2148337 0.63% 32.50% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 32.50% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 32.50% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 32.50% # Type of FU issued @@ -534,103 +534,103 @@ system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 32.50% # Ty system.cpu.iq.FU_type_0::SimdShift 0 0.00% 32.50% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 32.50% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 32.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 6792731 2.00% 34.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 6792696 2.00% 34.50% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 34.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 8635726 2.54% 37.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 3210403 0.95% 37.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1592905 0.47% 38.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 20864008 6.15% 44.61% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 7178651 2.11% 46.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 7141492 2.10% 48.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 175295 0.05% 48.88% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 90027492 26.52% 75.40% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 83518264 24.60% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 8634939 2.54% 37.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 3210556 0.95% 37.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1592986 0.47% 38.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 20863290 6.15% 44.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 7179112 2.11% 46.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 7141893 2.10% 48.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 175297 0.05% 48.88% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 90024001 26.52% 75.40% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 83518602 24.60% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 339469619 # Type of FU issued -system.cpu.iq.rate 1.518831 # Inst issue rate -system.cpu.iq.fu_busy_cnt 119095856 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.350829 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 738018306 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 235153924 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 219171367 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 283565878 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 123658767 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 116921576 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 293614389 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 164951086 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 5389138 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 339465004 # Type of FU issued +system.cpu.iq.rate 1.408797 # Inst issue rate +system.cpu.iq.fu_busy_cnt 118914923 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.350301 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 753593457 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 235149136 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 219170609 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 283361550 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 123645361 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 116917491 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 293630516 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 164749411 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 5409371 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4257693 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7295 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11836 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2015651 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4251743 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7382 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 12082 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2016854 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 126905 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 613909 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 126951 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 613385 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 860947 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1344821 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 736472 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 343307622 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 861289 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1346418 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1223561 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 343298428 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 89989968 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 84391268 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 11575 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 7371 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 729404 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11836 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 437891 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 454375 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 892266 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 337441545 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 89439870 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2028074 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 89984018 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 84392471 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 11590 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 7654 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1216581 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 12082 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 438027 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 454511 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 892538 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 337435973 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 89435470 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2029031 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1392 # number of nop insts executed -system.cpu.iew.exec_refs 172567373 # number of memory reference insts executed -system.cpu.iew.exec_branches 31555849 # Number of branches executed -system.cpu.iew.exec_stores 83127503 # Number of stores executed -system.cpu.iew.exec_rate 1.509758 # Inst execution rate -system.cpu.iew.wb_sent 336239137 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 336092943 # cumulative count of insts written-back -system.cpu.iew.wb_producers 151867680 # num instructions producing a value -system.cpu.iew.wb_consumers 263704827 # num instructions consuming a value -system.cpu.iew.wb_rate 1.503724 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.575900 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 14172678 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 1419 # number of nop insts executed +system.cpu.iew.exec_refs 172563167 # number of memory reference insts executed +system.cpu.iew.exec_branches 31555788 # Number of branches executed +system.cpu.iew.exec_stores 83127697 # Number of stores executed +system.cpu.iew.exec_rate 1.400376 # Inst execution rate +system.cpu.iew.wb_sent 336234414 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 336088100 # cumulative count of insts written-back +system.cpu.iew.wb_producers 151781597 # num instructions producing a value +system.cpu.iew.wb_consumers 263546089 # num instructions consuming a value +system.cpu.iew.wb_rate 1.394783 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.575921 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 14163176 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 850314 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 220392023 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.487405 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.078236 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 850428 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 235953046 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.389311 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.042233 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 89247998 40.50% 40.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 67546822 30.65% 71.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 20918501 9.49% 80.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 13253983 6.01% 86.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 8642695 3.92% 90.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 4496391 2.04% 92.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 3033426 1.38% 93.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 2604506 1.18% 95.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 10647701 4.83% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 104793604 44.41% 44.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 67594704 28.65% 73.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 20883417 8.85% 81.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 13239055 5.61% 87.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 8655759 3.67% 91.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 4517031 1.91% 93.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 3019754 1.28% 94.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 2590982 1.10% 95.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 10658740 4.52% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 220392023 # Number of insts commited each cycle -system.cpu.commit.committedInsts 273037832 # Number of instructions committed -system.cpu.commit.committedOps 327812214 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 235953046 # Number of insts commited each cycle +system.cpu.commit.committedInsts 273037830 # Number of instructions committed +system.cpu.commit.committedOps 327812212 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 168107892 # Number of memory references committed system.cpu.commit.loads 85732275 # Number of loads committed system.cpu.commit.membars 11033 # Number of memory barriers committed -system.cpu.commit.branches 30563526 # Number of branches committed +system.cpu.commit.branches 30563525 # Number of branches committed system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions. -system.cpu.commit.int_insts 258331704 # Number of committed integer instructions. +system.cpu.commit.int_insts 258331703 # Number of committed integer instructions. system.cpu.commit.function_calls 6225114 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 104312487 31.82% 31.82% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 104312485 31.82% 31.82% # Class of committed instruction system.cpu.commit.op_class_0::IntMult 2145917 0.65% 32.48% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 0 0.00% 32.48% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 32.48% # Class of committed instruction @@ -663,157 +663,157 @@ system.cpu.commit.op_class_0::MemRead 85732275 26.15% 74.87% # Cl system.cpu.commit.op_class_0::MemWrite 82375617 25.13% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 327812214 # Class of committed instruction -system.cpu.commit.bw_lim_events 10647701 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 551726691 # The number of ROB reads -system.cpu.rob.rob_writes 686162246 # The number of ROB writes -system.cpu.timesIdled 18335 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 924807 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 273037220 # Number of Instructions Simulated -system.cpu.committedOps 327811602 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.818596 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.818596 # CPI: Total CPI of All Threads -system.cpu.ipc 1.221604 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.221604 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 325161919 # number of integer regfile reads -system.cpu.int_regfile_writes 134094717 # number of integer regfile writes -system.cpu.fp_regfile_reads 186641875 # number of floating regfile reads -system.cpu.fp_regfile_writes 131668024 # number of floating regfile writes -system.cpu.cc_regfile_reads 1279432977 # number of cc regfile reads -system.cpu.cc_regfile_writes 80060950 # number of cc regfile writes -system.cpu.misc_regfile_reads 1056766062 # number of misc regfile reads +system.cpu.commit.op_class_0::total 327812212 # Class of committed instruction +system.cpu.commit.bw_lim_events 10658740 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 567267171 # The number of ROB reads +system.cpu.rob.rob_writes 686142351 # The number of ROB writes +system.cpu.timesIdled 39413 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 2818479 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 273037218 # Number of Instructions Simulated +system.cpu.committedOps 327811600 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.882520 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.882520 # CPI: Total CPI of All Threads +system.cpu.ipc 1.133118 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.133118 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 325162337 # number of integer regfile reads +system.cpu.int_regfile_writes 134093699 # number of integer regfile writes +system.cpu.fp_regfile_reads 186638060 # number of floating regfile reads +system.cpu.fp_regfile_writes 131662989 # number of floating regfile writes +system.cpu.cc_regfile_reads 1279404689 # number of cc regfile reads +system.cpu.cc_regfile_writes 80058303 # number of cc regfile writes +system.cpu.misc_regfile_reads 1056730531 # number of misc regfile reads system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 1542955 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.836799 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 162076726 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1543467 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 105.008222 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 85416000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.836799 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999681 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999681 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 1542807 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.846983 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 162052499 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1543319 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 105.002594 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 87321000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.846983 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999701 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999701 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 309 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 113 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 308 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 90 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 333528119 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 333528119 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 81065236 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 81065236 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 80920030 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 80920030 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 69611 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 69611 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 10906 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 10906 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 333478959 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 333478959 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 81039652 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 81039652 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 80921351 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 80921351 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 69633 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 69633 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 10908 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 10908 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 161985266 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 161985266 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 162054877 # number of overall hits -system.cpu.dcache.overall_hits::total 162054877 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2782957 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2782957 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1132669 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1132669 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 161961003 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 161961003 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 162030636 # number of overall hits +system.cpu.dcache.overall_hits::total 162030636 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2784011 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2784011 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1131348 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1131348 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 18 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 18 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 3915626 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3915626 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3915644 # number of overall misses -system.cpu.dcache.overall_misses::total 3915644 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 31092984500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 31092984500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9127104911 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9127104911 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 182000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 182000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 40220089411 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 40220089411 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 40220089411 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 40220089411 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 83848193 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 83848193 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 3915359 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3915359 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3915377 # number of overall misses +system.cpu.dcache.overall_misses::total 3915377 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 45256653500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 45256653500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9138834402 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9138834402 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 184000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 184000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 54395487902 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 54395487902 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 54395487902 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 54395487902 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 83823663 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 83823663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052699 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052699 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 69629 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 69629 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10910 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 10910 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 69651 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 69651 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10912 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 10912 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 165900892 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 165900892 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 165970521 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 165970521 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.033190 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.033190 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013804 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.013804 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000259 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.000259 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_accesses::cpu.data 165876362 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 165876362 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 165946013 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 165946013 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.033213 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.033213 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013788 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.013788 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000258 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.000258 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000367 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000367 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.023602 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.023602 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.023592 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.023592 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11172.642804 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11172.642804 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8058.051303 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 8058.051303 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 45500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 45500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 10271.688208 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 10271.688208 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 10271.640990 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 10271.640990 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.023604 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.023604 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.023594 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.023594 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16255.917631 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16255.917631 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8077.827867 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 8077.827867 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 46000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 46000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 13892.848115 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 13892.848115 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 13892.784246 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 13892.784246 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1079488 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1086145 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 136770 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 136219 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 7.892725 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 1542955 # number of writebacks -system.cpu.dcache.writebacks::total 1542955 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1460236 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1460236 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 911920 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 911920 # number of WriteReq MSHR hits +system.cpu.dcache.avg_blocked_cycles::no_targets 7.973521 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 1542807 # number of writebacks +system.cpu.dcache.writebacks::total 1542807 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1461430 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1461430 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 910604 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 910604 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2372156 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2372156 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2372156 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2372156 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1322721 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1322721 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 220749 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 220749 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 2372034 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2372034 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2372034 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2372034 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1322581 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1322581 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 220744 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 220744 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 11 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 11 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1543470 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1543470 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1543481 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1543481 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15298451500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 15298451500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1831859691 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1831859691 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 695500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 695500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17130311191 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 17130311191 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17131006691 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 17131006691 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015775 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015775 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 1543325 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1543325 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1543336 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1543336 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 25407816000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 25407816000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1834277181 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1834277181 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 705000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 705000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27242093181 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 27242093181 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27242798181 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 27242798181 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015778 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015778 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002690 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002690 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000158 # mshr miss rate for SoftPFReq accesses @@ -822,392 +822,396 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.009304 system.cpu.dcache.demand_mshr_miss_rate::total 0.009304 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.009300 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.009300 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11565.894471 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11565.894471 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8298.382738 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8298.382738 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 63227.272727 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 63227.272727 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11098.570877 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11098.570877 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11098.942385 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11098.942385 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 726201 # number of replacements -system.cpu.icache.tags.tagsinuse 511.803602 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 81470529 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 726713 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 112.108259 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 331355500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.803602 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999616 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999616 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19210.782553 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19210.782553 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8309.522257 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8309.522257 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 64090.909091 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 64090.909091 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17651.559575 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 17651.559575 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17651.890568 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 17651.890568 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 725593 # number of replacements +system.cpu.icache.tags.tagsinuse 511.815316 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 81471161 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 726105 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 112.203002 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 334835500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.815316 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999639 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999639 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 242 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 243 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 14 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 69 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 70 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 165133375 # Number of tag accesses -system.cpu.icache.tags.data_accesses 165133375 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 81470529 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 81470529 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 81470529 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 81470529 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 81470529 # number of overall hits -system.cpu.icache.overall_hits::total 81470529 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 732796 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 732796 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 732796 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 732796 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 732796 # number of overall misses -system.cpu.icache.overall_misses::total 732796 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 6565806949 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 6565806949 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 6565806949 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 6565806949 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 6565806949 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 6565806949 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 82203325 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 82203325 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 82203325 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 82203325 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 82203325 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 82203325 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008914 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.008914 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.008914 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.008914 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.008914 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.008914 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8959.938303 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 8959.938303 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 8959.938303 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 8959.938303 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 8959.938303 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 8959.938303 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 64284 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 94 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 3051 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 165134244 # Number of tag accesses +system.cpu.icache.tags.data_accesses 165134244 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 81471161 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 81471161 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 81471161 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 81471161 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 81471161 # number of overall hits +system.cpu.icache.overall_hits::total 81471161 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 732901 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 732901 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 732901 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 732901 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 732901 # number of overall misses +system.cpu.icache.overall_misses::total 732901 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 8031652441 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 8031652441 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 8031652441 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 8031652441 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 8031652441 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 8031652441 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 82204062 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 82204062 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 82204062 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 82204062 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 82204062 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 82204062 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008916 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.008916 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.008916 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.008916 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.008916 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.008916 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10958.713989 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 10958.713989 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 10958.713989 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 10958.713989 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 10958.713989 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 10958.713989 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 128534 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 100 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 4274 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 21.069813 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 31.333333 # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 726201 # number of writebacks -system.cpu.icache.writebacks::total 726201 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 6071 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 6071 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 6071 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 6071 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 6071 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 6071 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 726725 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 726725 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 726725 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 726725 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 726725 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 726725 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 6109081458 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 6109081458 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 6109081458 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 6109081458 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 6109081458 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 6109081458 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008841 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008841 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008841 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.008841 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008841 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.008841 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8406.318013 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 8406.318013 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8406.318013 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 8406.318013 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8406.318013 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 8406.318013 # average overall mshr miss latency -system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.prefetcher.num_hwpf_issued 402434 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 402547 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 102 # number of redundant prefetches already in prefetch queue +system.cpu.icache.avg_blocked_cycles::no_mshrs 30.073467 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 33.333333 # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 725593 # number of writebacks +system.cpu.icache.writebacks::total 725593 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 6780 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 6780 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 6780 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 6780 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 6780 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 6780 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 726121 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 726121 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 726121 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 726121 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 726121 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 726121 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 7527879949 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 7527879949 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 7527879949 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 7527879949 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 7527879949 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 7527879949 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008833 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008833 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008833 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.008833 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008833 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.008833 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 10367.252771 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 10367.252771 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10367.252771 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 10367.252771 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10367.252771 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 10367.252771 # average overall mshr miss latency +system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.prefetcher.num_hwpf_issued 402848 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 402975 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 113 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 28085 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.prefetcher.pfSpanPage 27937 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 5603.177963 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3041133 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 6750 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 450.538222 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 5253.562311 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1811987 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 6314 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 286.979252 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 5495.535708 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 107.642255 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.335421 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.006570 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.341991 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 497 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 6253 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::0 16 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::writebacks 5154.206528 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 99.355783 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.314588 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.006064 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.320652 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 192 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 6122 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::0 12 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::1 22 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::2 344 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 2 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 113 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 146 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 912 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 72 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 5048 # 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number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 29502 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 29502 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 228171 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 228171 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 29502 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 228928 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 258430 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 29502 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 228928 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 54157 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 312587 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 187753381 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 187753381 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 251000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 251000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 53315000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 53315000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2084473500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2084473500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 14900259000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 14900259000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2084473500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14953574000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17038047500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2084473500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14953574000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 187753381 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17225800881 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.928571 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.928571 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.003307 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.003307 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.013343 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.013343 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.054095 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.054095 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.013343 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.046832 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.036112 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.013343 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.046832 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.941176 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.941176 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.003429 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.003429 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.040634 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.040634 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.172520 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.172520 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.040634 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.148335 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.113878 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.040634 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.148335 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.058865 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3448.748330 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 3448.748330 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14384.615385 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14384.615385 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68908.904110 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68908.904110 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64966.016914 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64966.016914 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 64708.293153 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 64708.293153 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64966.016914 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64750.715936 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64776.180485 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64966.016914 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64750.715936 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3448.748330 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41071.748859 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 4539362 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2269187 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 254586 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 130262 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 52910 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 77352 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 2049447 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 968360 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1300796 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 81249 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 53022 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 14 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 14 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 220745 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 220745 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 726725 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1322722 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2179572 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4629917 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6809489 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 92982208 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 197531008 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 290513216 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 134350 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 5056 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 2404477 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.192237 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.468638 # Request fanout histogram +system.cpu.l2cache.overall_mshr_miss_rate::total 0.137742 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3466.834961 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 3466.834961 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15687.500000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15687.500000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70429.326288 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70429.326288 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70655.328452 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70655.328452 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 65303.035881 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 65303.035881 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70655.328452 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65319.987070 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65929.062028 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70655.328452 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65319.987070 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3466.834961 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55107.220969 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 4537857 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2268434 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 254467 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 51535 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 51534 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 2048700 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 968253 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1300147 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 55525 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 220739 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 220739 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 726121 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1322580 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2177753 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4629479 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6807232 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 92904448 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 197512064 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 290416512 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 55606 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 5184 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 2324982 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.131629 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.338088 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2019600 83.99% 83.99% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 307525 12.79% 96.78% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 77352 3.22% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2018948 86.84% 86.84% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 306033 13.16% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2404477 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4538837000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 4.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1090392888 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2315538337 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 2.1 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 83887 # Transaction distribution -system.membus.trans_dist::UpgradeReq 13 # Transaction distribution -system.membus.trans_dist::ReadExReq 730 # Transaction distribution -system.membus.trans_dist::ReadExResp 730 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 83887 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 169247 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 169247 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 5415488 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 5415488 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoop_fanout::total 2324982 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4537328500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 3.8 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1089458442 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 2315007958 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.9 # Layer utilization (%) +system.membus.snoop_filter.tot_requests 261068 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 253748 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 260294 # Transaction distribution +system.membus.trans_dist::UpgradeReq 16 # Transaction distribution +system.membus.trans_dist::ReadExReq 757 # Transaction distribution +system.membus.trans_dist::ReadExResp 757 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 260295 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 522119 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 522119 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16707264 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 16707264 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 84630 # Request fanout histogram +system.membus.snoop_fanout::samples 261068 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 84630 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 261068 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 84630 # Request fanout histogram -system.membus.reqLayer0.occupancy 108151910 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 445724357 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.4 # Layer utilization (%) +system.membus.snoop_fanout::total 261068 # Request fanout histogram +system.membus.reqLayer0.occupancy 329929457 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 1377865586 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 1.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- |