diff options
Diffstat (limited to 'tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt')
| -rw-r--r-- | tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt | 1216 |
1 files changed, 687 insertions, 529 deletions
diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index 908860e43..843436b83 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -1,32 +1,190 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.070882 # Number of seconds simulated -sim_ticks 70882487500 # Number of ticks simulated -final_tick 70882487500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.071023 # Number of seconds simulated +sim_ticks 71023388000 # Number of ticks simulated +final_tick 71023388000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 146290 # Simulator instruction rate (inst/s) -host_op_rate 187023 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 37976354 # Simulator tick rate (ticks/s) -host_mem_usage 236976 # Number of bytes of host memory used -host_seconds 1866.49 # Real time elapsed on the host +host_inst_rate 129198 # Simulator instruction rate (inst/s) +host_op_rate 165172 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 33606101 # Simulator tick rate (ticks/s) +host_mem_usage 240544 # Number of bytes of host memory used +host_seconds 2113.41 # Real time elapsed on the host sim_insts 273048441 # Number of instructions simulated sim_ops 349076165 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 194880 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 272768 # Number of bytes read from this memory -system.physmem.bytes_read::total 467648 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 272832 # Number of bytes read from this memory +system.physmem.bytes_read::total 467712 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 194880 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 194880 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu.inst 3045 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 4262 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7307 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2749339 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3848172 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6597511 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2749339 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2749339 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2749339 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3848172 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6597511 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::cpu.data 4263 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7308 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2743885 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3841439 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6585324 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2743885 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2743885 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2743885 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3841439 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6585324 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7308 # Total number of read requests seen +system.physmem.writeReqs 0 # Total number of write requests seen +system.physmem.cpureqs 7308 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 467712 # Total number of bytes read from memory +system.physmem.bytesWritten 0 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 467712 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 345 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 467 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 513 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 578 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 475 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 461 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 441 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 510 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 480 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 494 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 484 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 551 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 363 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 415 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 369 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 362 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis +system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 71023232000 # Total gap between requests +system.physmem.readPktSize::0 0 # Categorize read packet sizes +system.physmem.readPktSize::1 0 # Categorize read packet sizes +system.physmem.readPktSize::2 0 # Categorize read packet sizes +system.physmem.readPktSize::3 0 # Categorize read packet sizes +system.physmem.readPktSize::4 0 # Categorize read packet sizes +system.physmem.readPktSize::5 0 # Categorize read packet sizes +system.physmem.readPktSize::6 7308 # Categorize read packet sizes +system.physmem.readPktSize::7 0 # Categorize read packet sizes +system.physmem.readPktSize::8 0 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # categorize write packet sizes +system.physmem.writePktSize::1 0 # categorize write packet sizes +system.physmem.writePktSize::2 0 # categorize write packet sizes +system.physmem.writePktSize::3 0 # categorize write packet sizes +system.physmem.writePktSize::4 0 # categorize write packet sizes +system.physmem.writePktSize::5 0 # categorize write packet sizes +system.physmem.writePktSize::6 0 # categorize write packet sizes +system.physmem.writePktSize::7 0 # categorize write packet sizes +system.physmem.writePktSize::8 0 # categorize write packet sizes +system.physmem.neitherpktsize::0 0 # categorize neither packet sizes +system.physmem.neitherpktsize::1 0 # categorize neither packet sizes +system.physmem.neitherpktsize::2 0 # categorize neither packet sizes +system.physmem.neitherpktsize::3 0 # categorize neither packet sizes +system.physmem.neitherpktsize::4 0 # categorize neither packet sizes +system.physmem.neitherpktsize::5 0 # categorize neither packet sizes +system.physmem.neitherpktsize::6 0 # categorize neither packet sizes +system.physmem.neitherpktsize::7 0 # categorize neither packet sizes +system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.rdQLenPdf::0 4207 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2152 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 666 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 201 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 75 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.totQLat 41389289 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 172709289 # Sum of mem lat for all requests +system.physmem.totBusLat 29232000 # Total cycles spent in databus access +system.physmem.totBankLat 102088000 # Total cycles spent in bank access +system.physmem.avgQLat 5663.56 # Average queueing delay per request +system.physmem.avgBankLat 13969.35 # Average bank access latency per request +system.physmem.avgBusLat 4000.00 # Average bus latency per request +system.physmem.avgMemAccLat 23632.91 # Average memory access latency +system.physmem.avgRdBW 6.59 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 6.59 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.04 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.00 # Average read queue length over time +system.physmem.avgWrQLen 0.00 # Average write queue length over time +system.physmem.readRowHits 6370 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate 87.16 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 9718559.39 # Average gap between requests system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -70,107 +228,107 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 141764976 # number of cpu cycles simulated +system.cpu.numCycles 142046777 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 43022632 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 21746290 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 2100537 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 27784307 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 17845610 # Number of BTB hits +system.cpu.BPredUnit.lookups 43162042 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 21862143 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 2121703 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 28877793 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 17918646 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 6965581 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 7462 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 40878725 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 328721134 # Number of instructions fetch has processed -system.cpu.fetch.Branches 43022632 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 24811191 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 73667201 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 8391169 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 20823021 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 27 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 3522 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 39401519 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 692730 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 141652682 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.982295 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.454701 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 6972885 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 7671 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 40968439 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 329355833 # Number of instructions fetch has processed +system.cpu.fetch.Branches 43162042 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 24891531 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 73809901 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 8464308 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 20842753 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 28 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 2971 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 39491995 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 707720 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 141956225 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.979912 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.453592 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 68666188 48.48% 48.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 7372946 5.20% 53.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 5824782 4.11% 57.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 6228810 4.40% 62.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4953654 3.50% 65.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4319066 3.05% 68.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3319868 2.34% 71.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 4326916 3.05% 74.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 36640452 25.87% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 68825893 48.48% 48.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 7402388 5.21% 53.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 5830184 4.11% 57.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 6288593 4.43% 62.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4967322 3.50% 65.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4323548 3.05% 68.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3311772 2.33% 71.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4321361 3.04% 74.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 36685164 25.84% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 141652682 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.303479 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.318775 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 47724056 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 16047440 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 69280897 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 2389978 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 6210311 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 7496443 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 70615 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 414536105 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 220570 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 6210311 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 53491207 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1558118 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 338571 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 65828585 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 14225890 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 403967880 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 63 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1665803 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 10197275 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 723 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 443295910 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2386846444 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1300310044 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1086536400 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 141956225 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.303858 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.318643 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 47854672 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 16043866 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 69433090 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 2362421 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 6262176 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 7513619 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 70716 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 415062954 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 220817 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 6262176 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 53639950 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1545689 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 333184 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 65936980 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 14238246 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 404539854 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 67 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1667551 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 10176735 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 553 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 443995291 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2389355526 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1302857658 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1086497868 # Number of floating rename lookups system.cpu.rename.CommittedMaps 384584946 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 58710964 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 14469 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 14467 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 35655672 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 105463248 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 93220202 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 4594940 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5698907 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 391915159 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 25548 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 378021086 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1395950 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 41892562 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 109796784 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1071 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 141652682 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.668648 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.042717 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 59410345 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 14542 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 14541 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 35671511 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 105577606 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 93228051 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 4593885 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5660351 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 392311117 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 25611 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 378254160 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1403521 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 42287591 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 111052876 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1134 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 141956225 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.664583 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.042822 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 28697410 20.26% 20.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 20492119 14.47% 34.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 20907256 14.76% 49.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 18207035 12.85% 62.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 24094157 17.01% 79.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15966233 11.27% 90.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 9051361 6.39% 97.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3319497 2.34% 99.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 917614 0.65% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 28896984 20.36% 20.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 20515288 14.45% 34.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 20937445 14.75% 49.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 18231025 12.84% 62.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 24110473 16.98% 79.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15997056 11.27% 90.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 9050570 6.38% 97.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3298757 2.32% 99.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 918627 0.65% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 141652682 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 141956225 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 8869 0.05% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 4699 0.03% 0.08% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9062 0.05% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 4694 0.03% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.08% # attempts to use FU when none available @@ -189,127 +347,127 @@ system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.08% # at system.cpu.iq.fu_full::SimdShift 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 45720 0.25% 0.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 45808 0.25% 0.33% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 7848 0.04% 0.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 429 0.00% 0.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 7711 0.04% 0.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 383 0.00% 0.38% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatDiv 3 0.00% 0.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 193652 1.08% 1.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 4980 0.03% 1.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 240582 1.34% 2.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.82% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9467921 52.63% 55.44% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 8015707 44.56% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 193806 1.08% 1.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 5491 0.03% 1.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 241038 1.34% 2.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.83% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9458380 52.63% 55.45% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 8006771 44.55% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 128195849 33.91% 33.91% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2174611 0.58% 34.49% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.49% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.49% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.49% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.49% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.49% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.49% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 34.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 6839706 1.81% 36.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 8692181 2.30% 38.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 3465000 0.92% 39.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1622054 0.43% 39.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 21343322 5.65% 45.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 7172329 1.90% 47.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 7135364 1.89% 49.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 49.42% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 102447083 27.10% 76.52% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 88758301 23.48% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 128369790 33.94% 33.94% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2174598 0.57% 34.51% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 34.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 6843583 1.81% 36.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 8689764 2.30% 38.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 3465929 0.92% 39.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1622822 0.43% 39.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 21343412 5.64% 45.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 7172666 1.90% 47.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 7136167 1.89% 49.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 175288 0.05% 49.44% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 102562726 27.11% 76.55% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 88697415 23.45% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 378021086 # Type of FU issued -system.cpu.iq.rate 2.666534 # Inst issue rate -system.cpu.iq.fu_busy_cnt 17990410 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.047591 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 665853263 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 301144367 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 252283124 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 251227951 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 132702727 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 118872712 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 266490153 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 129521343 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 10844694 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 378254160 # Type of FU issued +system.cpu.iq.rate 2.662884 # Inst issue rate +system.cpu.iq.fu_busy_cnt 17973147 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.047516 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 666559792 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 301879538 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 252435570 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 251281421 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 132758695 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 118859507 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 266684443 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 129542864 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 10845590 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 10812156 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 121101 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14360 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 10842267 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 10926514 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 120350 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14368 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 10850116 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 29815 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 119 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 27154 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 78 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 6210311 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 59816 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 7651 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 391949728 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1062817 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 105463248 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 93220202 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 14378 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 211 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 349 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14360 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1675475 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 499111 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 2174586 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 373364048 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 101084784 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 4657038 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 6262176 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 55211 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 11686 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 392346402 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1078418 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 105577606 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 93228051 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 14439 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 194 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 331 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14368 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1702737 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 499287 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 2202024 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 373561232 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 101191974 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 4692928 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9021 # number of nop insts executed -system.cpu.iew.exec_refs 188503459 # number of memory reference insts executed -system.cpu.iew.exec_branches 38700482 # Number of branches executed -system.cpu.iew.exec_stores 87418675 # Number of stores executed -system.cpu.iew.exec_rate 2.633683 # Inst execution rate -system.cpu.iew.wb_sent 371949572 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 371155836 # cumulative count of insts written-back -system.cpu.iew.wb_producers 184798274 # num instructions producing a value -system.cpu.iew.wb_consumers 367725403 # num instructions consuming a value +system.cpu.iew.exec_nop 9674 # number of nop insts executed +system.cpu.iew.exec_refs 188550520 # number of memory reference insts executed +system.cpu.iew.exec_branches 38725245 # Number of branches executed +system.cpu.iew.exec_stores 87358546 # Number of stores executed +system.cpu.iew.exec_rate 2.629847 # Inst execution rate +system.cpu.iew.wb_sent 372099364 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 371295077 # cumulative count of insts written-back +system.cpu.iew.wb_producers 184920977 # num instructions producing a value +system.cpu.iew.wb_consumers 367888043 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.618107 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.502544 # average fanout of values written-back +system.cpu.iew.wb_rate 2.613893 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.502656 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 42873018 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 43269770 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 24477 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 2030662 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 135442372 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.577309 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.655328 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 2051746 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 135694050 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.572528 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.654395 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 38119190 28.14% 28.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 29150867 21.52% 49.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13483643 9.96% 59.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11130935 8.22% 67.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 13797972 10.19% 78.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7276796 5.37% 83.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 3948237 2.92% 86.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3977327 2.94% 89.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 14557405 10.75% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 38297743 28.22% 28.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 29217550 21.53% 49.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13522381 9.97% 59.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11119570 8.19% 67.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 13774007 10.15% 78.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7289874 5.37% 83.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 3949510 2.91% 86.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3974023 2.93% 89.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 14549392 10.72% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 135442372 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 135694050 # Number of insts commited each cycle system.cpu.commit.committedInsts 273049053 # Number of instructions committed system.cpu.commit.committedOps 349076777 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -320,70 +478,70 @@ system.cpu.commit.branches 36549055 # Nu system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions. system.cpu.commit.int_insts 279593983 # Number of committed integer instructions. system.cpu.commit.function_calls 6225112 # Number of function calls committed. -system.cpu.commit.bw_lim_events 14557405 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 14549392 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 512832239 # The number of ROB reads -system.cpu.rob.rob_writes 790114412 # The number of ROB writes -system.cpu.timesIdled 3064 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 112294 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 513488682 # The number of ROB reads +system.cpu.rob.rob_writes 790959694 # The number of ROB writes +system.cpu.timesIdled 2717 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 90552 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 273048441 # Number of Instructions Simulated system.cpu.committedOps 349076165 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 273048441 # Number of Instructions Simulated -system.cpu.cpi 0.519194 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.519194 # CPI: Total CPI of All Threads -system.cpu.ipc 1.926064 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.926064 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1783379175 # number of integer regfile reads -system.cpu.int_regfile_writes 236079321 # number of integer regfile writes -system.cpu.fp_regfile_reads 189868959 # number of floating regfile reads -system.cpu.fp_regfile_writes 133650660 # number of floating regfile writes -system.cpu.misc_regfile_reads 990849298 # number of misc regfile reads +system.cpu.cpi 0.520226 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.520226 # CPI: Total CPI of All Threads +system.cpu.ipc 1.922243 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.922243 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1784209945 # number of integer regfile reads +system.cpu.int_regfile_writes 236299492 # number of integer regfile writes +system.cpu.fp_regfile_reads 189823111 # number of floating regfile reads +system.cpu.fp_regfile_writes 133661428 # number of floating regfile writes +system.cpu.misc_regfile_reads 991633784 # number of misc regfile reads system.cpu.misc_regfile_writes 34426469 # number of misc regfile writes -system.cpu.icache.replacements 13928 # number of replacements -system.cpu.icache.tagsinuse 1856.985526 # Cycle average of tags in use -system.cpu.icache.total_refs 39384906 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 15824 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 2488.934909 # Average number of references to valid blocks. +system.cpu.icache.replacements 13962 # number of replacements +system.cpu.icache.tagsinuse 1856.548325 # Cycle average of tags in use +system.cpu.icache.total_refs 39475406 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 15856 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 2489.619450 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1856.985526 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.906731 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.906731 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 39384906 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 39384906 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 39384906 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 39384906 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 39384906 # number of overall hits -system.cpu.icache.overall_hits::total 39384906 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 16613 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 16613 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 16613 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 16613 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 16613 # number of overall misses -system.cpu.icache.overall_misses::total 16613 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 188398500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 188398500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 188398500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 188398500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 188398500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 188398500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 39401519 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 39401519 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 39401519 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 39401519 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 39401519 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 39401519 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000422 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000422 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000422 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000422 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000422 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000422 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 11340.426172 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 11340.426172 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 11340.426172 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 11340.426172 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 11340.426172 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 11340.426172 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1856.548325 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.906518 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.906518 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 39475406 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 39475406 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 39475406 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 39475406 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 39475406 # number of overall hits +system.cpu.icache.overall_hits::total 39475406 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 16589 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 16589 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 16589 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 16589 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 16589 # number of overall misses +system.cpu.icache.overall_misses::total 16589 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 174124000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 174124000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 174124000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 174124000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 174124000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 174124000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 39491995 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 39491995 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 39491995 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 39491995 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 39491995 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 39491995 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000420 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000420 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000420 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000420 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000420 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000420 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10496.353005 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 10496.353005 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 10496.353005 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 10496.353005 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 10496.353005 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 10496.353005 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -392,146 +550,146 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 789 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 789 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 789 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 789 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 789 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 789 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15824 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 15824 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 15824 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 15824 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 15824 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 15824 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 136475000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 136475000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 136475000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 136475000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 136475000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 136475000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000402 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000402 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000402 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000402 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000402 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000402 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8624.557634 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 8624.557634 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8624.557634 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 8624.557634 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8624.557634 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 8624.557634 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 733 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 733 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 733 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 733 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 733 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 733 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15856 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 15856 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 15856 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 15856 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 15856 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 15856 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 125938500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 125938500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 125938500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 125938500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 125938500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 125938500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000401 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000401 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000401 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000401 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000401 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000401 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7942.640010 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7942.640010 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7942.640010 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 7942.640010 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7942.640010 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 7942.640010 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1417 # number of replacements -system.cpu.dcache.tagsinuse 3115.188705 # Cycle average of tags in use -system.cpu.dcache.total_refs 172067508 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 4618 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 37260.179298 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1428 # number of replacements +system.cpu.dcache.tagsinuse 3114.448538 # Cycle average of tags in use +system.cpu.dcache.total_refs 172176390 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 4628 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 37203.195765 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3115.188705 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.760544 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.760544 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 90009194 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 90009194 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 82031517 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 82031517 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 13545 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 13545 # number of LoadLockedReq hits +system.cpu.dcache.occ_blocks::cpu.data 3114.448538 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.760363 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.760363 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 90117753 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 90117753 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 82031823 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 82031823 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 13562 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 13562 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 13252 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 13252 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 172040711 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 172040711 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 172040711 # number of overall hits -system.cpu.dcache.overall_hits::total 172040711 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 3936 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 3936 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 21143 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 21143 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 172149576 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 172149576 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 172149576 # number of overall hits +system.cpu.dcache.overall_hits::total 172149576 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 3920 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 3920 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 20837 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 20837 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 25079 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 25079 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 25079 # number of overall misses -system.cpu.dcache.overall_misses::total 25079 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 123444000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 123444000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 700240500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 700240500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 74000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 74000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 823684500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 823684500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 823684500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 823684500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 90013130 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 90013130 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 24757 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 24757 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 24757 # number of overall misses +system.cpu.dcache.overall_misses::total 24757 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 107051000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 107051000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 536036000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 536036000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 83000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 83000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 643087000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 643087000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 643087000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 643087000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 90121673 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 90121673 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052660 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052660 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13547 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 13547 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13564 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 13564 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 13252 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 13252 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 172065790 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 172065790 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 172065790 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 172065790 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000044 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000044 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000258 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000258 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000148 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000148 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000146 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000146 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000146 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000146 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31362.804878 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 31362.804878 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33119.259329 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33119.259329 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 37000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 37000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 32843.594242 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 32843.594242 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 32843.594242 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 32843.594242 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 172174333 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 172174333 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 172174333 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 172174333 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000043 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000043 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000254 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000254 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000147 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000147 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000144 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000144 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000144 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000144 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27308.928571 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 27308.928571 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25725.200365 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 25725.200365 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 41500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 41500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 25975.966393 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 25975.966393 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 25975.966393 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 25975.966393 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 626 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 365 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 16 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 12 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 39.125000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 30.416667 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1041 # number of writebacks -system.cpu.dcache.writebacks::total 1041 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2130 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2130 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18331 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 18331 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 1045 # number of writebacks +system.cpu.dcache.writebacks::total 1045 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2105 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2105 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18024 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 18024 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 20461 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 20461 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 20461 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 20461 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1806 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1806 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2812 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2812 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4618 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4618 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4618 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4618 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 58649500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 58649500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 107455500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 107455500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 166105000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 166105000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 166105000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 166105000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_hits::cpu.data 20129 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 20129 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 20129 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 20129 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1815 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1815 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2813 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2813 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4628 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4628 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4628 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4628 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 50564500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 50564500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84395500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 84395500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 134960000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 134960000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 134960000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 134960000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000020 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000020 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000034 # mshr miss rate for WriteReq accesses @@ -540,98 +698,98 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32474.806202 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 32474.806202 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38213.193457 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38213.193457 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35969.034214 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 35969.034214 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35969.034214 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 35969.034214 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27859.228650 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27859.228650 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30001.955208 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30001.955208 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29161.624892 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 29161.624892 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29161.624892 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 29161.624892 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 3978.553859 # Cycle average of tags in use -system.cpu.l2cache.total_refs 13166 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 5424 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.427360 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 3987.642168 # Cycle average of tags in use +system.cpu.l2cache.total_refs 13211 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 5425 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 2.435207 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 368.225876 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2798.824975 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 811.503008 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.011237 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.085413 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.024765 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.121416 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 12759 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 297 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 13056 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1041 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1041 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 17 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 17 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 12759 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 314 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 13073 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 12759 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 314 # number of overall hits -system.cpu.l2cache.overall_hits::total 13073 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3064 # number of ReadReq misses +system.cpu.l2cache.occ_blocks::writebacks 370.156310 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2800.588114 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 816.897744 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.011296 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.085467 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.024930 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.121693 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 12793 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 306 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 13099 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1045 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1045 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 20 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 20 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 12793 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 326 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 13119 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 12793 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 326 # number of overall hits +system.cpu.l2cache.overall_hits::total 13119 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3063 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 1508 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 4572 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 2796 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 2796 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3064 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 4304 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 7368 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3064 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 4304 # number of overall misses -system.cpu.l2cache.overall_misses::total 7368 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 107820500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 56418000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 164238500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 104584000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 104584000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 107820500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 161002000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 268822500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 107820500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 161002000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 268822500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 15823 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1805 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 17628 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 1041 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1041 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 2813 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 2813 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 15823 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 4618 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 20441 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 15823 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 4618 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 20441 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.193642 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.835457 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.259360 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.993957 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.993957 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.193642 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.932005 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.360452 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.193642 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.932005 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.360452 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35189.458225 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 37412.466844 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 35922.681540 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 37404.864092 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 37404.864092 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35189.458225 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 37407.527881 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 36485.138436 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35189.458225 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 37407.527881 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 36485.138436 # average overall miss latency +system.cpu.l2cache.ReadReq_misses::total 4571 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 2794 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 2794 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3063 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 4302 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 7365 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3063 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 4302 # number of overall misses +system.cpu.l2cache.overall_misses::total 7365 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 97211500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 48306000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 145517500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 81468500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 81468500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 97211500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 129774500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 226986000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 97211500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 129774500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 226986000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 15856 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1814 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 17670 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 1045 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1045 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 2814 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 2814 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 15856 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 4628 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 20484 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 15856 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 4628 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 20484 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.193176 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.831312 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.258687 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.992893 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.992893 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.193176 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.929559 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.359549 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.193176 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.929559 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.359549 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 31737.349004 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 32033.156499 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 31834.937650 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 29158.375089 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 29158.375089 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 31737.349004 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 30166.085542 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 30819.551935 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 31737.349004 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 30166.085542 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 30819.551935 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -640,59 +798,59 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 19 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 42 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 61 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 19 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 42 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 61 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 19 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 42 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 61 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 18 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 39 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 57 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 18 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 39 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 57 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 18 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 39 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 57 # number of overall MSHR hits system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3045 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1466 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 4511 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2796 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 2796 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1469 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 4514 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2794 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 2794 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 3045 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 4262 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 7307 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 4263 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 7308 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 3045 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 4262 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 7307 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 97703000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 50497000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 148200000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 95754500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 95754500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 97703000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 146251500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 243954500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 97703000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 146251500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 243954500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.192441 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.812188 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.255900 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.993957 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.993957 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.192441 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.922910 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.357468 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.192441 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922910 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.357468 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32086.371100 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 34445.429741 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32853.025937 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 34246.959943 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 34246.959943 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32086.371100 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34315.227593 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33386.410292 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32086.371100 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34315.227593 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33386.410292 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_misses::cpu.data 4263 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 7308 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 85814425 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 42422648 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 128237073 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 72139117 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 72139117 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 85814425 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 114561765 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 200376190 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 85814425 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 114561765 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 200376190 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.192041 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.809813 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.255461 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992893 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992893 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.192041 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.921132 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.356766 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.192041 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.921132 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.356766 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 28182.077176 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 28878.589517 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 28408.744572 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 25819.297423 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 25819.297423 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 28182.077176 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 26873.508093 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 27418.745211 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 28182.077176 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 26873.508093 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 27418.745211 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |