diff options
Diffstat (limited to 'tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt')
| -rw-r--r-- | tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt | 1411 |
1 files changed, 712 insertions, 699 deletions
diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index 94f7097ff..8a385b77d 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -1,46 +1,46 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.112557 # Number of seconds simulated -sim_ticks 112556618500 # Number of ticks simulated -final_tick 112556618500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.112686 # Number of seconds simulated +sim_ticks 112686104500 # Number of ticks simulated +final_tick 112686104500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 125639 # Simulator instruction rate (inst/s) -host_op_rate 150843 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 51793233 # Simulator tick rate (ticks/s) -host_mem_usage 327772 # Number of bytes of host memory used -host_seconds 2173.19 # Real time elapsed on the host +host_inst_rate 125538 # Simulator instruction rate (inst/s) +host_op_rate 150722 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 51811162 # Simulator tick rate (ticks/s) +host_mem_usage 327864 # Number of bytes of host memory used +host_seconds 2174.94 # Real time elapsed on the host sim_insts 273037220 # Number of instructions simulated sim_ops 327811602 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 187072 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 117696 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 162752 # Number of bytes read from this memory -system.physmem.bytes_read::total 467520 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 112896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 167936 # Number of bytes read from this memory +system.physmem.bytes_read::total 467904 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 187072 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 187072 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu.inst 2923 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1839 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 2543 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7305 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1662026 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1045660 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 1445957 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4153643 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1662026 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1662026 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1662026 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1045660 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 1445957 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4153643 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7305 # Number of read requests accepted +system.physmem.num_reads::cpu.data 1764 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 2624 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7311 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1660116 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1001863 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 1490299 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4152278 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1660116 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1660116 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1660116 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1001863 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 1490299 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4152278 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7311 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 7305 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 7311 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 467520 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 467904 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 467520 # Total read bytes from the system interface side +system.physmem.bytesReadSys 467904 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -51,16 +51,16 @@ system.physmem.perBankRdBursts::2 601 # Pe system.physmem.perBankRdBursts::3 520 # Per bank write bursts system.physmem.perBankRdBursts::4 444 # Per bank write bursts system.physmem.perBankRdBursts::5 346 # Per bank write bursts -system.physmem.perBankRdBursts::6 146 # Per bank write bursts -system.physmem.perBankRdBursts::7 247 # Per bank write bursts +system.physmem.perBankRdBursts::6 153 # Per bank write bursts +system.physmem.perBankRdBursts::7 252 # Per bank write bursts system.physmem.perBankRdBursts::8 219 # Per bank write bursts system.physmem.perBankRdBursts::9 290 # Per bank write bursts system.physmem.perBankRdBursts::10 315 # Per bank write bursts system.physmem.perBankRdBursts::11 411 # Per bank write bursts -system.physmem.perBankRdBursts::12 540 # Per bank write bursts +system.physmem.perBankRdBursts::12 547 # Per bank write bursts system.physmem.perBankRdBursts::13 678 # Per bank write bursts system.physmem.perBankRdBursts::14 615 # Per bank write bursts -system.physmem.perBankRdBursts::15 555 # Per bank write bursts +system.physmem.perBankRdBursts::15 542 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -79,14 +79,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 112556460000 # Total gap between requests +system.physmem.totGap 112685946000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 7305 # Read request sizes (log2) +system.physmem.readPktSize::6 7311 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -94,22 +94,22 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4013 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1460 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 489 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 289 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 237 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 191 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 168 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 137 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 186 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 52 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 26 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 20 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 17 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 16 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3986 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1457 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 456 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 293 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 235 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 200 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 175 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 198 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 151 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 66 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 30 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 20 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 17 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see @@ -190,26 +190,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1395 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 333.121147 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 192.861490 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 347.787983 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 501 35.91% 35.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 324 23.23% 59.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 138 9.89% 69.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 72 5.16% 74.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 60 4.30% 78.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 40 2.87% 81.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 25 1.79% 83.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 33 2.37% 85.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 202 14.48% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1395 # Bytes accessed per row activation -system.physmem.totQLat 103629565 # Total ticks spent queuing -system.physmem.totMemAccLat 240598315 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 36525000 # Total ticks spent in databus transfers -system.physmem.avgQLat 14186.11 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1367 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 340.646672 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 198.022122 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 348.529599 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 486 35.55% 35.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 298 21.80% 57.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 139 10.17% 67.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 76 5.56% 73.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 63 4.61% 77.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 51 3.73% 81.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 27 1.98% 83.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 26 1.90% 85.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 201 14.70% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1367 # Bytes accessed per row activation +system.physmem.totQLat 102208518 # Total ticks spent queuing +system.physmem.totMemAccLat 239289768 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 36555000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13980.10 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 32936.11 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 32730.10 # Average memory access latency per DRAM burst system.physmem.avgRdBW 4.15 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 4.15 # Average system read bandwidth in MiByte/s @@ -218,51 +218,51 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.37 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.49 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 5900 # Number of row buffer hits during reads +system.physmem.readRowHits 5935 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.77 # Row buffer hit rate for reads +system.physmem.readRowHitRate 81.18 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 15408139.63 # Average gap between requests -system.physmem.pageHitRate 80.77 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 4800600 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2619375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 28509000 # Energy for read commands per rank (pJ) +system.physmem.avgGap 15413205.58 # Average gap between requests +system.physmem.pageHitRate 81.18 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 4815720 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2627625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 28657200 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 7351234800 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3210095790 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 64714428750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 75311688315 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.136839 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 107655127862 # Time in different power states -system.physmem_0.memoryStateTime::REF 3758300000 # Time in different power states +system.physmem_0.refreshEnergy 7359880320 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 3231673425 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 64774920750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 75402575040 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.157389 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 107755851914 # Time in different power states +system.physmem_0.memoryStateTime::REF 3762720000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1137230638 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1164613086 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 5692680 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3106125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 28033200 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 5496120 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2998875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 28064400 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 7351234800 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 3321763065 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 64616466750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 75326296620 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.266714 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 107490739638 # Time in different power states -system.physmem_1.memoryStateTime::REF 3758300000 # Time in different power states +system.physmem_1.refreshEnergy 7359880320 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 3295137510 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 64719250500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 75410827725 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.230627 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 107661884129 # Time in different power states +system.physmem_1.memoryStateTime::REF 3762720000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1301464112 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1258279621 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 37745745 # Number of BP lookups -system.cpu.branchPred.condPredicted 20165036 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1746193 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 18664433 # Number of BTB lookups -system.cpu.branchPred.BTBHits 17299757 # Number of BTB hits +system.cpu.branchPred.lookups 37742989 # Number of BP lookups +system.cpu.branchPred.condPredicted 20164516 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1746156 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 18663196 # Number of BTB lookups +system.cpu.branchPred.BTBHits 17299233 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.688361 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 7225644 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 3815 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 92.691697 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 7223653 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 3816 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -381,129 +381,129 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 225113238 # number of cpu cycles simulated +system.cpu.numCycles 225372210 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 12251417 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 334051298 # Number of instructions fetch has processed -system.cpu.fetch.Branches 37745745 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 24525401 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 210778013 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3510671 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 1214 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.IcacheWaitRetryStallCycles 2374 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 89095174 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 21831 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 224788353 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.802613 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.228565 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 12439138 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 334051202 # Number of instructions fetch has processed +system.cpu.fetch.Branches 37742989 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 24522886 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 210855691 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 3510707 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 1284 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 2593 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 89092155 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 21708 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 225054059 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.800470 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.229417 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 51103569 22.73% 22.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 42898008 19.08% 41.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 30051948 13.37% 55.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 100734828 44.81% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 51374086 22.83% 22.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 42891136 19.06% 41.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 30054592 13.35% 55.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 100734245 44.76% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 224788353 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.167674 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.483926 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 27670582 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 63851253 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 108576447 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 23069494 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1620577 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 6880022 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 135197 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 363530011 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 6168132 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1620577 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 44985380 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 17900890 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 342489 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 113387887 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 46551130 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 355747905 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 2899336 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 6599141 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 195125 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 7751977 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 21225499 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 2892433 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 403402217 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2533894130 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 350207887 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 194891394 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 225054059 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.167470 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.482220 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 27837229 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 63912010 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 108618315 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 23065911 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1620594 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 6880048 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 135198 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 363546099 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 6169805 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1620594 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 45200014 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 17874059 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 342377 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 113380979 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 46636036 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 355768136 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 2890465 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 6610669 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 177931 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 7803674 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 21223053 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 2890533 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 403406015 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2534023592 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 350247327 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 194894263 # Number of floating rename lookups system.cpu.rename.CommittedMaps 372230051 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 31172166 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 17015 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 17024 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 55319848 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 92416628 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 88482470 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1658909 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1843123 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 353235356 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 28024 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 346405014 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 2300418 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 25451778 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 73600174 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 5904 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 224788353 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.541027 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.099686 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 31175964 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 17016 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 17025 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 55505783 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 92416404 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 88498336 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1661010 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1846418 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 353252226 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 28026 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 346438238 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 2301579 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 25468650 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 73725461 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 5906 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 225054059 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.539356 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.099855 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 40435382 17.99% 17.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 78271933 34.82% 52.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 61035531 27.15% 79.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 34789384 15.48% 95.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 9595504 4.27% 99.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 651863 0.29% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8756 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 40665072 18.07% 18.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 78300215 34.79% 52.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 60997700 27.10% 79.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 34882254 15.50% 95.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 9557051 4.25% 99.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 642945 0.29% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8822 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 224788353 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 225054059 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9471637 7.62% 7.62% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 7328 0.01% 7.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 7.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 7.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 7.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 7.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 257062 0.21% 7.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 126985 0.10% 7.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 92941 0.07% 8.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 68002 0.05% 8.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 719490 0.58% 8.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 316341 0.25% 8.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 682827 0.55% 9.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.45% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 53603507 43.13% 52.57% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 58947270 47.43% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9490410 7.63% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 7314 0.01% 7.64% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 7.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 7.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 7.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 7.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 255762 0.21% 7.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 126866 0.10% 7.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 93218 0.07% 8.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 68015 0.05% 8.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 721741 0.58% 8.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 297231 0.24% 8.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 683043 0.55% 9.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.44% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 53642366 43.14% 52.58% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 58960700 47.42% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 110656004 31.94% 31.94% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2148356 0.62% 32.56% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 110655140 31.94% 31.94% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2148362 0.62% 32.56% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 32.56% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 32.56% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 32.56% # Type of FU issued @@ -522,93 +522,93 @@ system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 32.56% # Ty system.cpu.iq.FU_type_0::SimdShift 0 0.00% 32.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 32.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 32.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 6798499 1.96% 34.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 34.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 8668326 2.50% 37.03% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 3332485 0.96% 37.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1592467 0.46% 38.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 20930113 6.04% 44.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 7182308 2.07% 46.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 7148959 2.06% 48.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 6798396 1.96% 34.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 34.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 8668155 2.50% 37.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 3332481 0.96% 37.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1592458 0.46% 38.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 20930094 6.04% 44.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 7182326 2.07% 46.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 7148962 2.06% 48.63% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 48.68% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 91886991 26.53% 75.21% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 85885220 24.79% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 91923219 26.53% 75.21% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 85883359 24.79% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 346405014 # Type of FU issued -system.cpu.iq.rate 1.538803 # Inst issue rate -system.cpu.iq.fu_busy_cnt 124293390 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.358809 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 756692141 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 251708637 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 223263072 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 287500048 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 127016707 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 117424886 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 303165485 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 167532919 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 5066153 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 346438238 # Type of FU issued +system.cpu.iq.rate 1.537183 # Inst issue rate +system.cpu.iq.fu_busy_cnt 124346666 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.358929 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 757024395 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 251740362 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 223260150 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 287554385 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 127018791 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 117424955 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 303230405 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 167554499 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 5064919 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6684353 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 13689 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 10190 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 6106853 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6684129 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 13573 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 10255 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 6122719 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 154467 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 567717 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 155303 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 607776 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1620577 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2121612 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 331103 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 353264247 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 1620594 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2118849 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 332046 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 353281117 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 92416628 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 88482470 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 16991 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 8045 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 337585 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 10190 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1220609 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 439082 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1659691 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 342414524 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 90667106 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3990490 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 92416404 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 88498336 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 16993 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 8049 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 338505 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 10255 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1220656 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 439058 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1659714 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 342448377 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 90703712 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3989861 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 867 # number of nop insts executed -system.cpu.iew.exec_refs 175256113 # number of memory reference insts executed -system.cpu.iew.exec_branches 31752933 # Number of branches executed -system.cpu.iew.exec_stores 84589007 # Number of stores executed -system.cpu.iew.exec_rate 1.521077 # Inst execution rate -system.cpu.iew.wb_sent 340946411 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 340687958 # cumulative count of insts written-back -system.cpu.iew.wb_producers 153730891 # num instructions producing a value -system.cpu.iew.wb_consumers 266895127 # num instructions consuming a value +system.cpu.iew.exec_nop 865 # number of nop insts executed +system.cpu.iew.exec_refs 175291126 # number of memory reference insts executed +system.cpu.iew.exec_branches 31752707 # Number of branches executed +system.cpu.iew.exec_stores 84587414 # Number of stores executed +system.cpu.iew.exec_rate 1.519479 # Inst execution rate +system.cpu.iew.wb_sent 340943800 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 340685105 # cumulative count of insts written-back +system.cpu.iew.wb_producers 153662327 # num instructions producing a value +system.cpu.iew.wb_consumers 266738216 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.513407 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.575997 # average fanout of values written-back +system.cpu.iew.wb_rate 1.511655 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.576079 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 23077429 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 23082519 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1611435 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 221063225 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.482889 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.052142 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1611397 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 221328864 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.481109 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.050764 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 87359166 39.52% 39.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 70369846 31.83% 71.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 20804571 9.41% 80.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 13442893 6.08% 86.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 8809424 3.99% 90.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 4514904 2.04% 92.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 2991184 1.35% 94.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 2424669 1.10% 95.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 10346568 4.68% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 87530154 39.55% 39.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 70479011 31.84% 71.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 20814829 9.40% 80.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 13433176 6.07% 86.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 8801116 3.98% 90.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 4514131 2.04% 92.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 2986629 1.35% 94.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 2449420 1.11% 95.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 10320398 4.66% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 221063225 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 221328864 # Number of insts commited each cycle system.cpu.commit.committedInsts 273037832 # Number of instructions committed system.cpu.commit.committedOps 327812214 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -654,154 +654,154 @@ system.cpu.commit.op_class_0::MemWrite 82375617 25.13% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 327812214 # Class of committed instruction -system.cpu.commit.bw_lim_events 10346568 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 561603777 # The number of ROB reads -system.cpu.rob.rob_writes 705508335 # The number of ROB writes -system.cpu.timesIdled 50687 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 324885 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 10320398 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 561900676 # The number of ROB reads +system.cpu.rob.rob_writes 705518580 # The number of ROB writes +system.cpu.timesIdled 50864 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 318151 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 273037220 # Number of Instructions Simulated system.cpu.committedOps 327811602 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.824478 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.824478 # CPI: Total CPI of All Threads -system.cpu.ipc 1.212888 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.212888 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 331301011 # number of integer regfile reads -system.cpu.int_regfile_writes 136940115 # number of integer regfile writes -system.cpu.fp_regfile_reads 187107432 # number of floating regfile reads -system.cpu.fp_regfile_writes 132177980 # number of floating regfile writes -system.cpu.cc_regfile_reads 1297030870 # number of cc regfile reads -system.cpu.cc_regfile_writes 80242369 # number of cc regfile writes -system.cpu.misc_regfile_reads 1182848919 # number of misc regfile reads +system.cpu.cpi 0.825427 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.825427 # CPI: Total CPI of All Threads +system.cpu.ipc 1.211495 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.211495 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 331331443 # number of integer regfile reads +system.cpu.int_regfile_writes 136939322 # number of integer regfile writes +system.cpu.fp_regfile_reads 187108010 # number of floating regfile reads +system.cpu.fp_regfile_writes 132178699 # number of floating regfile writes +system.cpu.cc_regfile_reads 1297132712 # number of cc regfile reads +system.cpu.cc_regfile_writes 80241070 # number of cc regfile writes +system.cpu.misc_regfile_reads 1183128145 # number of misc regfile reads system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes -system.cpu.dcache.tags.replacements 1533856 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.842901 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 163689178 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1534368 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 106.681825 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 84489000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.842901 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999693 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999693 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 1533845 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.844014 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 163642665 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1534357 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 106.652275 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 82317000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.844014 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999695 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999695 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 312 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 89 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 310 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 90 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 336633512 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 336633512 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 82631334 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 82631334 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 80965560 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 80965560 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 70478 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 70478 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 336636785 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 336636785 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 82609327 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 82609327 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 80941037 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 80941037 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 70495 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 70495 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 10909 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 10909 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 163596894 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 163596894 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 163667372 # number of overall hits -system.cpu.dcache.overall_hits::total 163667372 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2773234 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2773234 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1087139 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1087139 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 163550364 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 163550364 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 163620859 # number of overall hits +system.cpu.dcache.overall_hits::total 163620859 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2796866 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2796866 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1111662 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1111662 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 18 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 18 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 5 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 5 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 3860373 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3860373 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3860391 # number of overall misses -system.cpu.dcache.overall_misses::total 3860391 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 22353219965 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 22353219965 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8921439031 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8921439031 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 189750 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 189750 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 31274658996 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 31274658996 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 31274658996 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 31274658996 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 85404568 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 85404568 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 3908528 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3908528 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3908546 # number of overall misses +system.cpu.dcache.overall_misses::total 3908546 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 22404027000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 22404027000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8967503998 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8967503998 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 189000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 189000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 31371530998 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 31371530998 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 31371530998 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 31371530998 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 85406193 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 85406193 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052699 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052699 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 70496 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 70496 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 70513 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 70513 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10914 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 10914 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 167457267 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 167457267 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 167527763 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 167527763 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032472 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.032472 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013249 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.013249 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 167458892 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 167458892 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 167529405 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 167529405 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032748 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.032748 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013548 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.013548 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000255 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.000255 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000458 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000458 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.023053 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.023053 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.023043 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.023043 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 8060.343976 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 8060.343976 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8206.346227 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 8206.346227 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 37950 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 37950 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 8101.460402 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 8101.460402 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 8101.422627 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 8101.422627 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.023340 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.023340 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.023331 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.023331 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 8010.404145 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 8010.404145 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8066.754102 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 8066.754102 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 37800 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 37800 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 8026.431178 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 8026.431178 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 8026.394214 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 8026.394214 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 920181 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1059827 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 117395 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 134751 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 7.838332 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 7.865077 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 966341 # number of writebacks -system.cpu.dcache.writebacks::total 966341 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1459520 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1459520 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 866494 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 866494 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 966339 # number of writebacks +system.cpu.dcache.writebacks::total 966339 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1483173 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1483173 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 891007 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 891007 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 5 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2326014 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2326014 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2326014 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2326014 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1313714 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1313714 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 220645 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 220645 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 2374180 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2374180 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2374180 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2374180 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1313693 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1313693 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 220655 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 220655 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 11 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 11 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1534359 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1534359 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1534370 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1534370 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9970454284 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 9970454284 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1720952041 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1720952041 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 709000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 709000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11691406325 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11691406325 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11692115325 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11692115325 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 1534348 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1534348 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1534359 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1534359 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10622731000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10622731000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1827670779 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1827670779 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 681000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 681000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12450401779 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12450401779 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12451082779 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12451082779 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015382 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015382 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002689 # mshr miss rate for WriteReq accesses @@ -812,368 +812,381 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.009163 system.cpu.dcache.demand_mshr_miss_rate::total 0.009163 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.009159 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.009159 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7589.516656 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7589.516656 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 7799.642145 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 7799.642145 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 64454.545455 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 64454.545455 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 7619.733273 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 7619.733273 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 7620.140726 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 7620.140726 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8086.159399 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8086.159399 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8282.933897 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8282.933897 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61909.090909 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61909.090909 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8114.457593 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 8114.457593 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8114.843253 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 8114.843253 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 715712 # number of replacements -system.cpu.icache.tags.tagsinuse 511.827844 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 88374047 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 716224 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 123.388838 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 326692250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.827844 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999664 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999664 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 715634 # number of replacements +system.cpu.icache.tags.tagsinuse 511.830268 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 88370349 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 716146 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 123.397113 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 324802500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.830268 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999668 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999668 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 129 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 245 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 130 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 246 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 69 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 178906541 # Number of tag accesses -system.cpu.icache.tags.data_accesses 178906541 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 88374047 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 88374047 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 88374047 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 88374047 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 88374047 # number of overall hits -system.cpu.icache.overall_hits::total 88374047 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 721111 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 721111 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 721111 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 721111 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 721111 # number of overall misses -system.cpu.icache.overall_misses::total 721111 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 5974650710 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 5974650710 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 5974650710 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 5974650710 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 5974650710 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 5974650710 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 89095158 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 89095158 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 89095158 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 89095158 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 89095158 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 89095158 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008094 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.008094 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.008094 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.008094 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.008094 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.008094 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8285.341244 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 8285.341244 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 8285.341244 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 8285.341244 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 8285.341244 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 8285.341244 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 59670 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 95 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 2032 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 178900425 # Number of tag accesses +system.cpu.icache.tags.data_accesses 178900425 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 88370349 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 88370349 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 88370349 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 88370349 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 88370349 # number of overall hits +system.cpu.icache.overall_hits::total 88370349 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 721790 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 721790 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 721790 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 721790 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 721790 # number of overall misses +system.cpu.icache.overall_misses::total 721790 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 5973224944 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 5973224944 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 5973224944 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 5973224944 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 5973224944 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 5973224944 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 89092139 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 89092139 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 89092139 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 89092139 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 89092139 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 89092139 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008102 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.008102 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.008102 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.008102 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.008102 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.008102 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8275.571765 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 8275.571765 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 8275.571765 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 8275.571765 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 8275.571765 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 8275.571765 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 62134 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 94 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 2178 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 29.365157 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 31.666667 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 28.528007 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 31.333333 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4886 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 4886 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 4886 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 4886 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 4886 # 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number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 5193352944 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 5193352944 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008039 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008039 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008039 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.008039 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008039 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.008039 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7251.007636 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7251.007636 # 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number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 68370000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 181139000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 118983500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 300122500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 181139000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 118983500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 188993302 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 489115802 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.003648 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.003648 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004086 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.001199 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.002117 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004086 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.001199 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.003354 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.003354 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.004087 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.004087 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000779 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000779 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004087 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.001150 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.002083 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004087 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.001150 # 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average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61970.236059 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67450.963719 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64032.963516 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61970.236059 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67450.963719 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 6227.126919 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 13959.979507 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2029950 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2029950 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 966341 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 31609 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2029851 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 966339 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 1033895 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 31761 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 220643 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 220643 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1431544 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4035081 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 5466625 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45780416 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 160045376 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 205825792 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 32515 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3248545 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.009730 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.098161 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadExReq 220653 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 220653 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 716147 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1313704 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2122577 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4377763 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6500340 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45775424 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 160044544 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 205819968 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 32667 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 4531746 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.007009 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.083423 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3216936 99.03% 99.03% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 31609 0.97% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 4499985 99.30% 99.30% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 31761 0.70% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3248545 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2574809000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 2.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1075177011 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 4531746 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 3216331500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 2.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1074485469 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 1.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2301798469 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2301553965 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.0 # Layer utilization (%) -system.membus.trans_dist::ReadReq 6500 # Transaction distribution -system.membus.trans_dist::ReadResp 6500 # Transaction distribution +system.membus.trans_dist::ReadResp 6571 # Transaction distribution system.membus.trans_dist::UpgradeReq 1 # Transaction distribution system.membus.trans_dist::UpgradeResp 1 # Transaction distribution -system.membus.trans_dist::ReadExReq 805 # Transaction distribution -system.membus.trans_dist::ReadExResp 805 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14612 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 14612 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 467520 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 467520 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 740 # Transaction distribution +system.membus.trans_dist::ReadExResp 740 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 6571 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14624 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 14624 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 467904 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 467904 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 7306 # Request fanout histogram +system.membus.snoop_fanout::samples 7312 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 7306 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 7312 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 7306 # Request fanout histogram -system.membus.reqLayer0.occupancy 9226230 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 7312 # Request fanout histogram +system.membus.reqLayer0.occupancy 9348857 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 38266679 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 38261400 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |