diff options
Diffstat (limited to 'tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt')
| -rw-r--r-- | tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt | 284 |
1 files changed, 142 insertions, 142 deletions
diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt index ce6e736cb..bbdf06ba7 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt @@ -1,32 +1,32 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.525854 # Number of seconds simulated -sim_ticks 525854475000 # Number of ticks simulated -final_tick 525854475000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 525854423000 # Number of ticks simulated +final_tick 525854423000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 697015 # Simulator instruction rate (inst/s) -host_op_rate 891108 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1343878935 # Simulator tick rate (ticks/s) -host_mem_usage 238268 # Number of bytes of host memory used -host_seconds 391.30 # Real time elapsed on the host -sim_insts 272739291 # Number of instructions simulated -sim_ops 348687131 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 167040 # Number of bytes read from this memory +host_inst_rate 1009014 # Simulator instruction rate (inst/s) +host_op_rate 1289987 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1945426950 # Simulator tick rate (ticks/s) +host_mem_usage 241152 # Number of bytes of host memory used +host_seconds 270.30 # Real time elapsed on the host +sim_insts 272739283 # Number of instructions simulated +sim_ops 348687122 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 166976 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 270272 # Number of bytes read from this memory -system.physmem.bytes_read::total 437312 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 167040 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 167040 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 2610 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 437248 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 166976 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 166976 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 2609 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 4223 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6833 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 317654 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 6832 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 317533 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 513967 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 831622 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 317654 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 317654 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 317654 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 831500 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 317533 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 317533 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 317533 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 513967 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 831622 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 831500 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -70,73 +70,73 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 1051708950 # number of cpu cycles simulated +system.cpu.numCycles 1051708846 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 272739291 # Number of instructions committed -system.cpu.committedOps 348687131 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 279584925 # Number of integer alu accesses +system.cpu.committedInsts 272739283 # Number of instructions committed +system.cpu.committedOps 348687122 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 279584917 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses -system.cpu.num_func_calls 12433363 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 18087061 # number of instructions that are conditional controls -system.cpu.num_int_insts 279584925 # number of integer instructions +system.cpu.num_func_calls 12448615 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 18087060 # number of instructions that are conditional controls +system.cpu.num_int_insts 279584917 # number of integer instructions system.cpu.num_fp_insts 114216705 # number of float instructions -system.cpu.num_int_register_reads 2212913209 # number of times the integer registers were read -system.cpu.num_int_register_writes 251197915 # number of times the integer registers were written +system.cpu.num_int_register_reads 2212913168 # number of times the integer registers were read +system.cpu.num_int_register_writes 251197902 # number of times the integer registers were written system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written -system.cpu.num_mem_refs 177024357 # number of memory refs -system.cpu.num_load_insts 94648758 # Number of load instructions +system.cpu.num_mem_refs 177024356 # number of memory refs +system.cpu.num_load_insts 94648757 # Number of load instructions system.cpu.num_store_insts 82375599 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 1051708950 # Number of busy cycles +system.cpu.num_busy_cycles 1051708846 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 13796 # number of replacements -system.cpu.icache.tagsinuse 1765.984158 # Cycle average of tags in use -system.cpu.icache.total_refs 348644756 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1765.984191 # Cycle average of tags in use +system.cpu.icache.total_refs 348644747 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 15603 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 22344.725758 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 22344.725181 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1765.984158 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 1765.984191 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.862297 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.862297 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 348644756 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 348644756 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 348644756 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 348644756 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 348644756 # number of overall hits -system.cpu.icache.overall_hits::total 348644756 # number of overall hits +system.cpu.icache.ReadReq_hits::cpu.inst 348644747 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 348644747 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 348644747 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 348644747 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 348644747 # number of overall hits +system.cpu.icache.overall_hits::total 348644747 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 15603 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 15603 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 15603 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 15603 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 15603 # number of overall misses system.cpu.icache.overall_misses::total 15603 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 328062000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 328062000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 328062000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 328062000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 328062000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 328062000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 348660359 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 348660359 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 348660359 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 348660359 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 348660359 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 348660359 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 328020000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 328020000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 328020000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 328020000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 328020000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 328020000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 348660350 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 348660350 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 348660350 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 348660350 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 348660350 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 348660350 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000045 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000045 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000045 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000045 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000045 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21025.572005 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 21025.572005 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 21025.572005 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 21025.572005 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 21025.572005 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 21025.572005 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21022.880215 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 21022.880215 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 21022.880215 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 21022.880215 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 21022.880215 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 21022.880215 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -151,46 +151,46 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 15603 system.cpu.icache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 15603 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 15603 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281253000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 281253000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281253000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 281253000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281253000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 281253000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281211000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 281211000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281211000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 281211000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281211000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 281211000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000045 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18025.572005 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18025.572005 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18025.572005 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 18025.572005 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18025.572005 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 18025.572005 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18022.880215 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18022.880215 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18022.880215 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 18022.880215 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18022.880215 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 18022.880215 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 1332 # number of replacements -system.cpu.dcache.tagsinuse 3078.396238 # Cycle average of tags in use -system.cpu.dcache.total_refs 176641600 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 3078.396294 # Cycle average of tags in use +system.cpu.dcache.total_refs 176641599 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 4478 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 39446.538633 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 39446.538410 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3078.396238 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 3078.396294 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.751562 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.751562 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 94570005 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 94570005 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 94570004 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 94570004 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 82049805 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 82049805 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 176619810 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 176619810 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 176619810 # number of overall hits -system.cpu.dcache.overall_hits::total 176619810 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 176619809 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 176619809 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 176619809 # number of overall hits +system.cpu.dcache.overall_hits::total 176619809 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 1606 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 1606 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 2872 # number of WriteReq misses @@ -207,18 +207,18 @@ system.cpu.dcache.demand_miss_latency::cpu.data 240058000 system.cpu.dcache.demand_miss_latency::total 240058000 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 240058000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 240058000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 94571611 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 94571611 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 94571610 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 94571610 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 176624288 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 176624288 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 176624288 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 176624288 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 176624287 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 176624287 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 176624287 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 176624287 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000017 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000017 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000035 # miss rate for WriteReq accesses @@ -278,54 +278,54 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 50608.307280 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50608.307280 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 50608.307280 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 48 # number of replacements -system.cpu.l2cache.tagsinuse 3475.672922 # Cycle average of tags in use -system.cpu.l2cache.total_refs 13308 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 4883 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.725374 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.tagsinuse 3487.701804 # Cycle average of tags in use +system.cpu.l2cache.total_refs 13310 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 4882 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 2.726342 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 341.613272 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2402.300580 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 731.759070 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 341.613277 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2408.384377 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 737.704150 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.010425 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.073312 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.022332 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.106069 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 12993 # number of ReadReq hits +system.cpu.l2cache.occ_percent::cpu.inst 0.073498 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.022513 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.106436 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 12994 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 239 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 13232 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 13233 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 998 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 998 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 16 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 12993 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 12994 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 255 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 13248 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 12993 # 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