diff options
Diffstat (limited to 'tests/long/se/30.eon/ref/arm/linux')
| -rw-r--r-- | tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt | 1152 | ||||
| -rw-r--r-- | tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt | 1493 | ||||
| -rw-r--r-- | tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt | 160 | ||||
| -rw-r--r-- | tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt | 492 |
4 files changed, 1671 insertions, 1626 deletions
diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt index 0a05ac469..73979cce4 100644 --- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt @@ -1,560 +1,58 @@ ---------- Begin Simulation Statistics ---------- -final_tick 227445516000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -host_inst_rate 153700 # Simulator instruction rate (inst/s) -host_mem_usage 303376 # Number of bytes of host memory used -host_op_rate 196498 # Simulator op (including micro ops) rate (op/s) -host_seconds 1776.44 # Real time elapsed on the host -host_tick_rate 128034740 # Simulator tick rate (ticks/s) +sim_seconds 0.212377 # Number of seconds simulated +sim_ticks 212377413000 # Number of ticks simulated +final_tick 212377413000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 273037854 # Number of instructions simulated -sim_ops 349065592 # Number of ops (including micro ops) simulated -sim_seconds 0.227446 # Number of seconds simulated -sim_ticks 227445516000 # Number of ticks simulated +host_inst_rate 166098 # Simulator instruction rate (inst/s) +host_op_rate 199419 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 129195965 # Simulator tick rate (ticks/s) +host_mem_usage 326468 # Number of bytes of host memory used +host_seconds 1643.84 # Real time elapsed on the host +sim_insts 273037856 # Number of instructions simulated +sim_ops 327812213 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 83.362247 # BTB Hit Percentage -system.cpu.branchPred.BTBHits 16723894 # Number of BTB hits -system.cpu.branchPred.BTBLookups 20061712 # Number of BTB lookups -system.cpu.branchPred.RASInCorrect 121 # Number of incorrect RAS predictions. -system.cpu.branchPred.condIncorrect 1671536 # Number of conditional branches incorrect -system.cpu.branchPred.condPredicted 21059526 # Number of conditional branches predicted -system.cpu.branchPred.lookups 35363260 # Number of BP lookups -system.cpu.branchPred.usedRAS 6617396 # Number of times the RAS was used to get a target. -system.cpu.committedInsts 273037854 # Number of instructions committed -system.cpu.committedOps 349065592 # Number of ops (including micro ops) committed -system.cpu.cpi 1.666037 # CPI: cycles per instruction -system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 10895 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_hits::cpu.inst 10895 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits -system.cpu.dcache.ReadReq_accesses::cpu.inst 95145110 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 95145110 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 61749.740048 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 61749.740048 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 61620.734497 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61620.734497 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits::cpu.inst 95143025 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 95143025 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 128748208 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 128748208 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.000022 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses::cpu.inst 2085 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2085 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 424 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 424 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 102352040 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 102352040 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000017 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000017 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 1661 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1661 # number of ReadReq MSHR misses -system.cpu.dcache.StoreCondReq_accesses::cpu.inst 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_hits::cpu.inst 10895 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.WriteReq_accesses::cpu.inst 82052677 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68469.206380 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 68469.206380 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 68654.108392 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68654.108392 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits::cpu.inst 82047473 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 82047473 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 356313750 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 356313750 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.000063 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000063 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses::cpu.inst 5204 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5204 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 2344 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2344 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 196350750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 196350750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000035 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 2860 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2860 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses::cpu.inst 177197787 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 177197787 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66547.120044 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 66547.120044 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 66070.070781 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 66070.070781 # average overall mshr miss latency -system.cpu.dcache.demand_hits::cpu.inst 177190498 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 177190498 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency::cpu.inst 485061958 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 485061958 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate::cpu.inst 0.000041 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000041 # miss rate for demand accesses -system.cpu.dcache.demand_misses::cpu.inst 7289 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 7289 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits::cpu.inst 2768 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2768 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 298702790 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 298702790 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.000026 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000026 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses::cpu.inst 4521 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4521 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses::cpu.inst 177197787 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 177197787 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66547.120044 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 66547.120044 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 66070.070781 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 66070.070781 # average overall mshr miss latency -system.cpu.dcache.overall_hits::cpu.inst 177190498 # number of overall hits -system.cpu.dcache.overall_hits::total 177190498 # number of overall hits -system.cpu.dcache.overall_miss_latency::cpu.inst 485061958 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 485061958 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate::cpu.inst 0.000041 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000041 # miss rate for overall accesses -system.cpu.dcache.overall_misses::cpu.inst 7289 # number of overall misses -system.cpu.dcache.overall_misses::total 7289 # number of overall misses -system.cpu.dcache.overall_mshr_hits::cpu.inst 2768 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2768 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 298702790 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 298702790 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.000026 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000026 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses::cpu.inst 4521 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4521 # number of overall MSHR misses -system.cpu.dcache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 11 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 674 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 2436 # Occupied blocks per task id -system.cpu.dcache.tags.avg_refs 39197.586375 # Average number of references to valid blocks. -system.cpu.dcache.tags.data_accesses 354443675 # Number of data accesses -system.cpu.dcache.tags.occ_blocks::cpu.inst 3089.554835 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.754286 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.754286 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 3161 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.771729 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.replacements 1360 # number of replacements -system.cpu.dcache.tags.sampled_refs 4521 # Sample count of references to valid blocks. -system.cpu.dcache.tags.tag_accesses 354443675 # Number of tag accesses -system.cpu.dcache.tags.tagsinuse 3089.554835 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 177212288 # Total number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks::writebacks 1013 # number of writebacks -system.cpu.dcache.writebacks::total 1013 # number of writebacks -system.cpu.discardedOps 6932970 # Number of ops (including micro ops) which were discarded before commit -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.icache.ReadReq_accesses::cpu.inst 77471042 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 77471042 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17858.870336 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 17858.870336 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15825.006083 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15825.006083 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits::cpu.inst 77429612 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 77429612 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency::cpu.inst 739892998 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 739892998 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000535 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000535 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses::cpu.inst 41430 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 41430 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 655630002 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 655630002 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000535 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000535 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 41430 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 41430 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses::cpu.inst 77471042 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 77471042 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency::cpu.inst 17858.870336 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 17858.870336 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15825.006083 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 15825.006083 # average overall mshr miss latency -system.cpu.icache.demand_hits::cpu.inst 77429612 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 77429612 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency::cpu.inst 739892998 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 739892998 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate::cpu.inst 0.000535 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000535 # miss rate for demand accesses -system.cpu.icache.demand_misses::cpu.inst 41430 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 41430 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 655630002 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 655630002 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000535 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000535 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses::cpu.inst 41430 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 41430 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses::cpu.inst 77471042 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 77471042 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency::cpu.inst 17858.870336 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 17858.870336 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15825.006083 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 15825.006083 # average overall mshr miss latency -system.cpu.icache.overall_hits::cpu.inst 77429612 # number of overall hits -system.cpu.icache.overall_hits::total 77429612 # number of overall hits -system.cpu.icache.overall_miss_latency::cpu.inst 739892998 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 739892998 # number of overall miss cycles -system.cpu.icache.overall_miss_rate::cpu.inst 0.000535 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000535 # miss rate for overall accesses -system.cpu.icache.overall_misses::cpu.inst 41430 # number of overall misses -system.cpu.icache.overall_misses::total 41430 # number of overall misses -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 655630002 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 655630002 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000535 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000535 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses::cpu.inst 41430 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 41430 # number of overall MSHR misses -system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 87 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 33 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 288 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1478 # Occupied blocks per task id -system.cpu.icache.tags.avg_refs 1868.971300 # Average number of references to valid blocks. -system.cpu.icache.tags.data_accesses 154983513 # Number of data accesses -system.cpu.icache.tags.occ_blocks::cpu.inst 1927.026996 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.940931 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.940931 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1941 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.947754 # Percentage of cache occupancy per task id -system.cpu.icache.tags.replacements 39488 # number of replacements -system.cpu.icache.tags.sampled_refs 41429 # Sample count of references to valid blocks. -system.cpu.icache.tags.tag_accesses 154983513 # Number of tag accesses -system.cpu.icache.tags.tagsinuse 1927.026996 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 77429612 # Total number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.idleCycles 4029946 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.ipc 0.600227 # IPC: instructions per cycle -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 2860 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 2860 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 67967.563291 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67967.563291 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55399.173699 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55399.173699 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits::cpu.inst 16 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 193299750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 193299750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.994406 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.994406 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses::cpu.inst 2844 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 2844 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 157555250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 157555250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.994406 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994406 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 2844 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 2844 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses::cpu.inst 43091 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 43091 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68852.642487 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68852.642487 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56391.699770 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56391.699770 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits::cpu.inst 38266 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 38266 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 332214000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 332214000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.111972 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.111972 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses::cpu.inst 4825 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 4825 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 42 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 42 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 269721500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 269721500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.110998 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.110998 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4783 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 4783 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses::writebacks 1013 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1013 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits::writebacks 1013 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1013 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses::cpu.inst 45951 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 45951 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68524.416482 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68524.416482 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56021.600892 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56021.600892 # average overall mshr miss latency -system.cpu.l2cache.demand_hits::cpu.inst 38282 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 38282 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency::cpu.inst 525513750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 525513750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.166895 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.166895 # miss rate for demand accesses -system.cpu.l2cache.demand_misses::cpu.inst 7669 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 7669 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits::cpu.inst 42 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 42 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 427276750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 427276750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.165981 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.165981 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 7627 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 7627 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses::cpu.inst 45951 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 45951 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68524.416482 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68524.416482 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56021.600892 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56021.600892 # average overall mshr miss latency -system.cpu.l2cache.overall_hits::cpu.inst 38282 # number of overall hits -system.cpu.l2cache.overall_hits::total 38282 # number of overall hits -system.cpu.l2cache.overall_miss_latency::cpu.inst 525513750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 525513750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.166895 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.166895 # miss rate for overall accesses -system.cpu.l2cache.overall_misses::cpu.inst 7669 # number of overall misses -system.cpu.l2cache.overall_misses::total 7669 # number of overall misses -system.cpu.l2cache.overall_mshr_hits::cpu.inst 42 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 42 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 427276750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 427276750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.165981 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.165981 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 7627 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 7627 # number of overall MSHR misses -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 40 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1262 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4305 # Occupied blocks per task id -system.cpu.l2cache.tags.avg_refs 6.727368 # Average number of references to valid blocks. -system.cpu.l2cache.tags.data_accesses 384272 # Number of data accesses -system.cpu.l2cache.tags.occ_blocks::writebacks 356.812936 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3883.048925 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.010889 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.118501 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.129390 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 5700 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.173950 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.sampled_refs 5700 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.tag_accesses 384272 # Number of tag accesses -system.cpu.l2cache.tags.tagsinuse 4239.861860 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 38346 # Total number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.numCycles 454891032 # number of cpu cycles simulated -system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.tickCycles 450861086 # Number of cycles that the CPU actually ticked -system.cpu.toL2Bus.data_through_bus 3005632 # Total data (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 82859 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10055 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 92914 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 24495000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 62845998 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 7514710 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.throughput 13214734 # Throughput (bytes/s) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2651456 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 354176 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 3005632 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.trans_dist::ReadReq 43091 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 43090 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1013 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2860 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2860 # Transaction distribution -system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.membus.data_through_bus 488128 # Total data (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15254 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 15254 # Packet count per connected master and slave (bytes) -system.membus.reqLayer0.occupancy 8910000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 71341750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.throughput 2146132 # Throughput (bytes/s) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 488128 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 488128 # Cumulative packet size per connected master and slave (bytes) -system.membus.trans_dist::ReadReq 4783 # Transaction distribution -system.membus.trans_dist::ReadResp 4783 # Transaction distribution -system.membus.trans_dist::ReadExReq 2844 # Transaction distribution -system.membus.trans_dist::ReadExResp 2844 # Transaction distribution -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgGap 29821084.57 # Average gap between requests -system.physmem.avgMemAccLat 25580.41 # Average memory access latency per DRAM burst -system.physmem.avgQLat 6830.41 # Average queueing delay per DRAM burst -system.physmem.avgRdBW 2.15 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.15 # Average system read bandwidth in MiByte/s -system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s -system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.busUtil 0.02 # Data bus utilization in percentage -system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.bw_inst_read::cpu.inst 974721 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 974721 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 2146132 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2146132 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2146132 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2146132 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bytesPerActivate::samples 1544 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 315.689119 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 184.950751 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 330.584238 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 593 38.41% 38.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 326 21.11% 59.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 172 11.14% 70.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 76 4.92% 75.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 71 4.60% 80.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 58 3.76% 83.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 38 2.46% 86.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 28 1.81% 88.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 182 11.79% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1544 # Bytes accessed per row activation -system.physmem.bytesReadDRAM 488128 # Total number of bytes read from DRAM -system.physmem.bytesReadSys 488128 # Total read bytes from the system interface side +system.physmem.bytes_read::cpu.inst 485312 # Number of bytes read from this memory +system.physmem.bytes_read::total 485312 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 219008 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 219008 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 7583 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7583 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2285139 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2285139 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1031221 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1031221 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2285139 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2285139 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7583 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 7583 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 485312 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 485312 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side -system.physmem.bytes_inst_read::cpu.inst 221696 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 221696 # Number of instructions bytes read from this memory -system.physmem.bytes_read::cpu.inst 488128 # Number of bytes read from this memory -system.physmem.bytes_read::total 488128 # Number of bytes read from this memory -system.physmem.memoryStateTime::IDLE 217468466000 # Time in different power states -system.physmem.memoryStateTime::REF 7594860000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 2381096500 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.num_reads::cpu.inst 7627 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7627 # Number of read requests responded to by this memory -system.physmem.pageHitRate 79.70 # Row buffer hit rate, read and write combined -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.perBankRdBursts::0 637 # Per bank write bursts -system.physmem.perBankRdBursts::1 850 # Per bank write bursts -system.physmem.perBankRdBursts::2 633 # Per bank write bursts +system.physmem.perBankRdBursts::0 630 # Per bank write bursts +system.physmem.perBankRdBursts::1 843 # Per bank write bursts +system.physmem.perBankRdBursts::2 628 # Per bank write bursts system.physmem.perBankRdBursts::3 541 # Per bank write bursts -system.physmem.perBankRdBursts::4 470 # Per bank write bursts -system.physmem.perBankRdBursts::5 350 # Per bank write bursts -system.physmem.perBankRdBursts::6 175 # Per bank write bursts -system.physmem.perBankRdBursts::7 229 # Per bank write bursts -system.physmem.perBankRdBursts::8 210 # Per bank write bursts -system.physmem.perBankRdBursts::9 309 # Per bank write bursts -system.physmem.perBankRdBursts::10 346 # Per bank write bursts +system.physmem.perBankRdBursts::4 466 # Per bank write bursts +system.physmem.perBankRdBursts::5 349 # Per bank write bursts +system.physmem.perBankRdBursts::6 173 # Per bank write bursts +system.physmem.perBankRdBursts::7 228 # Per bank write bursts +system.physmem.perBankRdBursts::8 209 # Per bank write bursts +system.physmem.perBankRdBursts::9 310 # Per bank write bursts +system.physmem.perBankRdBursts::10 342 # Per bank write bursts system.physmem.perBankRdBursts::11 428 # Per bank write bursts -system.physmem.perBankRdBursts::12 552 # Per bank write bursts -system.physmem.perBankRdBursts::13 714 # Per bank write bursts -system.physmem.perBankRdBursts::14 639 # Per bank write bursts -system.physmem.perBankRdBursts::15 544 # Per bank write bursts +system.physmem.perBankRdBursts::12 554 # Per bank write bursts +system.physmem.perBankRdBursts::13 705 # Per bank write bursts +system.physmem.perBankRdBursts::14 637 # Per bank write bursts +system.physmem.perBankRdBursts::15 540 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -571,9 +69,26 @@ system.physmem.perBankWrBursts::12 0 # Pe system.physmem.perBankWrBursts::13 0 # Per bank write bursts system.physmem.perBankWrBursts::14 0 # Per bank write bursts system.physmem.perBankWrBursts::15 0 # Per bank write bursts -system.physmem.rdQLenPdf::0 6680 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 887 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 60 # What read queue length does an incoming req see +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 212377186000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 7583 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 6625 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 897 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 61 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -603,22 +118,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.readBursts 7627 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 7627 # Read request sizes (log2) -system.physmem.readReqs 7627 # Number of read requests accepted -system.physmem.readRowHitRate 79.70 # Row buffer hit rate for reads -system.physmem.readRowHits 6079 # Number of row buffer hits during reads -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.physmem.totBusLat 38135000 # Total ticks spent in databus transfers -system.physmem.totGap 227445412000 # Total gap between requests -system.physmem.totMemAccLat 195101750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totQLat 52095500 # Total ticks spent queuing system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -683,17 +182,518 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.bytesPerActivate::samples 1498 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 322.691589 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 189.527839 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 333.553355 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 554 36.98% 36.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 333 22.23% 59.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 160 10.68% 69.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 67 4.47% 74.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 72 4.81% 79.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 61 4.07% 83.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 43 2.87% 86.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 33 2.20% 88.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 175 11.68% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1498 # Bytes accessed per row activation +system.physmem.totQLat 52122500 # Total ticks spent queuing +system.physmem.totMemAccLat 194303750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 37915000 # Total ticks spent in databus transfers +system.physmem.avgQLat 6873.60 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 25623.60 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.29 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.29 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 0.02 # Data bus utilization in percentage +system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 6077 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.voltage_domain.voltage 1 # Voltage in Volts +system.physmem.readRowHitRate 80.14 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 28007013.85 # Average gap between requests +system.physmem.pageHitRate 80.14 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 202838268250 # Time in different power states +system.physmem.memoryStateTime::REF 7091500000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 2441586750 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.membus.throughput 2285139 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 4730 # Transaction distribution +system.membus.trans_dist::ReadResp 4730 # Transaction distribution +system.membus.trans_dist::ReadExReq 2853 # Transaction distribution +system.membus.trans_dist::ReadExResp 2853 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15166 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 15166 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485312 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 485312 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 485312 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 8812000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 70869000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.branchPred.lookups 33146135 # Number of BP lookups +system.cpu.branchPred.condPredicted 17115100 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1582628 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 18038083 # Number of BTB lookups +system.cpu.branchPred.BTBHits 15622031 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 86.605827 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 6627212 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 191 # Number of system calls +system.cpu.numCycles 424754826 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 273037856 # Number of instructions committed +system.cpu.committedOps 327812213 # Number of ops (including micro ops) committed +system.cpu.discardedOps 4318160 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching +system.cpu.cpi 1.555663 # CPI: cycles per instruction +system.cpu.ipc 0.642813 # IPC: instructions per cycle +system.cpu.tickCycles 420995897 # Number of cycles that the object actually ticked +system.cpu.idleCycles 3758929 # Total number of cycles that the object has spent stopped +system.cpu.icache.tags.replacements 36952 # number of replacements +system.cpu.icache.tags.tagsinuse 1924.941242 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 73208047 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 38889 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1882.487259 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1924.941242 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.939913 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.939913 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1937 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 83 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 33 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 275 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1488 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.945801 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 146532763 # Number of tag accesses +system.cpu.icache.tags.data_accesses 146532763 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 73208047 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 73208047 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 73208047 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 73208047 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 73208047 # 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Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2869 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2869 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 77779 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10029 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 87808 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2488896 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 353216 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 2842112 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 2842112 # 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Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3844.644919 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.010788 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.117329 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.128117 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 5644 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 42 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1251 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4259 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.172241 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 363785 # 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average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68066.771819 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68527.045633 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 68527.045633 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68527.045633 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 68527.045633 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # 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number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 7583 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 7583 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 7583 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 7583 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 266719500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 266719500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 158382000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 158382000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 425101500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 425101500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 425101500 # 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average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56388.900634 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55514.195584 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55514.195584 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56059.804827 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56059.804827 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56059.804827 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56059.804827 # average overall mshr miss latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.tags.replacements 1353 # number of replacements +system.cpu.dcache.tags.tagsinuse 3085.890933 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168774540 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 4510 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37422.292683 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.inst 3085.890933 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.753391 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.753391 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 3157 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 20 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 671 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 2433 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.770752 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 337568172 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 337568172 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 86705299 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 86705299 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.inst 82047451 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 82047451 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.inst 10895 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.inst 10895 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.inst 168752750 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168752750 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.inst 168752750 # number of overall hits +system.cpu.dcache.overall_hits::total 168752750 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.inst 2065 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2065 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.inst 5226 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5226 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.inst 7291 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 7291 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.inst 7291 # number of overall misses +system.cpu.dcache.overall_misses::total 7291 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 127204208 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 127204208 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 358851000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 358851000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 486055208 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 486055208 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 486055208 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 486055208 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.inst 86707364 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 86707364 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.inst 82052677 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 10895 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.inst 10895 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.inst 168760041 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 168760041 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 168760041 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 168760041 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.000024 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000024 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.000064 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000064 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.inst 0.000043 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.inst 0.000043 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 61600.100726 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 61600.100726 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68666.475316 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 68666.475316 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66665.095049 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 66665.095049 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66665.095049 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 66665.095049 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 1009 # number of writebacks +system.cpu.dcache.writebacks::total 1009 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 424 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 424 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 2357 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2357 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.inst 2781 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2781 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.inst 2781 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2781 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 1641 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1641 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 2869 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2869 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.inst 4510 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4510 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.inst 4510 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4510 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 100713040 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 100713040 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 197262500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 197262500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 297975540 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 297975540 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 297975540 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 297975540 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000019 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000035 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 61372.967703 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61372.967703 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 68756.535378 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68756.535378 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 66069.964523 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 66069.964523 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 66069.964523 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 66069.964523 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index dff7f3d85..6d48708ce 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -1,61 +1,61 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.064767 # Number of seconds simulated -sim_ticks 64766858000 # Number of ticks simulated -final_tick 64766858000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.058843 # Number of seconds simulated +sim_ticks 58842982000 # Number of ticks simulated +final_tick 58842982000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 139181 # Simulator instruction rate (inst/s) -host_op_rate 177937 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 33015138 # Simulator tick rate (ticks/s) -host_mem_usage 270440 # Number of bytes of host memory used -host_seconds 1961.73 # Real time elapsed on the host -sim_insts 273036725 # Number of instructions simulated -sim_ops 349064449 # Number of ops (including micro ops) simulated +host_inst_rate 157851 # Simulator instruction rate (inst/s) +host_op_rate 189517 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 34018873 # Simulator tick rate (ticks/s) +host_mem_usage 327492 # Number of bytes of host memory used +host_seconds 1729.72 # Real time elapsed on the host +sim_insts 273036656 # Number of instructions simulated +sim_ops 327810999 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 194688 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 272960 # Number of bytes read from this memory -system.physmem.bytes_read::total 467648 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 194688 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 194688 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3042 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 4265 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7307 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 3005982 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 4214501 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 7220483 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 3005982 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 3005982 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 3005982 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4214501 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7220483 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7307 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 189376 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 272128 # Number of bytes read from this memory +system.physmem.bytes_read::total 461504 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 189376 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 189376 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 2959 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 4252 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7211 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 3218328 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 4624647 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 7842974 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 3218328 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 3218328 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 3218328 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4624647 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7842974 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7211 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 7307 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 7211 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 467648 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 461504 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 467648 # Total read bytes from the system interface side +system.physmem.bytesReadSys 461504 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 3 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 604 # Per bank write bursts -system.physmem.perBankRdBursts::1 805 # Per bank write bursts -system.physmem.perBankRdBursts::2 608 # Per bank write bursts -system.physmem.perBankRdBursts::3 526 # Per bank write bursts -system.physmem.perBankRdBursts::4 446 # Per bank write bursts -system.physmem.perBankRdBursts::5 361 # Per bank write bursts -system.physmem.perBankRdBursts::6 162 # Per bank write bursts -system.physmem.perBankRdBursts::7 221 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 11 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 592 # Per bank write bursts +system.physmem.perBankRdBursts::1 792 # Per bank write bursts +system.physmem.perBankRdBursts::2 603 # Per bank write bursts +system.physmem.perBankRdBursts::3 519 # Per bank write bursts +system.physmem.perBankRdBursts::4 437 # Per bank write bursts +system.physmem.perBankRdBursts::5 342 # Per bank write bursts +system.physmem.perBankRdBursts::6 159 # Per bank write bursts +system.physmem.perBankRdBursts::7 228 # Per bank write bursts system.physmem.perBankRdBursts::8 208 # Per bank write bursts -system.physmem.perBankRdBursts::9 290 # Per bank write bursts -system.physmem.perBankRdBursts::10 326 # Per bank write bursts -system.physmem.perBankRdBursts::11 415 # Per bank write bursts -system.physmem.perBankRdBursts::12 530 # Per bank write bursts -system.physmem.perBankRdBursts::13 688 # Per bank write bursts -system.physmem.perBankRdBursts::14 613 # Per bank write bursts +system.physmem.perBankRdBursts::9 292 # Per bank write bursts +system.physmem.perBankRdBursts::10 317 # Per bank write bursts +system.physmem.perBankRdBursts::11 409 # Per bank write bursts +system.physmem.perBankRdBursts::12 526 # Per bank write bursts +system.physmem.perBankRdBursts::13 671 # Per bank write bursts +system.physmem.perBankRdBursts::14 612 # Per bank write bursts system.physmem.perBankRdBursts::15 504 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 64766656000 # Total gap between requests +system.physmem.totGap 58842848000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 7307 # Read request sizes (log2) +system.physmem.readPktSize::6 7211 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,11 +90,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4265 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2120 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 623 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 229 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 69 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4240 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2012 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 646 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 244 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 68 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -186,29 +186,29 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1462 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 319.430917 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 186.825713 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 340.055999 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 519 35.50% 35.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 381 26.06% 61.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 138 9.44% 71.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 81 5.54% 76.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 49 3.35% 79.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 41 2.80% 82.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 27 1.85% 84.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 24 1.64% 86.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 202 13.82% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1462 # Bytes accessed per row activation -system.physmem.totQLat 61897500 # Total ticks spent queuing -system.physmem.totMemAccLat 198903750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 36535000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8470.99 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1405 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 327.288256 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 191.332764 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 342.731237 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 492 35.02% 35.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 350 24.91% 59.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 132 9.40% 69.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 82 5.84% 75.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 53 3.77% 78.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 47 3.35% 82.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 27 1.92% 84.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 22 1.57% 85.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 200 14.23% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1405 # Bytes accessed per row activation +system.physmem.totQLat 59614750 # Total ticks spent queuing +system.physmem.totMemAccLat 194821000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 36055000 # Total ticks spent in databus transfers +system.physmem.avgQLat 8267.20 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27220.99 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 7.22 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 27017.20 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 7.84 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 7.22 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 7.84 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage @@ -216,44 +216,44 @@ system.physmem.busUtilRead 0.06 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.12 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 5841 # Number of row buffer hits during reads +system.physmem.readRowHits 5798 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.94 # Row buffer hit rate for reads +system.physmem.readRowHitRate 80.40 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 8863645.27 # Average gap between requests -system.physmem.pageHitRate 79.94 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 60826618500 # Time in different power states -system.physmem.memoryStateTime::REF 2162680000 # Time in different power states +system.physmem.avgGap 8160150.88 # Average gap between requests +system.physmem.pageHitRate 80.40 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 55121576750 # Time in different power states +system.physmem.memoryStateTime::REF 1964820000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 1777002750 # Time in different power states +system.physmem.memoryStateTime::ACT 1754568250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 7220483 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 4488 # Transaction distribution -system.membus.trans_dist::ReadResp 4488 # Transaction distribution -system.membus.trans_dist::UpgradeReq 3 # Transaction distribution -system.membus.trans_dist::UpgradeResp 3 # Transaction distribution -system.membus.trans_dist::ReadExReq 2819 # Transaction distribution -system.membus.trans_dist::ReadExResp 2819 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14620 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 14620 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 467648 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 467648 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 467648 # Total data (bytes) +system.membus.throughput 7842974 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 4381 # Transaction distribution +system.membus.trans_dist::ReadResp 4381 # Transaction distribution +system.membus.trans_dist::UpgradeReq 11 # Transaction distribution +system.membus.trans_dist::UpgradeResp 11 # Transaction distribution +system.membus.trans_dist::ReadExReq 2830 # Transaction distribution +system.membus.trans_dist::ReadExResp 2830 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14444 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 14444 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 461504 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 461504 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 461504 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 8747000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 8714000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 67869997 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 67059990 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 36489443 # Number of BP lookups -system.cpu.branchPred.condPredicted 21873029 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1677086 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 19094793 # Number of BTB lookups -system.cpu.branchPred.BTBHits 17269038 # Number of BTB hits +system.cpu.branchPred.lookups 36678579 # Number of BP lookups +system.cpu.branchPred.condPredicted 19369962 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1628976 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 19217639 # Number of BTB lookups +system.cpu.branchPred.BTBHits 17291098 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 90.438467 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 7051020 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 13969 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 89.975142 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 7036393 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 5252 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -339,516 +339,519 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 129533717 # number of cpu cycles simulated +system.cpu.numCycles 117685965 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 40065447 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 327212599 # Number of instructions fetch has processed -system.cpu.fetch.Branches 36489443 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 24320058 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 72959266 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 8220576 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 9614052 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 94 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1657 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 76 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 38688978 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 553522 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 129167933 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.246487 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.483221 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 40172132 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 329927106 # Number of instructions fetch has processed +system.cpu.fetch.Branches 36678579 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 24327491 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 75600101 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 3327960 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 175 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 2800 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 41 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 38768855 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 530996 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 117439229 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.389931 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.437439 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 56843632 44.01% 44.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 6961373 5.39% 49.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 5946764 4.60% 54.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 6307392 4.88% 58.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 5037669 3.90% 62.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4117601 3.19% 65.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3252291 2.52% 68.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 4297115 3.33% 71.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 36404096 28.18% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 46731814 39.79% 39.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 7329854 6.24% 46.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 6574514 5.60% 51.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 6398088 5.45% 57.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4252484 3.62% 60.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 5520861 4.70% 65.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3987559 3.40% 68.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3254311 2.77% 71.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 33389744 28.43% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 129167933 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.281698 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.526081 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 43040295 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 8294549 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 70704377 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 671384 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 6457328 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 7532389 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 70819 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 413867422 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 226829 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 6457328 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 45867800 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 237018 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 350499 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 68547941 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 7707347 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 406294876 # Number of instructions processed by rename +system.cpu.fetch.rateDist::total 117439229 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.311665 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.803453 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 34271331 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 16148849 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 61039844 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 4384832 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1594373 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 7530126 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 70364 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 389722126 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 437543 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1594373 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37031203 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 5569218 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 387986 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 62601924 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 10254525 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 382340457 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 36 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2372159 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1808118 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 3023073 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 35743 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 447044512 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2837901709 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1622364142 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 210216215 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 384566193 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 62478319 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 12155 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 12154 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 14556867 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 106022236 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 93881214 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 5184446 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5926802 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 394612578 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 23007 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 378124394 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 2730874 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 45321613 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 166213653 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 887 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 129167933 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.927386 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.138502 # Number of insts issued each cycle +system.cpu.rename.IQFullEvents 4583661 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 2043172 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 2989050 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 65700 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 432935056 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2729953830 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 376601971 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 209126886 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 372229219 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 60705837 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 14453 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 15060 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 19856485 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 96101144 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 93882304 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 9920575 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 10878783 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 370378331 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 25182 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 358744041 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1234352 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 42331510 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 132428138 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 3062 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 117439229 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 3.054721 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.223263 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 23289729 18.03% 18.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 17219322 13.33% 31.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 17000952 13.16% 44.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 16863081 13.06% 57.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 22471092 17.40% 74.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15547625 12.04% 87.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 10749417 8.32% 95.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 4018790 3.11% 98.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2007925 1.55% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 21274018 18.11% 18.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 14280801 12.16% 30.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 14869023 12.66% 42.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 13830819 11.78% 54.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 20620243 17.56% 72.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15076681 12.84% 85.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 10030176 8.54% 93.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 4472440 3.81% 97.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2985028 2.54% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 129167933 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 117439229 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 70479 0.37% 0.37% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 4864 0.03% 0.39% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 116556 0.60% 1.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 10208 0.05% 1.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 2498 0.01% 1.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 3 0.00% 1.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 192000 1.00% 2.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 6622 0.03% 2.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 104426 0.54% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 10354293 53.72% 56.35% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 8412591 43.65% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 30566 0.13% 0.13% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5035 0.02% 0.15% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.15% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.15% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.15% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.15% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.15% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.15% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.15% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 218902 0.91% 1.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 207576 0.86% 1.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 15328 0.06% 1.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 1824 0.01% 1.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 338916 1.41% 3.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 30886 0.13% 3.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 130712 0.54% 4.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.07% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 13684069 56.78% 60.84% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 9438097 39.16% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 127925021 33.83% 33.83% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2175908 0.58% 34.41% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.41% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.41% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.41% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.41% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.41% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.41% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 6 0.00% 34.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 6792348 1.80% 36.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 8524841 2.25% 38.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 3465145 0.92% 39.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1600581 0.42% 39.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 21035851 5.56% 45.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 7175261 1.90% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 7134800 1.89% 49.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 175287 0.05% 49.19% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 103072110 27.26% 76.45% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 89047235 23.55% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 114997382 32.06% 32.06% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2177572 0.61% 32.66% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 32.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 32.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 32.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 32.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 32.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 32.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 32.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 32.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 32.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 32.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 32.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 32.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 32.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 32.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 32.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 32.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 32.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 32.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 6789188 1.89% 34.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 34.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 8562613 2.39% 36.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 3491505 0.97% 37.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1605361 0.45% 38.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 21185799 5.91% 44.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 7196318 2.01% 46.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 7147739 1.99% 48.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 183217 0.05% 48.32% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 95472748 26.61% 74.93% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 89934599 25.07% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 378124394 # Type of FU issued -system.cpu.iq.rate 2.919119 # Inst issue rate -system.cpu.iq.fu_busy_cnt 19274540 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.050974 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 653351237 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 300092831 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 252502629 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 254070898 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 139884609 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 118704168 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 266903131 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 130495803 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 12681428 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 358744041 # Type of FU issued +system.cpu.iq.rate 3.048316 # Inst issue rate +system.cpu.iq.fu_busy_cnt 24101911 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.067184 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 600140343 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 274631052 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 231134438 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 260123231 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 138160310 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 119811956 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 246702850 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 136143102 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 13691987 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 11373488 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 85866 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 20564 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 11505631 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 10368919 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 114059 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 68397 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 11506726 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 299397 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 2800 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 1395971 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 850 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 6457328 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 4758 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 17342 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 394637253 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 715920 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 106022236 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 93881214 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 11972 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 602 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 17793 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 20564 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1298443 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 381522 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1679965 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 373834206 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 101210545 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 4290188 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1594373 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 4558099 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 129859 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 370404619 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1080086 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 96101144 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 93882304 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 14149 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 21825 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 109033 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 68397 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1241378 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 435662 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1677040 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 354745077 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 94263609 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3998964 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1668 # number of nop insts executed -system.cpu.iew.exec_refs 189079864 # number of memory reference insts executed -system.cpu.iew.exec_branches 32211788 # Number of branches executed -system.cpu.iew.exec_stores 87869319 # Number of stores executed -system.cpu.iew.exec_rate 2.885999 # Inst execution rate -system.cpu.iew.wb_sent 372104883 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 371206797 # cumulative count of insts written-back -system.cpu.iew.wb_producers 194146455 # num instructions producing a value -system.cpu.iew.wb_consumers 400678068 # num instructions consuming a value +system.cpu.iew.exec_nop 1106 # number of nop insts executed +system.cpu.iew.exec_refs 182843438 # number of memory reference insts executed +system.cpu.iew.exec_branches 32405794 # Number of branches executed +system.cpu.iew.exec_stores 88579829 # Number of stores executed +system.cpu.iew.exec_rate 3.014336 # Inst execution rate +system.cpu.iew.wb_sent 352024494 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 350946394 # cumulative count of insts written-back +system.cpu.iew.wb_producers 175212964 # num instructions producing a value +system.cpu.iew.wb_consumers 355804607 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.865716 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.484545 # average fanout of values written-back +system.cpu.iew.wb_rate 2.982058 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.492442 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 45577363 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 42598489 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1607073 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 122710605 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.844620 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.797026 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1559369 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 111323846 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.944667 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.904010 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 31366686 25.56% 25.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 25118346 20.47% 46.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 12977285 10.58% 56.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 10004590 8.15% 64.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 11874018 9.68% 74.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 6164142 5.02% 79.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 4197962 3.42% 82.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3586787 2.92% 85.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 17420789 14.20% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 29334492 26.35% 26.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 21002495 18.87% 45.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 12438899 11.17% 56.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8843852 7.94% 64.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 8943359 8.03% 72.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 5286497 4.75% 77.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 3580965 3.22% 80.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3438245 3.09% 83.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 18455042 16.58% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 122710605 # Number of insts commited each cycle -system.cpu.commit.committedInsts 273037337 # Number of instructions committed -system.cpu.commit.committedOps 349065061 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 111323846 # Number of insts commited each cycle +system.cpu.commit.committedInsts 273037268 # Number of instructions committed +system.cpu.commit.committedOps 327811611 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 177024331 # Number of memory references committed -system.cpu.commit.loads 94648748 # Number of loads committed +system.cpu.commit.refs 168107803 # Number of memory references committed +system.cpu.commit.loads 85732225 # Number of loads committed system.cpu.commit.membars 11033 # Number of memory barriers committed -system.cpu.commit.branches 30563497 # Number of branches committed +system.cpu.commit.branches 30563485 # Number of branches committed system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions. -system.cpu.commit.int_insts 279584611 # Number of committed integer instructions. +system.cpu.commit.int_insts 258331174 # Number of committed integer instructions. system.cpu.commit.function_calls 6225112 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 116648967 33.42% 33.42% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 2145845 0.61% 34.03% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 34.03% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 0 0.00% 34.03% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 34.03% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 34.03% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 34.03% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 34.03% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 34.03% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 34.03% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 34.03% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 34.03% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 34.03% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 34.03% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 34.03% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 34.03% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 34.03% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 34.03% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 34.03% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 34.03% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 6594343 1.89% 35.92% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 35.92% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 7943502 2.28% 38.20% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 3118180 0.89% 39.09% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 1563217 0.45% 39.54% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 19652356 5.63% 45.17% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 7136937 2.04% 47.21% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 7062098 2.02% 49.24% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 175285 0.05% 49.29% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 94648748 27.11% 76.40% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 82375583 23.60% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 104312045 31.82% 31.82% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 2145845 0.65% 32.48% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 32.48% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 32.48% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 32.48% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 32.48% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 32.48% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 32.48% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 32.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 32.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 32.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 32.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 32.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 32.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 32.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 32.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 32.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 32.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 32.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 32.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 6594343 2.01% 34.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 34.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 7943502 2.42% 36.91% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 3118180 0.95% 37.86% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 1563217 0.48% 38.34% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 19652356 6.00% 44.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 7136937 2.18% 46.51% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 175285 0.05% 48.72% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 85732225 26.15% 74.87% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 82375578 25.13% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 349065061 # Class of committed instruction -system.cpu.commit.bw_lim_events 17420789 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 327811611 # Class of committed instruction +system.cpu.commit.bw_lim_events 18455042 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 499929717 # The number of ROB reads -system.cpu.rob.rob_writes 795751266 # The number of ROB writes -system.cpu.timesIdled 6646 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 365784 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 273036725 # Number of Instructions Simulated -system.cpu.committedOps 349064449 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.474419 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.474419 # CPI: Total CPI of All Threads -system.cpu.ipc 2.107843 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.107843 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1785673756 # number of integer regfile reads -system.cpu.int_regfile_writes 235086257 # number of integer regfile writes -system.cpu.fp_regfile_reads 188627632 # number of floating regfile reads -system.cpu.fp_regfile_writes 133402932 # number of floating regfile writes -system.cpu.misc_regfile_reads 1210936846 # number of misc regfile reads +system.cpu.rob.rob_reads 463276381 # The number of ROB reads +system.cpu.rob.rob_writes 746948197 # The number of ROB writes +system.cpu.timesIdled 5570 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 246736 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 273036656 # Number of Instructions Simulated +system.cpu.committedOps 327810999 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.431026 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.431026 # CPI: Total CPI of All Threads +system.cpu.ipc 2.320044 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.320044 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 344698387 # number of integer regfile reads +system.cpu.int_regfile_writes 141985623 # number of integer regfile writes +system.cpu.fp_regfile_reads 189510679 # number of floating regfile reads +system.cpu.fp_regfile_writes 134618624 # number of floating regfile writes +system.cpu.cc_regfile_reads 1340695625 # number of cc regfile reads +system.cpu.cc_regfile_writes 80827327 # number of cc regfile writes +system.cpu.misc_regfile_reads 1216328122 # number of misc regfile reads system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes -system.cpu.toL2Bus.throughput 21331404 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 17706 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 17706 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1042 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 3 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 3 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2839 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2839 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 31825 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10310 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 42135 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1018304 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 363072 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 1381376 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 1381376 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 192 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 11837000 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 23209157 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 17471 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 17471 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1022 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 12 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 12 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2846 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2846 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 31432 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10234 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 41666 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1005376 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 359424 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 1364800 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 1364800 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 896 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 11697999 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 24407489 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 24104992 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 7420712 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 7380470 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 14019 # number of replacements -system.cpu.icache.tags.tagsinuse 1852.281625 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 38671572 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 15912 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 2430.340121 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 13841 # number of replacements +system.cpu.icache.tags.tagsinuse 1830.861112 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 38751311 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 15711 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 2466.508243 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1852.281625 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.904434 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.904434 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1893 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 1830.861112 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.893975 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.893975 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1870 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 208 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1526 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.924316 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 77393866 # Number of tag accesses -system.cpu.icache.tags.data_accesses 77393866 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 38671572 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 38671572 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 38671572 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 38671572 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 38671572 # number of overall hits -system.cpu.icache.overall_hits::total 38671572 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 17404 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 17404 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 17404 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 17404 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 17404 # number of overall misses -system.cpu.icache.overall_misses::total 17404 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 452089736 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 452089736 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 452089736 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 452089736 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 452089736 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 452089736 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 38688976 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 38688976 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 38688976 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 38688976 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 38688976 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 38688976 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000450 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000450 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000450 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000450 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000450 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000450 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25976.197196 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 25976.197196 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 25976.197196 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 25976.197196 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 25976.197196 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 25976.197196 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1041 # number of cycles access was blocked +system.cpu.icache.tags.age_task_id_blocks_1024::2 194 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1522 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.913086 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 77553427 # Number of tag accesses +system.cpu.icache.tags.data_accesses 77553427 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 38751328 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 38751328 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 38751328 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 38751328 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 38751328 # number of overall hits +system.cpu.icache.overall_hits::total 38751328 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 17524 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 17524 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 17524 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 17524 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 17524 # number of overall misses +system.cpu.icache.overall_misses::total 17524 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 439561740 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 439561740 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 439561740 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 439561740 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 439561740 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 439561740 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 38768852 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 38768852 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 38768852 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 38768852 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 38768852 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 38768852 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000452 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000452 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000452 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000452 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000452 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000452 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25083.413604 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 25083.413604 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 25083.413604 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 25083.413604 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 25083.413604 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 25083.413604 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 684 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 22 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 47.318182 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 57 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1490 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1490 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1490 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1490 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1490 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1490 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15914 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 15914 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 15914 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 15914 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 15914 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 15914 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 359079759 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 359079759 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 359079759 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 359079759 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 359079759 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 359079759 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000411 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000411 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000411 # 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number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 11 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 41 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 52 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 11 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 41 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 52 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 11 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 41 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 52 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3042 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1446 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 4488 # 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number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 254781750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 430471000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.191188 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.806920 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.253516 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992955 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992955 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.191188 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.920967 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.355710 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.191188 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.920967 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.355710 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57754.520053 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61704.875519 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59027.295009 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58728.804541 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58728.804541 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57754.520053 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59737.807737 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58912.139045 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57754.520053 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59737.807737 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58912.139045 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 8 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 40 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 48 # 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number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 112009 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 167488250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 167488250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 169394250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 254195250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 423589500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 169394250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 254195250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 423589500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.188363 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.813501 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.250960 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.916667 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.916667 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994378 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994378 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.188363 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.925555 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.355169 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.188363 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.925555 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.355169 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57247.127408 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60975.386779 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58457.258617 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10182.636364 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10182.636364 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59183.127208 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59183.127208 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57247.127408 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59782.514111 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58742.130079 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57247.127408 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59782.514111 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58742.130079 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1426 # number of replacements -system.cpu.dcache.tags.tagsinuse 3109.599416 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 170089338 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 4631 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 36728.425394 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 1384 # number of replacements +system.cpu.dcache.tags.tagsinuse 3114.575432 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 161730326 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 4594 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 35204.685677 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3109.599416 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.759180 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.759180 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 3205 # Occupied blocks per task id +system.cpu.dcache.tags.occ_blocks::cpu.data 3114.575432 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.760394 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.760394 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 3210 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 36 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 688 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 27 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 686 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 2446 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.782471 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 340235219 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 340235219 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 88036573 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 88036573 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 82030829 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 82030829 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 11027 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 11027 # number of LoadLockedReq hits +system.cpu.dcache.tags.age_task_id_blocks_1024::4 2462 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.783691 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 323517792 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 323517792 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 79590771 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 79590771 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 82030417 # 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number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 25968 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 25968 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 25968 # number of overall misses -system.cpu.dcache.overall_misses::total 25968 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 240617705 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 240617705 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1280155018 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1280155018 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 26302 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 26302 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 26342 # number of overall misses +system.cpu.dcache.overall_misses::total 26342 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 234715222 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 234715222 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1291834537 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1291834537 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 170250 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 170250 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1520772723 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1520772723 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1520772723 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1520772723 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 88040705 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 88040705 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 82052665 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 82052665 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11029 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 11029 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 1526549759 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1526549759 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1526549759 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1526549759 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 79594830 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 79594830 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 82052660 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 82052660 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 87085 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 87085 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11129 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 11129 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 170093370 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 170093370 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 170093370 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 170093370 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000047 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000047 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000266 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000266 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000181 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000181 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000153 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000153 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000153 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000153 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58232.745644 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 58232.745644 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 58625.893845 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 58625.893845 # average WriteReq miss latency +system.cpu.dcache.demand_accesses::cpu.data 161647490 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 161647490 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 161734575 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 161734575 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000051 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000051 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000271 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000271 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000459 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.000459 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000180 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000180 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000163 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000163 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000163 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000163 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 57825.873861 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 57825.873861 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 58078.251000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 58078.251000 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 85125 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 85125 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 58563.336530 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 58563.336530 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 58563.336530 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 58563.336530 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 30153 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1162 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 553 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 12 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 54.526221 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 96.833333 # average number of cycles each access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 58039.303437 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 58039.303437 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 57951.171475 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 57951.171475 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 32404 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1444 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 548 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 14 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 59.131387 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 103.142857 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1042 # number of writebacks -system.cpu.dcache.writebacks::total 1042 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2339 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2339 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18995 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 18995 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 1022 # number of writebacks +system.cpu.dcache.writebacks::total 1022 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2332 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2332 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 19388 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 19388 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 21334 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 21334 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 21334 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 21334 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1793 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1793 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2841 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2841 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4634 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4634 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4634 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4634 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 115097041 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 115097041 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 203424247 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 203424247 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 318521288 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 318521288 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 318521288 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 318521288 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000020 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000020 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_hits::cpu.data 21720 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 21720 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 21720 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 21720 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1727 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1727 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2855 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2855 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 24 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 24 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4582 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4582 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4606 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4606 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 109924790 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 109924790 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 205574740 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 205574740 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1745000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1745000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 315499530 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 315499530 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 317244530 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 317244530 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000022 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 64192.437814 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 64192.437814 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71603.043647 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71603.043647 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68735.711696 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 68735.711696 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68735.711696 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 68735.711696 # average overall mshr miss latency +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000276 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000276 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000028 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000028 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000028 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000028 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 63650.718008 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 63650.718008 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72005.162872 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72005.162872 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 72708.333333 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 72708.333333 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68856.292012 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 68856.292012 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68876.363439 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 68876.363439 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt index edb370512..d78fd5112 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt @@ -1,42 +1,42 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.212344 # Number of seconds simulated -sim_ticks 212344043000 # Number of ticks simulated -final_tick 212344043000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.201717 # Number of seconds simulated +sim_ticks 201717313500 # Number of ticks simulated +final_tick 201717313500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1152169 # Simulator instruction rate (inst/s) -host_op_rate 1472992 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 896053064 # Simulator tick rate (ticks/s) -host_mem_usage 309060 # Number of bytes of host memory used -host_seconds 236.98 # Real time elapsed on the host -sim_insts 273037663 # Number of instructions simulated -sim_ops 349065399 # Number of ops (including micro ops) simulated +host_inst_rate 1169681 # Simulator instruction rate (inst/s) +host_op_rate 1404332 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 864148101 # Simulator tick rate (ticks/s) +host_mem_usage 314684 # Number of bytes of host memory used +host_seconds 233.43 # Real time elapsed on the host +sim_insts 273037594 # Number of instructions simulated +sim_ops 327811949 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 1394641404 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 480709268 # Number of bytes read from this memory -system.physmem.bytes_read::total 1875350672 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1394641404 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1394641404 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 400047783 # Number of bytes written to this memory -system.physmem.bytes_written::total 400047783 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 348660351 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 94582505 # Number of read requests responded to by this memory -system.physmem.num_reads::total 443242856 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 82063572 # Number of write requests responded to by this memory -system.physmem.num_writes::total 82063572 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 6567838609 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2263822715 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 8831661324 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 6567838609 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 6567838609 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1883960470 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1883960470 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 6567838609 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4147783185 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 10715621794 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 10715621794 # Throughput (bytes/s) -system.membus.data_through_bus 2275398455 # Total data (bytes) +system.physmem.bytes_read::cpu.inst 1394641092 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 480709216 # Number of bytes read from this memory +system.physmem.bytes_read::total 1875350308 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1394641092 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1394641092 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 400047763 # Number of bytes written to this memory +system.physmem.bytes_written::total 400047763 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 348660273 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 86300511 # Number of read requests responded to by this memory +system.physmem.num_reads::total 434960784 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 82063567 # Number of write requests responded to by this memory +system.physmem.num_writes::total 82063567 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 6913839312 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2383083572 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 9296922884 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 6913839312 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 6913839312 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1983209850 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1983209850 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 6913839312 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4366293422 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 11280132734 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 11280132734 # Throughput (bytes/s) +system.membus.data_through_bus 2275398071 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits @@ -124,63 +124,65 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 424688087 # number of cpu cycles simulated +system.cpu.numCycles 403434628 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 273037663 # Number of instructions committed -system.cpu.committedOps 349065399 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 279584918 # Number of integer alu accesses +system.cpu.committedInsts 273037594 # Number of instructions committed +system.cpu.committedOps 327811949 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 258331481 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses system.cpu.num_func_calls 12448615 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 18105897 # number of instructions that are conditional controls -system.cpu.num_int_insts 279584918 # number of integer instructions +system.cpu.num_conditional_control_insts 15799338 # number of instructions that are conditional controls +system.cpu.num_int_insts 258331481 # number of integer instructions system.cpu.num_fp_insts 114216705 # number of float instructions -system.cpu.num_int_register_reads 2254222459 # number of times the integer registers were read -system.cpu.num_int_register_writes 251197905 # number of times the integer registers were written +system.cpu.num_int_register_reads 1174407516 # number of times the integer registers were read +system.cpu.num_int_register_writes 162499657 # number of times the integer registers were written system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written -system.cpu.num_mem_refs 177024356 # number of memory refs -system.cpu.num_load_insts 94648757 # Number of load instructions -system.cpu.num_store_insts 82375599 # Number of store instructions +system.cpu.num_cc_register_reads 985884623 # number of times the CC registers were read +system.cpu.num_cc_register_writes 76361749 # number of times the CC registers were written +system.cpu.num_mem_refs 168107829 # number of memory refs +system.cpu.num_load_insts 85732235 # Number of load instructions +system.cpu.num_store_insts 82375594 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 424688087 # Number of busy cycles +system.cpu.num_busy_cycles 403434628 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 30563502 # Number of branches fetched +system.cpu.Branches 30563490 # Number of branches fetched system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 116649415 33.42% 33.42% # Class of executed instruction -system.cpu.op_class::IntMult 2145905 0.61% 34.03% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 6594343 1.89% 35.92% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 35.92% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 7943502 2.28% 38.20% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 3118180 0.89% 39.09% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 1563217 0.45% 39.54% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 19652356 5.63% 45.17% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 7136937 2.04% 47.21% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 7062098 2.02% 49.24% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 175285 0.05% 49.29% # Class of executed instruction -system.cpu.op_class::MemRead 94648757 27.11% 76.40% # Class of executed instruction -system.cpu.op_class::MemWrite 82375599 23.60% 100.00% # Class of executed instruction +system.cpu.op_class::IntAlu 104312492 31.82% 31.82% # Class of executed instruction +system.cpu.op_class::IntMult 2145905 0.65% 32.48% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 6594343 2.01% 34.49% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 34.49% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 7943502 2.42% 36.91% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 3118180 0.95% 37.86% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 1563217 0.48% 38.34% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 19652356 6.00% 44.33% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 7136937 2.18% 46.51% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 175285 0.05% 48.72% # Class of executed instruction +system.cpu.op_class::MemRead 85732235 26.15% 74.87% # Class of executed instruction +system.cpu.op_class::MemWrite 82375594 25.13% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 349065594 # Class of executed instruction +system.cpu.op_class::total 327812144 # Class of executed instruction ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt index 23ba68f1d..57cca8ea4 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.525834 # Number of seconds simulated -sim_ticks 525834342000 # Number of ticks simulated -final_tick 525834342000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.517235 # Number of seconds simulated +sim_ticks 517235411000 # Number of ticks simulated +final_tick 517235411000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 605985 # Simulator instruction rate (inst/s) -host_op_rate 774729 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1168322503 # Simulator tick rate (ticks/s) -host_mem_usage 318808 # Number of bytes of host memory used -host_seconds 450.08 # Real time elapsed on the host -sim_insts 272739283 # Number of instructions simulated -sim_ops 348687122 # Number of ops (including micro ops) simulated +host_inst_rate 749544 # Simulator instruction rate (inst/s) +host_op_rate 899855 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1421469107 # Simulator tick rate (ticks/s) +host_mem_usage 324416 # Number of bytes of host memory used +host_seconds 363.87 # Real time elapsed on the host +sim_insts 272739285 # Number of instructions simulated +sim_ops 327433743 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 166976 # Number of bytes read from this memory @@ -21,15 +21,15 @@ system.physmem.bytes_inst_read::total 166976 # Nu system.physmem.num_reads::cpu.inst 2609 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 4223 # Number of read requests responded to by this memory system.physmem.num_reads::total 6832 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 317545 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 513987 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 831532 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 317545 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 317545 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 317545 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 513987 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 831532 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 831532 # Throughput (bytes/s) +system.physmem.bw_read::cpu.inst 322824 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 522532 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 845356 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 322824 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 322824 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 322824 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 522532 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 845356 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 845356 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 3976 # Transaction distribution system.membus.trans_dist::ReadResp 3976 # Transaction distribution system.membus.trans_dist::ReadExReq 2856 # Transaction distribution @@ -40,9 +40,9 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 437248 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 437248 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 6832000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 7260000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 61488000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 61915000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits @@ -130,73 +130,75 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 1051668684 # number of cpu cycles simulated +system.cpu.numCycles 1034470822 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 272739283 # Number of instructions committed -system.cpu.committedOps 348687122 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 279584917 # Number of integer alu accesses +system.cpu.committedInsts 272739285 # Number of instructions committed +system.cpu.committedOps 327433743 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 258331537 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses system.cpu.num_func_calls 12448615 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 18105896 # number of instructions that are conditional controls -system.cpu.num_int_insts 279584917 # number of integer instructions +system.cpu.num_conditional_control_insts 15799349 # number of instructions that are conditional controls +system.cpu.num_int_insts 258331537 # number of integer instructions system.cpu.num_fp_insts 114216705 # number of float instructions -system.cpu.num_int_register_reads 2579483474 # number of times the integer registers were read -system.cpu.num_int_register_writes 251197902 # number of times the integer registers were written +system.cpu.num_int_register_reads 1215888421 # number of times the integer registers were read +system.cpu.num_int_register_writes 162499693 # number of times the integer registers were written system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written -system.cpu.num_mem_refs 177024356 # number of memory refs -system.cpu.num_load_insts 94648757 # Number of load instructions +system.cpu.num_cc_register_reads 1242915500 # number of times the CC registers were read +system.cpu.num_cc_register_writes 76361814 # number of times the CC registers were written +system.cpu.num_mem_refs 168107847 # number of memory refs +system.cpu.num_load_insts 85732248 # Number of load instructions system.cpu.num_store_insts 82375599 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 1051668684 # Number of busy cycles +system.cpu.num_busy_cycles 1034470822 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 30563501 # Number of branches fetched +system.cpu.Branches 30563502 # Number of branches fetched system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 116649413 33.42% 33.42% # Class of executed instruction -system.cpu.op_class::IntMult 2145905 0.61% 34.03% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 34.03% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 6594343 1.89% 35.92% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 35.92% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 7943502 2.28% 38.20% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 3118180 0.89% 39.09% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 1563217 0.45% 39.54% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 19652356 5.63% 45.17% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 7136937 2.04% 47.21% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 7062098 2.02% 49.24% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 175285 0.05% 49.29% # Class of executed instruction -system.cpu.op_class::MemRead 94648757 27.11% 76.40% # Class of executed instruction -system.cpu.op_class::MemWrite 82375599 23.60% 100.00% # Class of executed instruction +system.cpu.op_class::IntAlu 104312543 31.82% 31.82% # Class of executed instruction +system.cpu.op_class::IntMult 2145905 0.65% 32.48% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 6594343 2.01% 34.49% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 34.49% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 7943502 2.42% 36.91% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 3118180 0.95% 37.86% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 1563217 0.48% 38.34% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 19652356 6.00% 44.33% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 7136937 2.18% 46.51% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 175285 0.05% 48.72% # Class of executed instruction +system.cpu.op_class::MemRead 85732248 26.15% 74.87% # Class of executed instruction +system.cpu.op_class::MemWrite 82375599 25.13% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 349065592 # Class of executed instruction +system.cpu.op_class::total 327812213 # Class of executed instruction system.cpu.icache.tags.replacements 13796 # number of replacements -system.cpu.icache.tags.tagsinuse 1765.993223 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 348644747 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1766.007645 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 348644749 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 15603 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 22344.725181 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 22344.725309 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1765.993223 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.862301 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.862301 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1766.007645 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.862308 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.862308 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1807 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id @@ -204,44 +206,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 26 system.cpu.icache.tags.age_task_id_blocks_1024::3 161 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1524 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.882324 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 697336303 # Number of tag accesses -system.cpu.icache.tags.data_accesses 697336303 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 348644747 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 348644747 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 348644747 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 348644747 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 348644747 # number of overall hits -system.cpu.icache.overall_hits::total 348644747 # number of overall hits +system.cpu.icache.tags.tag_accesses 697336307 # Number of tag accesses +system.cpu.icache.tags.data_accesses 697336307 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 348644749 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 348644749 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 348644749 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 348644749 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 348644749 # number of overall hits +system.cpu.icache.overall_hits::total 348644749 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 15603 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 15603 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 15603 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 15603 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 15603 # number of overall misses system.cpu.icache.overall_misses::total 15603 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 312417000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 312417000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 312417000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 312417000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 312417000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 312417000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 348660350 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 348660350 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 348660350 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 348660350 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 348660350 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 348660350 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 312527500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 312527500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 312527500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 312527500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 312527500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 312527500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 348660352 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 348660352 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 348660352 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 348660352 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 348660352 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 348660352 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000045 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000045 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000045 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000045 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000045 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20022.880215 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 20022.880215 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 20022.880215 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 20022.880215 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 20022.880215 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 20022.880215 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20029.962187 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 20029.962187 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 20029.962187 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 20029.962187 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 20029.962187 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 20029.962187 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -256,38 +258,38 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 15603 system.cpu.icache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 15603 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 15603 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281211000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 281211000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281211000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 281211000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281211000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 281211000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281321500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 281321500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281321500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 281321500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281321500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 281321500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000045 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18022.880215 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18022.880215 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18022.880215 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 18022.880215 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18022.880215 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 18022.880215 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18029.962187 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18029.962187 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18029.962187 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 18029.962187 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18029.962187 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 18029.962187 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 3487.723791 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 3487.764987 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 13310 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 4882 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 2.726342 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 341.616093 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2408.399470 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 737.708228 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.010425 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 341.623056 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2408.427143 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 737.714788 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.010426 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073499 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.022513 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.106437 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.106438 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 4882 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 46 # Occupied blocks per task id @@ -321,17 +323,17 @@ system.cpu.l2cache.demand_misses::total 6832 # nu system.cpu.l2cache.overall_misses::cpu.inst 2609 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 4223 # number of overall misses system.cpu.l2cache.overall_misses::total 6832 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 135668000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 71084000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 206752000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 148512000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 148512000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 135668000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 219596000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 355264000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 135668000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 219596000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 355264000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 135778500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 71271000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 207049500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 148649500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 148649500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 135778500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 219920500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 355699000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 135778500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 219920500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 355699000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 15603 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 1606 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 17209 # number of ReadReq accesses(hits+misses) @@ -356,17 +358,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.340222 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.167211 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.943055 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.340222 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52042.353392 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52136.795903 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52074.823944 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52048.144258 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52048.144258 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52042.353392 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52076.841108 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52063.670960 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52042.353392 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52076.841108 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52063.670960 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -386,17 +388,17 @@ system.cpu.l2cache.demand_mshr_misses::total 6832 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2609 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 4223 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 6832 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 104360000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 104365000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54680000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 159040000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 114240000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 114240000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 104360000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 168920000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 273280000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 104360000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 168920000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 273280000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 159045000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 114243000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 114243000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 104365000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 168923000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 273288000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 104365000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 168923000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 273288000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.167211 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.851183 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.231042 # mshr miss rate for ReadReq accesses @@ -408,92 +410,100 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.340222 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.167211 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943055 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.340222 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40001.916443 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40001.257545 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40001.050420 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40001.050420 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40001.916443 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.710395 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40001.170960 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40001.916443 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.710395 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40001.170960 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 1332 # number of replacements -system.cpu.dcache.tags.tagsinuse 3078.412981 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 176641599 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 3078.445016 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168359617 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4478 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 39446.538410 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37597.056052 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3078.412981 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.751566 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.751566 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 3078.445016 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.751573 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.751573 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3146 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 11 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 10 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 677 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 2428 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.768066 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 353296632 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 353296632 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 94570004 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 94570004 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 336732670 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 336732670 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 86233963 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 86233963 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 82049805 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 82049805 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 54059 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 54059 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 176619809 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 176619809 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 176619809 # number of overall hits -system.cpu.dcache.overall_hits::total 176619809 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1606 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1606 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 168283768 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168283768 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168337827 # number of overall hits +system.cpu.dcache.overall_hits::total 168337827 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1604 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1604 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 2872 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 2872 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 4478 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4478 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 4478 # number of overall misses -system.cpu.dcache.overall_misses::total 4478 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 78292000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 78292000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 157288000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 157288000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 235580000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 235580000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 235580000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 235580000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 94571610 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 94571610 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_misses::cpu.data 3 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 3 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 4476 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4476 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 4479 # number of overall misses +system.cpu.dcache.overall_misses::total 4479 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 78354000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 78354000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 157425500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 157425500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 235779500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 235779500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 235779500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 235779500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 86235567 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 86235567 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 54062 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 54062 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 176624287 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 176624287 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 176624287 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 176624287 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000017 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000017 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 168288244 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 168288244 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 168342306 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 168342306 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000019 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000019 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000035 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.000035 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48749.688667 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 48749.688667 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54766.016713 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 54766.016713 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 52608.307280 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 52608.307280 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 52608.307280 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 52608.307280 # average overall miss latency +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000055 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.000055 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000027 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000027 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000027 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000027 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48849.127182 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 48849.127182 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54813.892758 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54813.892758 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 52676.385165 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 52676.385165 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 52641.102925 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 52641.102925 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -504,40 +514,54 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 998 # number of writebacks system.cpu.dcache.writebacks::total 998 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1606 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1606 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1603 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1603 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2872 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 2872 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4478 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4478 # number of demand (read+write) MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4475 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4475 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4478 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4478 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75080000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 75080000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 151544000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 151544000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 226624000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 226624000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 226624000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 226624000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000017 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000017 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75108000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 75108000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 151681500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 151681500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 159000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 159000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 226789500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 226789500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 226948500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 226948500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46749.688667 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46749.688667 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52766.016713 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52766.016713 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50608.307280 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 50608.307280 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50608.307280 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 50608.307280 # average overall mshr miss latency +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000055 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000055 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46854.647536 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46854.647536 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52813.892758 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52813.892758 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50679.217877 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 50679.217877 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50680.772666 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 50680.772666 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 2565553 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 2608205 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 17209 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 17209 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 998 # Transaction distribution |