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-rw-r--r--tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini1
-rwxr-xr-xtests/long/se/30.eon/ref/arm/linux/o3-timing/simout6
-rw-r--r--tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt14
3 files changed, 10 insertions, 11 deletions
diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini
index c6c5b71d8..dd0636ebe 100644
--- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini
@@ -86,6 +86,7 @@ max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=false
numIQEntries=64
+numPhysCCRegs=0
numPhysFloatRegs=256
numPhysIntRegs=256
numROBEntries=192
diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout
index d9d67c53c..d3e872fc3 100755
--- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout
@@ -1,10 +1,8 @@
-Redirecting stdout to build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing/simout
-Redirecting stderr to build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 22 2013 07:58:15
-gem5 started Sep 22 2013 08:27:24
+gem5 compiled Oct 16 2013 01:36:42
+gem5 started Oct 16 2013 02:05:47
gem5 executing on zizzer
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
index cfe46b65a..8bc1d638d 100644
--- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.068375 # Nu
sim_ticks 68375005500 # Number of ticks simulated
final_tick 68375005500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 121198 # Simulator instruction rate (inst/s)
-host_op_rate 154946 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 30350947 # Simulator tick rate (ticks/s)
-host_mem_usage 251080 # Number of bytes of host memory used
-host_seconds 2252.81 # Real time elapsed on the host
+host_inst_rate 143200 # Simulator instruction rate (inst/s)
+host_op_rate 183074 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 35860683 # Simulator tick rate (ticks/s)
+host_mem_usage 256516 # Number of bytes of host memory used
+host_seconds 1906.68 # Real time elapsed on the host
sim_insts 273036725 # Number of instructions simulated
sim_ops 349064449 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 194176 # Number of bytes read from this memory
@@ -362,8 +362,8 @@ system.cpu.rename.LSQFullEvents 10191603 # Nu
system.cpu.rename.FullRegisterEvents 1124 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 432142984 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 2330358431 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 1257645546 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 1072712885 # Number of floating rename lookups
+system.cpu.rename.int_rename_lookups 1572902779 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 200313916 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 384566193 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 47576791 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 11831 # count of serializing insts renamed