diff options
Diffstat (limited to 'tests/long/se/30.eon/ref/arm')
| -rw-r--r-- | tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini | 81 | ||||
| -rwxr-xr-x | tests/long/se/30.eon/ref/arm/linux/o3-timing/simout | 8 | ||||
| -rw-r--r-- | tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt | 1210 |
3 files changed, 665 insertions, 634 deletions
diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini index ca4ea2a9a..f736a3c63 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a -clock=1 +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -30,7 +30,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -78,6 +78,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -129,18 +130,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=262144 subblock_size=0 system=system @@ -159,7 +160,7 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -432,18 +433,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=131072 subblock_size=0 system=system @@ -457,6 +458,23 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=ArmInterrupts +[system.cpu.isa] +type=ArmISA +fpsid=1090793632 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=3 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=4027589137 +id_pfr0=49 +id_pfr1=1 +midr=890224640 + [system.cpu.itb] type=ArmTLB children=walker @@ -465,7 +483,7 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -473,24 +491,24 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=20 is_top_level=false max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -500,10 +518,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port @@ -540,15 +558,28 @@ master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clock=1 +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout index 2e2e5579e..4b90608f0 100755 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 21 2012 11:19:00 -gem5 started Sep 21 2012 13:21:28 +gem5 compiled Oct 30 2012 11:20:14 +gem5 started Oct 30 2012 19:45:28 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -12,5 +12,5 @@ Eon, Version 1.1 info: Increasing stack size by one page. info: Increasing stack size by one page. info: Increasing stack size by one page. -OO-style eon Time= 0.070000 -Exiting @ tick 70907303500 because target called exit() +OO-style eon Time= 0.060000 +Exiting @ tick 68267465500 because target called exit() diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index d021c65df..e8af9a733 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.071124 # Number of seconds simulated -sim_ticks 71123520500 # Number of ticks simulated -final_tick 71123520500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.068267 # Number of seconds simulated +sim_ticks 68267465500 # Number of ticks simulated +final_tick 68267465500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 165652 # Simulator instruction rate (inst/s) -host_op_rate 211776 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 43149002 # Simulator tick rate (ticks/s) -host_mem_usage 241844 # Number of bytes of host memory used -host_seconds 1648.32 # Real time elapsed on the host -sim_insts 273048466 # Number of instructions simulated -sim_ops 349076190 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 194944 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 272832 # Number of bytes read from this memory -system.physmem.bytes_read::total 467776 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 194944 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 194944 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3046 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 4263 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7309 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2740922 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3836031 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6576952 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2740922 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2740922 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2740922 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3836031 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6576952 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7309 # Total number of read requests seen +host_inst_rate 130031 # Simulator instruction rate (inst/s) +host_op_rate 166236 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 32510221 # Simulator tick rate (ticks/s) +host_mem_usage 238756 # Number of bytes of host memory used +host_seconds 2099.88 # Real time elapsed on the host +sim_insts 273048375 # Number of instructions simulated +sim_ops 349076099 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 193920 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 273088 # Number of bytes read from this memory +system.physmem.bytes_read::total 467008 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 193920 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 193920 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3030 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 4267 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7297 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2840592 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 4000266 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6840857 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2840592 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2840592 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2840592 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4000266 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6840857 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7297 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 7309 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 467776 # Total number of bytes read from memory +system.physmem.cpureqs 7297 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 467008 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 467776 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 467008 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 346 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 470 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 344 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 467 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 514 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 578 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 477 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 456 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 440 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 507 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 480 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 494 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 484 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 551 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 365 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 581 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 475 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 457 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 437 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 505 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 483 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 495 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 481 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 558 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 359 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 416 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 368 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 363 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 365 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 360 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 71123348000 # Total gap between requests +system.physmem.totGap 68267282000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 7309 # Categorize read packet sizes +system.physmem.readPktSize::6 7297 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -98,12 +98,12 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 4384 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2130 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 552 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 174 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 67 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4347 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2135 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 568 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 183 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 64 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -164,27 +164,27 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 38077286 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 170549286 # Sum of mem lat for all requests -system.physmem.totBusLat 29236000 # Total cycles spent in databus access -system.physmem.totBankLat 103236000 # Total cycles spent in bank access -system.physmem.avgQLat 5209.64 # Average queueing delay per request -system.physmem.avgBankLat 14124.50 # Average bank access latency per request +system.physmem.totQLat 36802775 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 167840775 # Sum of mem lat for all requests +system.physmem.totBusLat 29188000 # Total cycles spent in databus access +system.physmem.totBankLat 101850000 # Total cycles spent in bank access +system.physmem.avgQLat 5043.55 # Average queueing delay per request +system.physmem.avgBankLat 13957.79 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 23334.15 # Average memory access latency -system.physmem.avgRdBW 6.58 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 23001.34 # Average memory access latency +system.physmem.avgRdBW 6.84 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 6.58 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 6.84 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 6380 # Number of row buffer hits during reads +system.physmem.readRowHits 6392 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.29 # Row buffer hit rate for reads +system.physmem.readRowHitRate 87.60 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 9730927.35 # Average gap between requests +system.physmem.avgGap 9355527.20 # Average gap between requests system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -228,108 +228,108 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 142247042 # number of cpu cycles simulated +system.cpu.numCycles 136534932 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 43100384 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 21816758 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 2115490 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 28214597 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 17877846 # Number of BTB hits +system.cpu.BPredUnit.lookups 41739250 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 21065104 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1640413 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 26027262 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 16735646 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 6960493 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 7483 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 41104486 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 329097721 # Number of instructions fetch has processed -system.cpu.fetch.Branches 43100384 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 24838339 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 73741038 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 8424830 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 20890852 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 101 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 3376 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 52 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 39439386 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 697861 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 142038328 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.976886 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.453881 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 6736138 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 7270 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 38860071 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 317518566 # Number of instructions fetch has processed +system.cpu.fetch.Branches 41739250 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 23471784 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 70794265 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6760095 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 21559516 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 34 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1854 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 30 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 37487912 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 519564 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 136324280 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.989165 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.456365 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 68979513 48.56% 48.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 7395782 5.21% 53.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 5795573 4.08% 57.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 6270161 4.41% 62.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4963047 3.49% 65.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4315752 3.04% 68.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3304919 2.33% 71.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 4334607 3.05% 74.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 36678974 25.82% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 66156807 48.53% 48.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 6761816 4.96% 53.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 5641032 4.14% 57.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 6022575 4.42% 62.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4881557 3.58% 65.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4156543 3.05% 68.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3204825 2.35% 71.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4146681 3.04% 74.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 35352444 25.93% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 142038328 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.302997 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.313565 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 47965638 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 16109831 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 69363004 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 2371211 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 6228644 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 7501471 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 70557 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 414890822 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 218836 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 6228644 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 53736634 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1580220 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 347679 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 65886950 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 14258201 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 404388597 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 136 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1669522 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 10203430 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 860 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 443737755 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2388674830 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1302452182 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1086222648 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 384584986 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 59152769 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 14467 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 14465 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 35681480 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 105493757 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 93214934 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 4606734 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5678105 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 392069014 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 25544 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 378019437 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1377395 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 42071369 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 110527513 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1062 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 142038328 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.661390 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.043453 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 136324280 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.305704 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.325548 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 45389084 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 16729555 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 66615921 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 2549925 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 5039795 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 7269016 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 69099 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 401164000 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 213330 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 5039795 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 50891753 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1911896 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 347462 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 63595531 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 14537843 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 393365757 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 50 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1668272 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 10291112 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 1086 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 431881386 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2329985493 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1257436076 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1072549417 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 384584833 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 47296553 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 14334 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 14333 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 36353497 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 103432229 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 91356063 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 4280154 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5359345 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 383896453 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 25411 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 373948163 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1224653 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 34098402 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 84823076 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 961 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 136324280 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.743078 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.023492 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 29008018 20.42% 20.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 20551186 14.47% 34.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 20935508 14.74% 49.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 18224796 12.83% 62.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 24071271 16.95% 79.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15985787 11.25% 90.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 9045864 6.37% 97.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3293540 2.32% 99.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 922358 0.65% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 24852306 18.23% 18.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 19962410 14.64% 32.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 20554570 15.08% 47.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 18105177 13.28% 61.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 23977307 17.59% 78.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15767707 11.57% 90.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8831817 6.48% 96.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3361471 2.47% 99.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 911515 0.67% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 142038328 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 136324280 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9132 0.05% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 4698 0.03% 0.08% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 8956 0.05% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 4688 0.03% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.08% # attempts to use FU when none available @@ -348,349 +348,494 @@ system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.08% # at system.cpu.iq.fu_full::SimdShift 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 45614 0.25% 0.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 7807 0.04% 0.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 399 0.00% 0.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 3 0.00% 0.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 193826 1.08% 1.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 4889 0.03% 1.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 240972 1.34% 2.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.82% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9466915 52.66% 55.48% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 8004617 44.52% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 46185 0.26% 0.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 7671 0.04% 0.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 470 0.00% 0.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 2 0.00% 0.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 190051 1.07% 1.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 6041 0.03% 1.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 241741 1.36% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9330966 52.43% 55.27% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 7960919 44.73% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 128267116 33.93% 33.93% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2174674 0.58% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 6840592 1.81% 36.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 8692743 2.30% 38.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 3457219 0.91% 39.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1621907 0.43% 39.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 21346208 5.65% 45.61% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 7171870 1.90% 47.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 7135741 1.89% 49.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 49.44% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 102459140 27.10% 76.54% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 88676941 23.46% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 126153074 33.74% 33.74% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2174128 0.58% 34.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 34.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 6786226 1.81% 36.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 8470375 2.27% 38.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 3426412 0.92% 39.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1600673 0.43% 39.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 20911148 5.59% 45.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 7171927 1.92% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 7134560 1.91% 49.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 49.21% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 101505429 27.14% 76.35% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 88438925 23.65% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 378019437 # Type of FU issued -system.cpu.iq.rate 2.657485 # Inst issue rate -system.cpu.iq.fu_busy_cnt 17978872 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.047561 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 666289235 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 301587031 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 252300909 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 251144234 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 132592793 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 118832927 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 266512180 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 129486129 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 10875090 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 373948163 # Type of FU issued +system.cpu.iq.rate 2.738846 # Inst issue rate +system.cpu.iq.fu_busy_cnt 17797690 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.047594 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 653530496 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 287597541 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 249877083 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 249712453 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 130436942 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 118161488 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 262975786 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 128770067 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 11107823 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 10842660 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 119827 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14278 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 10836994 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 8781151 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 113920 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14326 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 8978150 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 19866 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1167 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 176383 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1158 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 6228644 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 80063 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 4890 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 392103714 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1113019 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 105493757 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 93214934 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 14372 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 353 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 361 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14278 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1696490 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 500488 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 2196978 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 373371007 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 101101213 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 4648430 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 5039795 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 281091 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 41482 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 383923458 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 951525 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 103432229 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 91356063 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 14236 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 345 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 384 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14326 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1283309 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 356464 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1639773 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 370071311 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 100289689 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3876852 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9156 # number of nop insts executed -system.cpu.iew.exec_refs 188456752 # number of memory reference insts executed -system.cpu.iew.exec_branches 38701393 # Number of branches executed -system.cpu.iew.exec_stores 87355539 # Number of stores executed -system.cpu.iew.exec_rate 2.624807 # Inst execution rate -system.cpu.iew.wb_sent 371934669 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 371133836 # cumulative count of insts written-back -system.cpu.iew.wb_producers 184775670 # num instructions producing a value -system.cpu.iew.wb_consumers 367646771 # num instructions consuming a value +system.cpu.iew.exec_nop 1594 # number of nop insts executed +system.cpu.iew.exec_refs 187642898 # number of memory reference insts executed +system.cpu.iew.exec_branches 38279004 # Number of branches executed +system.cpu.iew.exec_stores 87353209 # Number of stores executed +system.cpu.iew.exec_rate 2.710451 # Inst execution rate +system.cpu.iew.wb_sent 368702519 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 368038571 # cumulative count of insts written-back +system.cpu.iew.wb_producers 182991065 # num instructions producing a value +system.cpu.iew.wb_consumers 363891400 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.609079 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.502590 # average fanout of values written-back +system.cpu.iew.wb_rate 2.695563 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.502873 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 43027028 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 24482 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 2045711 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 135809685 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.570338 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.654112 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 34846819 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 24450 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 1571698 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 131284486 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.658933 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.660928 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 38417531 28.29% 28.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 29199317 21.50% 49.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13525216 9.96% 59.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11128430 8.19% 67.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 13789447 10.15% 78.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7275712 5.36% 83.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 3957925 2.91% 86.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3970991 2.92% 89.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 14545116 10.71% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 34526115 26.30% 26.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 28464962 21.68% 47.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13313072 10.14% 58.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11375196 8.66% 66.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 13798040 10.51% 77.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7398451 5.64% 82.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 3831320 2.92% 85.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3930958 2.99% 88.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 14646372 11.16% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 135809685 # Number of insts commited each cycle -system.cpu.commit.committedInsts 273049078 # Number of instructions committed -system.cpu.commit.committedOps 349076802 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 131284486 # Number of insts commited each cycle +system.cpu.commit.committedInsts 273048987 # Number of instructions committed +system.cpu.commit.committedOps 349076711 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 177029037 # Number of memory references committed -system.cpu.commit.loads 94651097 # Number of loads committed +system.cpu.commit.refs 177028991 # Number of memory references committed +system.cpu.commit.loads 94651078 # Number of loads committed system.cpu.commit.membars 11033 # Number of memory barriers committed -system.cpu.commit.branches 36549060 # Number of branches committed +system.cpu.commit.branches 36549040 # Number of branches committed system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions. -system.cpu.commit.int_insts 279594003 # Number of committed integer instructions. +system.cpu.commit.int_insts 279593931 # Number of committed integer instructions. system.cpu.commit.function_calls 6225112 # Number of function calls committed. -system.cpu.commit.bw_lim_events 14545116 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 14646372 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 513365876 # The number of ROB reads -system.cpu.rob.rob_writes 790440754 # The number of ROB writes -system.cpu.timesIdled 6359 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 208714 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 273048466 # Number of Instructions Simulated -system.cpu.committedOps 349076190 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 273048466 # Number of Instructions Simulated -system.cpu.cpi 0.520959 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.520959 # CPI: Total CPI of All Threads -system.cpu.ipc 1.919537 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.919537 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1783321389 # number of integer regfile reads -system.cpu.int_regfile_writes 236147934 # number of integer regfile writes -system.cpu.fp_regfile_reads 189806588 # number of floating regfile reads -system.cpu.fp_regfile_writes 133619756 # number of floating regfile writes -system.cpu.misc_regfile_reads 991070858 # number of misc regfile reads -system.cpu.misc_regfile_writes 34426479 # number of misc regfile writes -system.cpu.icache.replacements 14002 # number of replacements -system.cpu.icache.tagsinuse 1857.450296 # Cycle average of tags in use -system.cpu.icache.total_refs 39422164 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 15897 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 2479.849280 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 500559121 # The number of ROB reads +system.cpu.rob.rob_writes 772890927 # The number of ROB writes +system.cpu.timesIdled 6411 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 210652 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 273048375 # Number of Instructions Simulated +system.cpu.committedOps 349076099 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 273048375 # Number of Instructions Simulated +system.cpu.cpi 0.500039 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.500039 # CPI: Total CPI of All Threads +system.cpu.ipc 1.999843 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.999843 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1769305779 # number of integer regfile reads +system.cpu.int_regfile_writes 232713829 # number of integer regfile writes +system.cpu.fp_regfile_reads 188383123 # number of floating regfile reads +system.cpu.fp_regfile_writes 132609484 # number of floating regfile writes +system.cpu.misc_regfile_reads 973808735 # number of misc regfile reads +system.cpu.misc_regfile_writes 34426415 # number of misc regfile writes +system.cpu.icache.replacements 13908 # number of replacements +system.cpu.icache.tagsinuse 1849.811927 # Cycle average of tags in use +system.cpu.icache.total_refs 37470862 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 15795 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 2372.324280 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1857.450296 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.906958 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.906958 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 39422164 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 39422164 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 39422164 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 39422164 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 39422164 # number of overall hits -system.cpu.icache.overall_hits::total 39422164 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 17219 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 17219 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 17219 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 17219 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 17219 # number of overall misses -system.cpu.icache.overall_misses::total 17219 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 362034000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 362034000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 362034000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 362034000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 362034000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 362034000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 39439383 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 39439383 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 39439383 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 39439383 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 39439383 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 39439383 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000437 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000437 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000437 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000437 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000437 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000437 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21025.262791 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 21025.262791 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 21025.262791 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 21025.262791 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 21025.262791 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 21025.262791 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 660 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1849.811927 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.903228 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.903228 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 37470862 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 37470862 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 37470862 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 37470862 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 37470862 # number of overall hits +system.cpu.icache.overall_hits::total 37470862 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 17049 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 17049 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 17049 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 17049 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 17049 # number of overall misses +system.cpu.icache.overall_misses::total 17049 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 356549497 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 356549497 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 356549497 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 356549497 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 356549497 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 356549497 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 37487911 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 37487911 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 37487911 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 37487911 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 37487911 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 37487911 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000455 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000455 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000455 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000455 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000455 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000455 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20913.220541 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 20913.220541 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 20913.220541 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 20913.220541 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 20913.220541 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 20913.220541 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 585 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 15 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 19 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 44 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 30.789474 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1322 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1322 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1322 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1322 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1322 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1322 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15897 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 15897 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 15897 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 15897 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 15897 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 15897 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 295359000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 295359000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 295359000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 295359000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 295359000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 295359000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000403 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000403 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000403 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000403 # mshr miss rate for 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accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 13257 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 172061347 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 172061347 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 172061347 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 172061347 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000045 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000259 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000259 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000147 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000147 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_latency::cpu.data 996644164 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 996644164 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 996644164 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 996644164 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 88819275 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 88819275 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 82052665 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 82052665 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13477 # number of LoadLockedReq accesses(hits+misses) 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0.000257 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000148 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000148 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000147 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000147 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000147 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000147 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40455.183452 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 40455.183452 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39020.440260 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 39020.440260 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40704.399407 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 40704.399407 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39423.502061 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 39423.502061 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 57500 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 57500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 39250.936823 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 39250.936823 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 39250.936823 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 39250.936823 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 13009 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 844 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 400 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 16 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 32.522500 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 52.750000 # average number of cycles each access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 39629.574297 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 39629.574297 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 39629.574297 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 39629.574297 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 13562 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 751 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 431 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 12 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.466357 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 62.583333 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1035 # number of writebacks -system.cpu.dcache.writebacks::total 1035 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2253 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2253 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18405 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 18405 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 1040 # number of writebacks +system.cpu.dcache.writebacks::total 1040 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2234 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2234 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18291 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 18291 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 20658 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 20658 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 20658 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 20658 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1808 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1808 # number of ReadReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 20525 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 20525 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 20525 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 20525 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1812 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1812 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2812 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 2812 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4620 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4620 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4620 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4620 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 79609500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 79609500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 131989000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 131989000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 211598500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 211598500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 211598500 # number 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cycles +system.cpu.dcache.demand_mshr_miss_latency::total 211723500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 211723500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 211723500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000020 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000020 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000034 # mshr miss rate for WriteReq accesses @@ -699,159 +844,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 44031.803097 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 44031.803097 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46937.766714 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46937.766714 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45800.541126 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 45800.541126 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45800.541126 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 45800.541126 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 44016.004415 # average ReadReq mshr miss latency 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number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 20516 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.192313 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.833426 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.257753 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.993957 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.993957 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.192313 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.931169 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.358696 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.192313 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.931169 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.358696 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49403.663723 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 49557.104914 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 49454.306377 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 46135.371960 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 46135.371960 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49403.663723 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 47333.217108 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 48193.300720 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49403.663723 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 47333.217108 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 48193.300720 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 11 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 39 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 50 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 11 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 39 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 50 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 11 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 39 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 50 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3046 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1467 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 4513 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2796 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 2796 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3046 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 4263 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 7309 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3046 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 4263 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 7309 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 111924644 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54839196 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 166763840 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 94353475 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 94353475 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 111924644 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 149192671 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 261117315 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 111924644 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 149192671 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 261117315 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.191621 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.811843 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.254929 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.993957 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.993957 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.191621 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.922727 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.356259 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.191621 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922727 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.356259 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 36744.794485 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37381.865031 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36951.881232 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33745.878040 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33745.878040 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 36744.794485 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34997.107905 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 35725.450130 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 36744.794485 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34997.107905 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 35725.450130 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |