diff options
Diffstat (limited to 'tests/long/se/30.eon/ref/arm')
4 files changed, 825 insertions, 800 deletions
diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt index c3dd06017..d7f32d52d 100644 --- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.225207 # Nu sim_ticks 225206521000 # Number of ticks simulated final_tick 225206521000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 132189 # Simulator instruction rate (inst/s) -host_op_rate 158707 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 109031633 # Simulator tick rate (ticks/s) -host_mem_usage 278744 # Number of bytes of host memory used -host_seconds 2065.52 # Real time elapsed on the host +host_inst_rate 284094 # Simulator instruction rate (inst/s) +host_op_rate 341086 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 234325505 # Simulator tick rate (ticks/s) +host_mem_usage 279956 # Number of bytes of host memory used +host_seconds 961.08 # Real time elapsed on the host sim_insts 273037855 # Number of instructions simulated sim_ops 327812212 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -415,7 +415,9 @@ system.cpu.op_class_0::FloatAdd 0 0.00% 32.48% # Cl system.cpu.op_class_0::FloatCmp 0 0.00% 32.48% # Class of committed instruction system.cpu.op_class_0::FloatCvt 0 0.00% 32.48% # Class of committed instruction system.cpu.op_class_0::FloatMult 0 0.00% 32.48% # Class of committed instruction +system.cpu.op_class_0::FloatMultAcc 0 0.00% 32.48% # Class of committed instruction system.cpu.op_class_0::FloatDiv 0 0.00% 32.48% # Class of committed instruction +system.cpu.op_class_0::FloatMisc 0 0.00% 32.48% # Class of committed instruction system.cpu.op_class_0::FloatSqrt 0 0.00% 32.48% # Class of committed instruction system.cpu.op_class_0::SimdAdd 0 0.00% 32.48% # Class of committed instruction system.cpu.op_class_0::SimdAddAcc 0 0.00% 32.48% # Class of committed instruction @@ -437,8 +439,10 @@ system.cpu.op_class_0::SimdFloatMisc 19652356 6.00% 44.33% # Cl system.cpu.op_class_0::SimdFloatMult 7136937 2.18% 46.51% # Class of committed instruction system.cpu.op_class_0::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of committed instruction system.cpu.op_class_0::SimdFloatSqrt 175285 0.05% 48.72% # Class of committed instruction -system.cpu.op_class_0::MemRead 85732248 26.15% 74.87% # Class of committed instruction -system.cpu.op_class_0::MemWrite 82375599 25.13% 100.00% # Class of committed instruction +system.cpu.op_class_0::MemRead 44185174 13.48% 62.20% # Class of committed instruction +system.cpu.op_class_0::MemWrite 55008381 16.78% 78.98% # Class of committed instruction +system.cpu.op_class_0::FloatMemRead 41547074 12.67% 91.65% # Class of committed instruction +system.cpu.op_class_0::FloatMemWrite 27367218 8.35% 100.00% # Class of committed instruction system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 327812212 # Class of committed instruction diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index 9802024db..fc2854304 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -1,67 +1,67 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.122178 # Number of seconds simulated -sim_ticks 122177531500 # Number of ticks simulated -final_tick 122177531500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.124291 # Number of seconds simulated +sim_ticks 124290972500 # Number of ticks simulated +final_tick 124290972500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 120262 # Simulator instruction rate (inst/s) -host_op_rate 144388 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 53814187 # Simulator tick rate (ticks/s) -host_mem_usage 292180 # Number of bytes of host memory used -host_seconds 2270.36 # Real time elapsed on the host +host_inst_rate 226846 # Simulator instruction rate (inst/s) +host_op_rate 272354 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 103264191 # Simulator tick rate (ticks/s) +host_mem_usage 292872 # Number of bytes of host memory used +host_seconds 1203.62 # Real time elapsed on the host sim_insts 273037218 # Number of instructions simulated sim_ops 327811600 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 1888192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 14650048 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 169280 # Number of bytes read from this memory -system.physmem.bytes_read::total 16707520 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1888192 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1888192 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 29503 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 228907 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 2645 # Number of read requests responded to by this memory -system.physmem.num_reads::total 261055 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 15454495 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 119907874 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 1385525 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 136747893 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 15454495 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 15454495 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 15454495 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 119907874 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 1385525 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 136747893 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 261056 # Number of read requests accepted +system.physmem.pwrStateResidencyTicks::UNDEFINED 124290972500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 1883840 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 14654016 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 168640 # Number of bytes read from this memory +system.physmem.bytes_read::total 16706496 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1883840 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1883840 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 29435 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 228969 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 2635 # Number of read requests responded to by this memory +system.physmem.num_reads::total 261039 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 15156692 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 117900888 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 1356816 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 134414396 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 15156692 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 15156692 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 15156692 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 117900888 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 1356816 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 134414396 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 261040 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 261056 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 261040 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 16707584 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 16706560 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 16707584 # Total read bytes from the system interface side +system.physmem.bytesReadSys 16706560 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 1259 # Per bank write bursts -system.physmem.perBankRdBursts::1 69992 # Per bank write bursts -system.physmem.perBankRdBursts::2 1296 # Per bank write bursts -system.physmem.perBankRdBursts::3 10759 # Per bank write bursts +system.physmem.perBankRdBursts::1 69986 # Per bank write bursts +system.physmem.perBankRdBursts::2 1297 # Per bank write bursts +system.physmem.perBankRdBursts::3 10756 # Per bank write bursts system.physmem.perBankRdBursts::4 42908 # Per bank write bursts -system.physmem.perBankRdBursts::5 121819 # Per bank write bursts -system.physmem.perBankRdBursts::6 160 # Per bank write bursts -system.physmem.perBankRdBursts::7 257 # Per bank write bursts +system.physmem.perBankRdBursts::5 121816 # Per bank write bursts +system.physmem.perBankRdBursts::6 153 # Per bank write bursts +system.physmem.perBankRdBursts::7 261 # Per bank write bursts system.physmem.perBankRdBursts::8 228 # Per bank write bursts system.physmem.perBankRdBursts::9 562 # Per bank write bursts -system.physmem.perBankRdBursts::10 7776 # Per bank write bursts +system.physmem.perBankRdBursts::10 7773 # Per bank write bursts system.physmem.perBankRdBursts::11 812 # Per bank write bursts system.physmem.perBankRdBursts::12 1213 # Per bank write bursts system.physmem.perBankRdBursts::13 743 # Per bank write bursts system.physmem.perBankRdBursts::14 662 # Per bank write bursts -system.physmem.perBankRdBursts::15 610 # Per bank write bursts +system.physmem.perBankRdBursts::15 611 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -80,14 +80,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 122177522000 # Total gap between requests +system.physmem.totGap 124290963000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 261056 # Read request sizes (log2) +system.physmem.readPktSize::6 261040 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -95,20 +95,20 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 204133 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 43349 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 204132 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 43333 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 12134 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 301 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 235 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 214 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 176 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 305 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 233 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 211 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 177 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 231 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 127 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 64 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 33 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 32 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 24 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 19 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 20 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 17 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see @@ -191,96 +191,96 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 67229 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 248.480388 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 181.727737 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 204.056429 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 18253 27.15% 27.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 21438 31.89% 59.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 11486 17.08% 76.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 6691 9.95% 86.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 4636 6.90% 92.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2199 3.27% 96.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1378 2.05% 98.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 426 0.63% 98.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 722 1.07% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 67229 # Bytes accessed per row activation -system.physmem.totQLat 4621160381 # Total ticks spent queuing -system.physmem.totMemAccLat 9515960381 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1305280000 # Total ticks spent in databus transfers -system.physmem.avgQLat 17701.80 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 67943 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 245.854084 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 180.733686 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 200.637928 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 18270 26.89% 26.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 22179 32.64% 59.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 11425 16.82% 76.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 6866 10.11% 86.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 4751 6.99% 93.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2068 3.04% 96.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1319 1.94% 98.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 392 0.58% 99.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 673 0.99% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 67943 # Bytes accessed per row activation +system.physmem.totQLat 4615275409 # Total ticks spent queuing +system.physmem.totMemAccLat 9509775409 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1305200000 # Total ticks spent in databus transfers +system.physmem.avgQLat 17680.34 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 36451.80 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 136.75 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 36430.34 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 134.41 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 136.75 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 134.41 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.07 # Data bus utilization in percentage -system.physmem.busUtilRead 1.07 # Data bus utilization in percentage for reads +system.physmem.busUtil 1.05 # Data bus utilization in percentage +system.physmem.busUtilRead 1.05 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.60 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 193817 # Number of row buffer hits during reads +system.physmem.readRowHits 193087 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 74.24 # Row buffer hit rate for reads +system.physmem.readRowHitRate 73.97 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 468012.69 # Average gap between requests -system.physmem.pageHitRate 74.24 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 445443180 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 236747280 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1773933000 # Energy for read commands per rank (pJ) +system.physmem.avgGap 476137.61 # Average gap between requests +system.physmem.pageHitRate 73.97 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 450177000 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 239263365 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1773833040 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 9531222480.000002 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 4632019500 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 224464800 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 45099806190 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 3562907040 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 919525950 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 66426265230 # Total energy per rank (pJ) -system.physmem_0.averagePower 543.686420 # Core power per rank (mW) -system.physmem_0.totalIdleTime 111434381144 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 154081000 # Time in different power states -system.physmem_0.memoryStateTime::REF 4033332000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 3253133750 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 9278182481 # Time in different power states -system.physmem_0.memoryStateTime::ACT 6555604606 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 98903197663 # Time in different power states -system.physmem_1.actEnergy 34636140 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 18382980 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 89999700 # Energy for read commands per rank (pJ) +system.physmem_0.refreshEnergy 9685497120.000002 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 4649003790 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 227628000 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 45880019340 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 3639028320 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 957591945 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 67502066010 # Total energy per rank (pJ) +system.physmem_0.averagePower 543.097094 # Core power per rank (mW) +system.physmem_0.totalIdleTime 113501776163 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 155671000 # Time in different power states +system.physmem_0.memoryStateTime::REF 4098592000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 3412225500 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 9476337397 # Time in different power states +system.physmem_0.memoryStateTime::ACT 6534800587 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 100613346016 # Time in different power states +system.physmem_1.actEnergy 35000280 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 18576525 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 89985420 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3038165520.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 716380560 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 121415040 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 10108537890 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 3723173760 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 21583783695 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 39434924925 # Total energy per rank (pJ) -system.physmem_1.averagePower 322.767403 # Core power per rank (mW) -system.physmem_1.totalIdleTime 120289757500 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 194586000 # Time in different power states -system.physmem_1.memoryStateTime::REF 1289158000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 88425719250 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 9695988513 # Time in different power states -system.physmem_1.memoryStateTime::ACT 404030000 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 22168049737 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 35971486 # Number of BP lookups -system.cpu.branchPred.condPredicted 19267078 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 984296 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 17894197 # Number of BTB lookups -system.cpu.branchPred.BTBHits 13923261 # Number of BTB hits +system.physmem_1.refreshEnergy 3070126800.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 722159790 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 122839680 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 10172185800 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 3790789440 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 22016840895 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 40039093920 # Total energy per rank (pJ) +system.physmem_1.averagePower 322.140000 # Core power per rank (mW) +system.physmem_1.totalIdleTime 122386077248 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 197400000 # Time in different power states +system.physmem_1.memoryStateTime::REF 1302732000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 90206777750 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 9871788058 # Time in different power states +system.physmem_1.memoryStateTime::ACT 404763252 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 22307511440 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 124290972500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 35978086 # Number of BP lookups +system.cpu.branchPred.condPredicted 19268966 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 984583 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 17896722 # Number of BTB lookups +system.cpu.branchPred.BTBHits 13923101 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 77.808806 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 6951889 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 4417 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 2517219 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 2473355 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 43864 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 128904 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 77.796934 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 6952398 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 4419 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 2517542 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 2473672 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 43870 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 129186 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 124290972500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -310,7 +310,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 124290972500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -340,7 +340,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 124290972500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -370,7 +370,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 124290972500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -401,234 +401,242 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 122177531500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 244355064 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 124290972500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 248581946 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 12854090 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 309386185 # Number of instructions fetch has processed -system.cpu.fetch.Branches 35971486 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 23348505 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 227028352 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1990311 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 1601 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 93 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 3162 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 82203694 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 34298 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 240882453 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.544883 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.296552 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 12982171 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 309515100 # Number of instructions fetch has processed +system.cpu.fetch.Branches 35978086 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 23349171 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 231243677 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1995433 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 1630 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 63 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 3229 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 82227465 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 34636 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 245228486 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.518257 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.300334 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 80675861 33.49% 33.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 40201773 16.69% 50.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 28081031 11.66% 61.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 91923788 38.16% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 84781187 34.57% 34.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 40505386 16.52% 51.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 28011183 11.42% 62.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 91930730 37.49% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 240882453 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.147210 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.266134 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 26812973 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 90710528 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 98252382 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 24245286 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 861284 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 6686689 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 134210 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 348538542 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3411137 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 861284 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 43083632 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 37000044 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 289266 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 105269732 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 54378495 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 344597413 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 1451618 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 7112089 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 85489 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 7460814 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 27903739 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 3277402 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 394869828 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2218091968 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 335911643 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 192912802 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 245228486 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.144733 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.245123 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 27310570 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 94773867 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 97190577 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 25089647 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 863825 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 6682147 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 134191 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 348416966 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3358743 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 863825 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 44033987 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 38819082 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 289712 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 104520763 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 56701117 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 344543720 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 1460141 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 7869954 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 94767 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 8436803 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 28433094 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 3429388 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 394731046 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2217541719 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 335903437 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 192790757 # Number of floating rename lookups system.cpu.rename.CommittedMaps 372230048 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 22639780 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 11606 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 11574 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 57375410 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 89984183 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 84392474 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1977179 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1898949 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 343275804 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 22622 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 339466020 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 967573 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 15486826 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 37253539 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 502 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 240882453 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.409260 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.140571 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 22500998 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 11600 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 11566 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 59469204 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 89978957 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 84398693 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2368147 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1979963 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 343241150 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 22616 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 339372334 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 953627 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 15452166 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 36722458 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 496 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 245228486 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.383903 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.138993 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 60724616 25.21% 25.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 76160793 31.62% 56.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 59430978 24.67% 81.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 34569007 14.35% 95.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 9283720 3.85% 99.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 678664 0.28% 99.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 34675 0.01% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 64185587 26.17% 26.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 77296840 31.52% 57.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 59648022 24.32% 82.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 34412911 14.03% 96.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 8897509 3.63% 99.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 775021 0.32% 99.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 12596 0.01% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 240882453 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 245228486 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9218221 7.75% 7.75% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 7322 0.01% 7.76% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 7.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 7.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 7.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 7.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 238834 0.20% 7.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 138891 0.12% 8.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 70679 0.06% 8.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 68365 0.06% 8.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 640804 0.54% 8.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 296732 0.25% 8.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 541759 0.46% 9.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.44% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 51504063 43.31% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 56187426 47.25% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 8796506 6.82% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 7321 0.01% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 160578 0.12% 6.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 165226 0.13% 7.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 81752 0.06% 7.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 59978 0.05% 7.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 823294 0.64% 7.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 313002 0.24% 8.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 382743 0.30% 8.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.36% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 27474499 21.29% 29.65% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 41314471 32.01% 61.66% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 30691566 23.78% 85.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 18785214 14.56% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 108184064 31.87% 31.87% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2148340 0.63% 32.50% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 32.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 32.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 32.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 32.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 32.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 32.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 32.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 32.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 32.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 32.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 32.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 32.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 32.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 32.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 32.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 32.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 32.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 32.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 6792701 2.00% 34.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 34.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 8634973 2.54% 37.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 3210554 0.95% 37.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1592986 0.47% 38.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 20863316 6.15% 44.61% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 7179113 2.11% 46.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 7141894 2.10% 48.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 175297 0.05% 48.88% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 90024187 26.52% 75.40% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 83518595 24.60% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 108168622 31.87% 31.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2148105 0.63% 32.51% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 32.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 32.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 32.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 32.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 32.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 32.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 32.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 32.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 32.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 32.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 32.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 32.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 32.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 32.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 32.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 32.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 32.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 32.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 32.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 32.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 6799290 2.00% 34.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 34.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 8596304 2.53% 37.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 3207462 0.95% 37.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1592646 0.47% 38.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 20838335 6.14% 44.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 7175285 2.11% 46.71% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 7140600 2.10% 48.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 175297 0.05% 48.87% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 46512146 13.71% 62.57% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 55971174 16.49% 79.07% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 43494368 12.82% 91.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 27552700 8.12% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 339466020 # Type of FU issued -system.cpu.iq.rate 1.389233 # Inst issue rate -system.cpu.iq.fu_busy_cnt 118913096 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.350295 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 756328552 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 235151256 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 219171646 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 283366610 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 123646075 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 116917582 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 293624810 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 164754306 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 5408815 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 339372334 # Type of FU issued +system.cpu.iq.rate 1.365233 # Inst issue rate +system.cpu.iq.fu_busy_cnt 129056150 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.380279 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 765892553 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 235176629 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 219155615 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 288090378 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 123554179 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 116971321 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 298827775 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 169600709 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 5587408 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4251908 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7378 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 12082 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2016857 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4246682 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7095 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14879 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2023076 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 126936 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 613330 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 158632 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 537261 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 861284 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1350225 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1508994 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 343299844 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 863825 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1349614 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1747627 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 343265167 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 89984183 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 84392474 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 11589 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 7652 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1502014 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 12082 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 438026 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 454508 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 892534 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 337437017 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 89435625 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2029003 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 89978957 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 84398693 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 11583 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 6712 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1741146 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14879 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 437892 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 454499 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 892391 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 337381646 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 89446380 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1990688 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1418 # number of nop insts executed -system.cpu.iew.exec_refs 172563316 # number of memory reference insts executed -system.cpu.iew.exec_branches 31556143 # Number of branches executed -system.cpu.iew.exec_stores 83127691 # Number of stores executed -system.cpu.iew.exec_rate 1.380929 # Inst execution rate -system.cpu.iew.wb_sent 336235772 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 336089228 # cumulative count of insts written-back -system.cpu.iew.wb_producers 151786231 # num instructions producing a value -system.cpu.iew.wb_consumers 263562514 # num instructions consuming a value -system.cpu.iew.wb_rate 1.375413 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.575902 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 14164375 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 1401 # number of nop insts executed +system.cpu.iew.exec_refs 172578078 # number of memory reference insts executed +system.cpu.iew.exec_branches 31542222 # Number of branches executed +system.cpu.iew.exec_stores 83131698 # Number of stores executed +system.cpu.iew.exec_rate 1.357225 # Inst execution rate +system.cpu.iew.wb_sent 336270787 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 336126936 # cumulative count of insts written-back +system.cpu.iew.wb_producers 153093104 # num instructions producing a value +system.cpu.iew.wb_consumers 267318257 # num instructions consuming a value +system.cpu.iew.wb_rate 1.352178 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.572700 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 14160521 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 850425 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 238692959 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.373364 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.035708 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 850692 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 243036852 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.348817 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.044097 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 107534765 45.05% 45.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 67583251 28.31% 73.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 20880103 8.75% 82.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 13256001 5.55% 87.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 8658859 3.63% 91.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 4515867 1.89% 93.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 3014415 1.26% 94.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 2598093 1.09% 95.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 10651605 4.46% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 113296519 46.62% 46.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 65998128 27.16% 73.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 21346559 8.78% 82.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 13163754 5.42% 87.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 8182652 3.37% 91.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 4361649 1.79% 93.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 2983865 1.23% 94.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 2442147 1.00% 95.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 11261579 4.63% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 238692959 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 243036852 # Number of insts commited each cycle system.cpu.commit.committedInsts 273037830 # Number of instructions committed system.cpu.commit.committedOps 327812212 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -647,7 +655,9 @@ system.cpu.commit.op_class_0::FloatAdd 0 0.00% 32.48% # Cl system.cpu.commit.op_class_0::FloatCmp 0 0.00% 32.48% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 0 0.00% 32.48% # Class of committed instruction system.cpu.commit.op_class_0::FloatMult 0 0.00% 32.48% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 32.48% # Class of committed instruction system.cpu.commit.op_class_0::FloatDiv 0 0.00% 32.48% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 0 0.00% 32.48% # Class of committed instruction system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 32.48% # Class of committed instruction system.cpu.commit.op_class_0::SimdAdd 0 0.00% 32.48% # Class of committed instruction system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 32.48% # Class of committed instruction @@ -669,560 +679,563 @@ system.cpu.commit.op_class_0::SimdFloatMisc 19652356 6.00% 44.33% # system.cpu.commit.op_class_0::SimdFloatMult 7136937 2.18% 46.51% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 175285 0.05% 48.72% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 85732275 26.15% 74.87% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 82375617 25.13% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 44185201 13.48% 62.20% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 55008399 16.78% 78.98% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 41547074 12.67% 91.65% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 27367218 8.35% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 327812212 # Class of committed instruction -system.cpu.commit.bw_lim_events 10651605 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 570015418 # The number of ROB reads -system.cpu.rob.rob_writes 686144847 # The number of ROB writes -system.cpu.timesIdled 39403 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 3472611 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 11261579 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 573745483 # The number of ROB reads +system.cpu.rob.rob_writes 686139464 # The number of ROB writes +system.cpu.timesIdled 39266 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 3353460 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 273037218 # Number of Instructions Simulated system.cpu.committedOps 327811600 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.894951 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.894951 # CPI: Total CPI of All Threads -system.cpu.ipc 1.117379 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.117379 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 325163205 # number of integer regfile reads -system.cpu.int_regfile_writes 134094196 # number of integer regfile writes -system.cpu.fp_regfile_reads 186638267 # number of floating regfile reads -system.cpu.fp_regfile_writes 131663703 # number of floating regfile writes -system.cpu.cc_regfile_reads 1279409265 # number of cc regfile reads -system.cpu.cc_regfile_writes 80058845 # number of cc regfile writes -system.cpu.misc_regfile_reads 1056731782 # number of misc regfile reads +system.cpu.cpi 0.910432 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.910432 # CPI: Total CPI of All Threads +system.cpu.ipc 1.098379 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.098379 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 325197340 # number of integer regfile reads +system.cpu.int_regfile_writes 134110925 # number of integer regfile writes +system.cpu.fp_regfile_reads 186451715 # number of floating regfile reads +system.cpu.fp_regfile_writes 131763174 # number of floating regfile writes +system.cpu.cc_regfile_reads 1279529156 # number of cc regfile reads +system.cpu.cc_regfile_writes 79965327 # number of cc regfile writes +system.cpu.misc_regfile_reads 1056169060 # number of misc regfile reads system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 1542799 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.841241 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 162053309 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1543311 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 105.003664 # Average number of references to valid blocks. +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 124290972500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 1542798 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.843941 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 161960642 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1543310 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 104.943687 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 91635000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.841241 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999690 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999690 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 511.843941 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999695 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999695 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 91 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 306 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 89 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 333480485 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 333480485 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 81040424 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 81040424 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 80921391 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 80921391 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 69631 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 69631 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 333233788 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 333233788 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 124290972500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 80947765 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 80947765 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 80921307 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 80921307 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 69703 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 69703 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 10908 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 10908 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 161961815 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 161961815 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 162031446 # number of overall hits -system.cpu.dcache.overall_hits::total 162031446 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2784008 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2784008 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1131308 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1131308 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 161869072 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 161869072 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 161938775 # number of overall hits +system.cpu.dcache.overall_hits::total 161938775 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2753247 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2753247 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1131392 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1131392 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 18 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 18 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 3915316 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3915316 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3915334 # number of overall misses -system.cpu.dcache.overall_misses::total 3915334 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 47872980500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 47872980500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9172353414 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9172353414 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 3884639 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3884639 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3884657 # number of overall misses +system.cpu.dcache.overall_misses::total 3884657 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 47533202500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 47533202500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9194702918 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9194702918 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 194000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 194000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 57045333914 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 57045333914 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 57045333914 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 57045333914 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 83824432 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 83824432 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 56727905418 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 56727905418 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 56727905418 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 56727905418 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 83701012 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 83701012 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052699 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052699 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 69649 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 69649 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 69721 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 69721 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10912 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 10912 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 165877131 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 165877131 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 165946780 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 165946780 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.033212 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.033212 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013788 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.013788 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 165753711 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 165753711 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 165823432 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 165823432 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032894 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.032894 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013789 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.013789 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000258 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.000258 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000367 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000367 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.023604 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.023604 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.023594 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.023594 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17195.705077 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17195.705077 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8107.742024 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 8107.742024 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.023436 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.023436 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.023426 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.023426 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17264.416342 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17264.416342 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8126.894054 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 8126.894054 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 48500 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 48500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14569.790513 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14569.790513 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14569.723532 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14569.723532 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14603.134401 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14603.134401 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14603.066736 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14603.066736 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1090477 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1098365 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 136210 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 136254 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 8.005851 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 1542799 # number of writebacks -system.cpu.dcache.writebacks::total 1542799 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1461435 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1461435 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 910564 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 910564 # number of WriteReq MSHR hits +system.cpu.dcache.avg_blocked_cycles::no_targets 8.061158 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 1542798 # number of writebacks +system.cpu.dcache.writebacks::total 1542798 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1430654 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1430654 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 910668 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 910668 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2371999 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2371999 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2371999 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2371999 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1322573 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1322573 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 220744 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 220744 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 2341322 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2341322 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2341322 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2341322 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1322593 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1322593 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 220724 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 220724 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 11 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 11 # number of SoftPFReq MSHR misses system.cpu.dcache.demand_mshr_misses::cpu.data 1543317 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 1543317 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1543328 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1543328 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27142024000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 27142024000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1845028694 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1845028694 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27108294500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 27108294500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1845527195 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1845527195 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1269000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1269000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28987052694 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 28987052694 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28988321694 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 28988321694 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015778 # 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Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999627 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999627 # Average percentage of cache occupancy +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18760.774160 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 18760.774160 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18761.462693 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 18761.462693 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 124290972500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 726144 # number of replacements +system.cpu.icache.tags.tagsinuse 511.811939 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 81493663 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 726656 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 112.148889 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 348619500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.811939 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999633 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999633 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 243 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 14 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 130 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 157 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 100 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 70 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 165133459 # Number of tag accesses -system.cpu.icache.tags.data_accesses 165133459 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 81470653 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 81470653 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 81470653 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 81470653 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 81470653 # 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Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 81493663 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 81493663 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 81493663 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 81493663 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 81493663 # number of overall hits +system.cpu.icache.overall_hits::total 81493663 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 733780 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 733780 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 733780 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 733780 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 733780 # number of overall misses +system.cpu.icache.overall_misses::total 733780 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 8421387941 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 8421387941 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 8421387941 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 8421387941 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 8421387941 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 8421387941 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 82227443 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 82227443 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 82227443 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 82227443 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 82227443 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 82227443 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008924 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.008924 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.008924 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.008924 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.008924 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.008924 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 11476.720463 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 11476.720463 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 11476.720463 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 11476.720463 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 11476.720463 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 11476.720463 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 139290 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 124 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 4376 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 4412 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 32.512340 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 31.570716 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 41.333333 # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 725588 # number of writebacks -system.cpu.icache.writebacks::total 725588 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 6903 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 6903 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 6903 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 6903 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 6903 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 6903 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 726116 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 726116 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 726116 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 726116 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 726116 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 726116 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 7892899950 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 7892899950 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 7892899950 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 7892899950 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 7892899950 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 7892899950 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008833 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008833 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008833 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.008833 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008833 # 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Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 189 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 6123 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::0 16 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::1 22 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::2 48 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 3 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 103 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 162 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 554 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1140 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 141 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4124 # 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Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 163 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 542 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 737 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 554 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4127 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.011536 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.373718 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 70566797 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 70566797 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 124290972500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 968251 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 968251 # 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number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 49 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::total 49 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 51 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::total 51 # number of ReadExReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 11 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::total 11 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 34 # number of ReadSharedReq MSHR hits system.cpu.l2cache.ReadSharedReq_mshr_hits::total 34 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2446651000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 16670177500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 206290287 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 19323118787 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.941176 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.941176 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.003307 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.003307 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.040637 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.040637 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.172525 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.172525 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.040637 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.148322 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.113870 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.040637 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.148322 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.944444 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.944444 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.003348 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.003348 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.040512 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.040512 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.172564 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.172564 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.040512 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.148362 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.113840 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.040512 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.148362 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.137871 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3790.758771 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 3790.758771 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15687.500000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15687.500000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 88424.657534 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 88424.657534 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 83022.895201 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 83022.895201 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72903.283416 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72903.283416 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 83022.895201 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72952.782134 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 74102.534335 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 83022.895201 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72952.782134 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3790.758771 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61862.391277 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 4537831 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2268421 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 254469 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 51822 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 51821 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_mshr_miss_rate::total 0.137664 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3814.680406 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 3814.680406 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15470.588235 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15470.588235 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 88102.165088 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 88102.165088 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 83117.645060 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 83117.645060 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72755.860316 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72755.860316 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 83117.645060 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72805.390686 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73980.102939 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 83117.645060 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72805.390686 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3814.680406 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61837.344070 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 4538943 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2268977 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 254452 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 51443 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 51442 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 2048687 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 968244 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1300143 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 55841 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 220739 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 220739 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 726116 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1322572 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2177738 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4629455 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6807193 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 92903808 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 197511040 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 290414848 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 55922 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 5184 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 2325285 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.131736 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.338205 # Request fanout histogram +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 124290972500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 2049252 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 968251 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1300691 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 55450 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 18 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 18 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 220730 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 220730 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 726673 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1322580 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2179407 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4629454 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6808861 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 92974976 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 197510912 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 290485888 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 55532 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 5248 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 2325451 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.131557 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.338010 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2018962 86.83% 86.83% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 306322 13.17% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2019523 86.84% 86.84% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 305927 13.16% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2325285 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4537302500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2325451 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4538413500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 3.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1089460423 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1090077361 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2314997455 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2314996455 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.9 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 261072 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 253753 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 261057 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 253739 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 122177531500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 260325 # Transaction distribution -system.membus.trans_dist::UpgradeReq 16 # Transaction distribution -system.membus.trans_dist::ReadExReq 730 # Transaction distribution -system.membus.trans_dist::ReadExResp 730 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 260326 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 522127 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 522127 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16707520 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 16707520 # Cumulative packet size per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 124290972500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 260300 # Transaction distribution +system.membus.trans_dist::UpgradeReq 17 # Transaction distribution +system.membus.trans_dist::ReadExReq 739 # Transaction distribution +system.membus.trans_dist::ReadExResp 739 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 260301 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 522096 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 522096 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16706496 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 16706496 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 261072 # Request fanout histogram +system.membus.snoop_fanout::samples 261057 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 261072 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 261057 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 261072 # Request fanout histogram -system.membus.reqLayer0.occupancy 329884354 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 261057 # Request fanout histogram +system.membus.reqLayer0.occupancy 317283410 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 1377672131 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1389540628 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt index ec456bd8f..a62595a11 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.201717 # Nu sim_ticks 201717314000 # Number of ticks simulated final_tick 201717314000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 781022 # Simulator instruction rate (inst/s) -host_op_rate 937704 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 577011080 # Simulator tick rate (ticks/s) -host_mem_usage 268872 # Number of bytes of host memory used -host_seconds 349.59 # Real time elapsed on the host +host_inst_rate 1476968 # Simulator instruction rate (inst/s) +host_op_rate 1773264 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1091168515 # Simulator tick rate (ticks/s) +host_mem_usage 268416 # Number of bytes of host memory used +host_seconds 184.86 # Real time elapsed on the host sim_insts 273037595 # Number of instructions simulated sim_ops 327811950 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -193,7 +193,9 @@ system.cpu.op_class::FloatAdd 0 0.00% 32.48% # Cl system.cpu.op_class::FloatCmp 0 0.00% 32.48% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 32.48% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 32.48% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 32.48% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 32.48% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 32.48% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 32.48% # Class of executed instruction @@ -215,8 +217,10 @@ system.cpu.op_class::SimdFloatMisc 19652356 6.00% 44.33% # Cl system.cpu.op_class::SimdFloatMult 7136937 2.18% 46.51% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 175285 0.05% 48.72% # Class of executed instruction -system.cpu.op_class::MemRead 85732235 26.15% 74.87% # Class of executed instruction -system.cpu.op_class::MemWrite 82375594 25.13% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 44185161 13.48% 62.20% # Class of executed instruction +system.cpu.op_class::MemWrite 55008376 16.78% 78.98% # Class of executed instruction +system.cpu.op_class::FloatMemRead 41547074 12.67% 91.65% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 27367218 8.35% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 327812145 # Class of executed instruction diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt index 81799693e..42d337cb5 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.517298 # Nu sim_ticks 517297855500 # Number of ticks simulated final_tick 517297855500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 565388 # Simulator instruction rate (inst/s) -host_op_rate 678769 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1072356714 # Simulator tick rate (ticks/s) -host_mem_usage 278352 # Number of bytes of host memory used -host_seconds 482.39 # Real time elapsed on the host +host_inst_rate 1075622 # Simulator instruction rate (inst/s) +host_op_rate 1291325 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2040106124 # Simulator tick rate (ticks/s) +host_mem_usage 278152 # Number of bytes of host memory used +host_seconds 253.56 # Real time elapsed on the host sim_insts 272739286 # Number of instructions simulated sim_ops 327433744 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -187,7 +187,9 @@ system.cpu.op_class::FloatAdd 0 0.00% 32.48% # Cl system.cpu.op_class::FloatCmp 0 0.00% 32.48% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 32.48% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 32.48% # Class of executed instruction system.cpu.op_class::FloatDiv 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 32.48% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 32.48% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 32.48% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 32.48% # Class of executed instruction @@ -209,8 +211,10 @@ system.cpu.op_class::SimdFloatMisc 19652356 6.00% 44.33% # Cl system.cpu.op_class::SimdFloatMult 7136937 2.18% 46.51% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 175285 0.05% 48.72% # Class of executed instruction -system.cpu.op_class::MemRead 85732248 26.15% 74.87% # Class of executed instruction -system.cpu.op_class::MemWrite 82375599 25.13% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 44185174 13.48% 62.20% # Class of executed instruction +system.cpu.op_class::MemWrite 55008381 16.78% 78.98% # Class of executed instruction +system.cpu.op_class::FloatMemRead 41547074 12.67% 91.65% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 27367218 8.35% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 327812214 # Class of executed instruction |