diff options
Diffstat (limited to 'tests/long/se/30.eon/ref/arm')
8 files changed, 424 insertions, 417 deletions
diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/minor-timing/config.ini index e8259a3e5..c0afc2364 100644 --- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/config.ini +++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/config.ini @@ -127,7 +127,7 @@ localPredictorSize=2048 numThreads=1 [system.cpu.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -586,7 +586,7 @@ eventq_index=0 opClass=InstPrefetch [system.cpu.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -696,7 +696,7 @@ sys=system port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=8 @@ -759,7 +759,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/m5/cpu2000/binaries/arm/linux/eon +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/eon gid=100 input=cin kvmInSE=false diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/simout b/tests/long/se/30.eon/ref/arm/linux/minor-timing/simout index 3857083f4..8d785cb1f 100755 --- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/simout +++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/simout @@ -1,12 +1,14 @@ +Redirecting stdout to build/ARM/tests/opt/long/se/30.eon/arm/linux/minor-timing/simout +Redirecting stderr to build/ARM/tests/opt/long/se/30.eon/arm/linux/minor-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 15 2015 20:30:55 -gem5 started Mar 15 2015 20:31:14 -gem5 executing on zizzer2 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/minor-timing -re /z/stever/hg/gem5/tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/minor-timing +gem5 compiled Sep 14 2015 23:29:19 +gem5 started Sep 15 2015 01:25:17 +gem5 executing on ribera.cs.wisc.edu +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/minor-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/minor-timing + Global frequency set at 1000000000000 ticks per second - 0: system.cpu.isa: ISA system set to: 0 0x3ccd9b0 info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Eon, Version 1.1 @@ -14,4 +16,4 @@ info: Increasing stack size by one page. info: Increasing stack size by one page. info: Increasing stack size by one page. OO-style eon Time= 0.210000 -Exiting @ tick 216864820000 because target called exit() +Exiting @ tick 215505832500 because target called exit() diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt index 454441ad4..333ae52c9 100644 --- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt @@ -1,60 +1,60 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.216071 # Number of seconds simulated -sim_ticks 216071083000 # Number of ticks simulated -final_tick 216071083000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.215506 # Number of seconds simulated +sim_ticks 215505832500 # Number of ticks simulated +final_tick 215505832500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 173126 # Simulator instruction rate (inst/s) -host_op_rate 207857 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 137004908 # Simulator tick rate (ticks/s) -host_mem_usage 323124 # Number of bytes of host memory used -host_seconds 1577.10 # Real time elapsed on the host +host_inst_rate 114925 # Simulator instruction rate (inst/s) +host_op_rate 137980 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 90709005 # Simulator tick rate (ticks/s) +host_mem_usage 317788 # Number of bytes of host memory used +host_seconds 2375.79 # Real time elapsed on the host sim_insts 273037857 # Number of instructions simulated sim_ops 327812214 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 219072 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 218880 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 266368 # Number of bytes read from this memory -system.physmem.bytes_read::total 485440 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 219072 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 219072 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3423 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 485248 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 218880 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 218880 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3420 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 4162 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7585 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1013889 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1232779 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2246668 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1013889 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1013889 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1013889 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1232779 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2246668 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7585 # Number of read requests accepted +system.physmem.num_reads::total 7582 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1015657 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1236013 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2251670 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1015657 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1015657 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1015657 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1236013 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2251670 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7582 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 7585 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 7582 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 485440 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 485248 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 485440 # Total read bytes from the system interface side +system.physmem.bytesReadSys 485248 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 630 # Per bank write bursts -system.physmem.perBankRdBursts::1 843 # Per bank write bursts +system.physmem.perBankRdBursts::1 844 # Per bank write bursts system.physmem.perBankRdBursts::2 628 # Per bank write bursts system.physmem.perBankRdBursts::3 541 # Per bank write bursts system.physmem.perBankRdBursts::4 466 # Per bank write bursts system.physmem.perBankRdBursts::5 349 # Per bank write bursts -system.physmem.perBankRdBursts::6 173 # Per bank write bursts +system.physmem.perBankRdBursts::6 171 # Per bank write bursts system.physmem.perBankRdBursts::7 228 # Per bank write bursts system.physmem.perBankRdBursts::8 209 # Per bank write bursts -system.physmem.perBankRdBursts::9 311 # Per bank write bursts +system.physmem.perBankRdBursts::9 310 # Per bank write bursts system.physmem.perBankRdBursts::10 342 # Per bank write bursts system.physmem.perBankRdBursts::11 428 # Per bank write bursts system.physmem.perBankRdBursts::12 553 # Per bank write bursts -system.physmem.perBankRdBursts::13 706 # Per bank write bursts +system.physmem.perBankRdBursts::13 705 # Per bank write bursts system.physmem.perBankRdBursts::14 638 # Per bank write bursts system.physmem.perBankRdBursts::15 540 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 216070847500 # Total gap between requests +system.physmem.totGap 215505593500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 7585 # Read request sizes (log2) +system.physmem.readPktSize::6 7582 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,8 +90,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 6627 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 897 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 6629 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 892 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 61 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1505 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 321.445847 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 189.975712 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 330.801659 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 552 36.68% 36.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 337 22.39% 59.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 156 10.37% 69.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 81 5.38% 74.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 75 4.98% 79.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 59 3.92% 83.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 41 2.72% 86.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 29 1.93% 88.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 175 11.63% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1505 # Bytes accessed per row activation -system.physmem.totQLat 52368250 # Total ticks spent queuing -system.physmem.totMemAccLat 194587000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 37925000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6904.19 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1519 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 318.272548 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 188.961816 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 330.159233 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 550 36.21% 36.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 342 22.51% 58.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 179 11.78% 70.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 82 5.40% 75.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 73 4.81% 80.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 43 2.83% 83.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 37 2.44% 85.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 30 1.97% 87.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 183 12.05% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1519 # Bytes accessed per row activation +system.physmem.totQLat 52046750 # Total ticks spent queuing +system.physmem.totMemAccLat 194209250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 37910000 # Total ticks spent in databus transfers +system.physmem.avgQLat 6864.51 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25654.19 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25614.51 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.25 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.25 # Average system read bandwidth in MiByte/s @@ -216,48 +216,48 @@ system.physmem.busUtilRead 0.02 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 6074 # Number of row buffer hits during reads +system.physmem.readRowHits 6056 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.08 # Row buffer hit rate for reads +system.physmem.readRowHitRate 79.87 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 28486598.22 # Average gap between requests -system.physmem.pageHitRate 80.08 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 5050080 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2755500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 29959800 # Energy for read commands per rank (pJ) +system.physmem.avgGap 28423317.53 # Average gap between requests +system.physmem.pageHitRate 79.87 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 4997160 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2726625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 29905200 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 14112540000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 5672899350 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 124664991000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 144488195730 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.714152 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 207389955000 # Time in different power states -system.physmem_0.memoryStateTime::REF 7215000000 # Time in different power states +system.physmem_0.refreshEnergy 14075415120 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 5632744275 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 124359177000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 144104965380 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.699601 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 206882994500 # Time in different power states +system.physmem_0.memoryStateTime::REF 7196020000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1464485500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1423707500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 6320160 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3448500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 28992600 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 6463800 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3526875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 28977000 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 14112540000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 5762856465 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 124586081250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 144500238975 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.769890 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 207255387750 # Time in different power states -system.physmem_1.memoryStateTime::REF 7215000000 # Time in different power states +system.physmem_1.refreshEnergy 14075415120 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 5808881115 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 124204671000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 144127934910 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.806188 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 206624169250 # Time in different power states +system.physmem_1.memoryStateTime::REF 7196020000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1598323500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1683261250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 33111389 # Number of BP lookups -system.cpu.branchPred.condPredicted 17094855 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1552605 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 17374125 # Number of BTB lookups -system.cpu.branchPred.BTBHits 15590921 # Number of BTB hits +system.cpu.branchPred.lookups 32816945 # Number of BP lookups +system.cpu.branchPred.condPredicted 16892744 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1463888 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 17497063 # Number of BTB lookups +system.cpu.branchPred.BTBHits 15468368 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 89.736439 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 6603992 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 88.405511 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 6575577 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -377,26 +377,26 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 432142166 # number of cpu cycles simulated +system.cpu.numCycles 431011665 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 273037857 # Number of instructions committed system.cpu.committedOps 327812214 # Number of ops (including micro ops) committed -system.cpu.discardedOps 4177938 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 3889170 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.582719 # CPI: cycles per instruction -system.cpu.ipc 0.631824 # IPC: instructions per cycle -system.cpu.tickCycles 428506724 # Number of cycles that the object actually ticked -system.cpu.idleCycles 3635442 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.578578 # CPI: cycles per instruction +system.cpu.ipc 0.633481 # IPC: instructions per cycle +system.cpu.tickCycles 427409330 # Number of cycles that the object actually ticked +system.cpu.idleCycles 3602335 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 1354 # number of replacements -system.cpu.dcache.tags.tagsinuse 3085.759854 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 168767138 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 3085.814933 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168714880 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4511 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37412.356019 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37400.771448 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3085.759854 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.753359 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.753359 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 3085.814933 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.753373 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.753373 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3157 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id @@ -404,72 +404,72 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 12 system.cpu.dcache.tags.age_task_id_blocks_1024::3 672 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 2432 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.770752 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 337553367 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 337553367 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 86634356 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 86634356 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 82047452 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 82047452 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 63540 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 63540 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 337448855 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 337448855 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 86582107 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 86582107 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 82047449 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 82047449 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 63534 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 63534 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 168681808 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168681808 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168745348 # number of overall hits -system.cpu.dcache.overall_hits::total 168745348 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 168629556 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168629556 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168693090 # number of overall hits +system.cpu.dcache.overall_hits::total 168693090 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 2059 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 2059 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5225 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5225 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 6 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 6 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 7284 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 7284 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 7290 # number of overall misses -system.cpu.dcache.overall_misses::total 7290 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 134727000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 134727000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 395694000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 395694000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 530421000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 530421000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 530421000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 530421000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 86636415 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 86636415 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_misses::cpu.data 5228 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5228 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 5 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 5 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 7287 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 7287 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 7292 # number of overall misses +system.cpu.dcache.overall_misses::total 7292 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 135542000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 135542000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 392317500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 392317500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 527859500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 527859500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 527859500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 527859500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 86584166 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 86584166 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 63546 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 63546 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 63539 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 63539 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 168689092 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 168689092 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 168752638 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 168752638 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 168636843 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 168636843 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 168700382 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 168700382 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000024 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000024 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000064 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.000064 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000094 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.000094 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000079 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.000079 # miss rate for SoftPFReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000043 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000043 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 65433.220010 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 65433.220010 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75730.909091 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 75730.909091 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 72820.016474 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 72820.016474 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 72760.082305 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 72760.082305 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 65829.043225 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 65829.043225 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75041.602907 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 75041.602907 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 72438.520653 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 72438.520653 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 72388.850795 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 72388.850795 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -480,109 +480,109 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 1010 # number of writebacks system.cpu.dcache.writebacks::total 1010 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 422 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 422 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2355 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2355 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2777 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2777 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2777 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2777 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1637 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1637 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 421 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 421 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2358 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2358 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2779 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2779 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2779 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2779 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1638 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1638 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2870 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 2870 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 4 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 4 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4507 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4507 # number of demand (read+write) MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4508 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4508 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4511 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4511 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 108637000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 108637000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 220584500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 220584500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 322000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 322000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 329221500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 329221500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 329543500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 329543500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 109498500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 109498500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 218637500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 218637500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 238000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 238000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 328136000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 328136000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 328374000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 328374000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000063 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000063 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000047 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000047 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66363.469762 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66363.469762 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76858.710801 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76858.710801 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 80500 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 80500 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73046.705125 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 73046.705125 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73053.314121 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 73053.314121 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66848.901099 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66848.901099 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76180.313589 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76180.313589 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 79333.333333 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 79333.333333 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72789.707187 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 72789.707187 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72794.058967 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 72794.058967 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 36911 # number of replacements -system.cpu.icache.tags.tagsinuse 1924.852805 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 73041980 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 38848 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1880.199238 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 36873 # number of replacements +system.cpu.icache.tags.tagsinuse 1923.841153 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 72548906 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 38809 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1869.383545 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1924.852805 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.939870 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.939870 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1937 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 87 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 1923.841153 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.939376 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.939376 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1936 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 86 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 34 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 274 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1488 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.945801 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 146200506 # Number of tag accesses -system.cpu.icache.tags.data_accesses 146200506 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 73041980 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 73041980 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 73041980 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 73041980 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 73041980 # number of overall hits -system.cpu.icache.overall_hits::total 73041980 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 38849 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 38849 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 38849 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 38849 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 38849 # number of overall misses -system.cpu.icache.overall_misses::total 38849 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 726693000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 726693000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 726693000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 726693000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 726693000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 726693000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 73080829 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 73080829 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 73080829 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 73080829 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 73080829 # 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miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.088173 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.931944 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.175946 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.088162 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.176035 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.088173 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.931944 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.175946 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75710.056062 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75710.056062 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75219.416058 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75219.416058 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 76601.111111 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 76601.111111 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75219.416058 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75996.194101 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 75647.463626 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75219.416058 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75996.194101 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 75647.463626 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.176035 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75028.030834 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75028.030834 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75475.014611 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75475.014611 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77177.037037 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77177.037037 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75475.014611 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75718.125595 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75609.034881 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75475.014611 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75718.125595 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75609.034881 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -734,106 +734,106 @@ system.cpu.l2cache.overall_mshr_hits::cpu.data 42 system.cpu.l2cache.overall_mshr_hits::total 44 # number of overall MSHR hits system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2854 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 2854 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3423 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3423 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3420 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3420 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1308 # number of ReadSharedReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1308 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3423 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3420 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 4162 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 7585 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3423 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 7582 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3420 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 4162 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 7585 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 187536500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 187536500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 223262000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 223262000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 87309500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 87309500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 223262000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 274846000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 498108000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 223262000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 274846000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 498108000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::total 7582 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 185590000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 185590000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 223941000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 223941000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 88101000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 88101000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 223941000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 273691000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 497632000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 223941000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 273691000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 497632000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994425 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994425 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.088110 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.088110 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.088122 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.088122 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.797075 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.797075 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.088110 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.088122 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.922634 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.174931 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.088110 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.175019 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.088122 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922634 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.174931 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65710.056062 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65710.056062 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65224.072451 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65224.072451 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 66750.382263 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 66750.382263 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65224.072451 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66037.001442 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65670.138431 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65224.072451 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66037.001442 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65670.138431 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.175019 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65028.030834 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65028.030834 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65479.824561 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65479.824561 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67355.504587 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67355.504587 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65479.824561 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65759.490630 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65633.342126 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65479.824561 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65759.490630 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65633.342126 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadResp 40489 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 40450 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 1010 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 22221 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 22200 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 2870 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 2870 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 38849 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 38810 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 1641 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 99690 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 99591 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10260 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 109950 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2486272 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 109851 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2483776 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 353344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2839616 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2837120 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 81625 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 81548 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 81625 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 81548 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 81625 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 41822500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 81548 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 41784000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 58272998 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 58214498 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 6787458 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.trans_dist::ReadResp 4731 # Transaction distribution +system.membus.trans_dist::ReadResp 4728 # Transaction distribution system.membus.trans_dist::ReadExReq 2854 # Transaction distribution system.membus.trans_dist::ReadExResp 2854 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 4731 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15170 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 15170 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485440 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 485440 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 4728 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15164 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 15164 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485248 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 485248 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 7585 # Request fanout histogram +system.membus.snoop_fanout::samples 7582 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 7585 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 7582 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 7585 # Request fanout histogram -system.membus.reqLayer0.occupancy 8844500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 7582 # Request fanout histogram +system.membus.reqLayer0.occupancy 8861000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 40248250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 40238250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini index e201ba957..be385b04e 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini @@ -149,7 +149,7 @@ instShiftAmt=2 numThreads=1 [system.cpu.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -490,7 +490,7 @@ opLat=4 pipelined=true [system.cpu.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -600,7 +600,7 @@ sys=system port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] -type=BaseCache +type=Cache children=prefetcher tags addr_ranges=0:18446744073709551615 assoc=16 @@ -688,7 +688,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/eon +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/eon gid=100 input=cin kvmInSE=false diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout index 88cf501ca..cbd037166 100755 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout @@ -1,13 +1,14 @@ +Redirecting stdout to build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing/simout +Redirecting stderr to build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Apr 22 2015 10:58:25 -gem5 started Apr 22 2015 11:46:25 -gem5 executing on phenom -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing +gem5 compiled Sep 14 2015 23:29:19 +gem5 started Sep 15 2015 01:15:27 +gem5 executing on ribera.cs.wisc.edu +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second - 0: system.cpu.isa: ISA system set to: 0 0x2c9dca0 info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Eon, Version 1.1 @@ -15,4 +16,4 @@ info: Increasing stack size by one page. info: Increasing stack size by one page. info: Increasing stack size by one page. OO-style eon Time= 0.110000 -Exiting @ tick 112553814500 because target called exit() +Exiting @ tick 112687034500 because target called exit() diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout index 563fc0af8..a48a8bb5c 100755 --- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout @@ -1,17 +1,19 @@ +Redirecting stdout to build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic/simout +Redirecting stderr to build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2014 12:08:08 -gem5 started Jan 23 2014 17:27:26 -gem5 executing on u200540-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic +gem5 compiled Sep 14 2015 23:29:19 +gem5 started Sep 15 2015 00:56:31 +gem5 executing on ribera.cs.wisc.edu +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic + Global frequency set at 1000000000000 ticks per second - 0: system.cpu.isa: ISA system set to: 0 0x56d96c0 info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Eon, Version 1.1 info: Increasing stack size by one page. info: Increasing stack size by one page. info: Increasing stack size by one page. -OO-style eon Time= 0.210000 -Exiting @ tick 212344043000 because target called exit() +OO-style eon Time= 0.200000 +Exiting @ tick 201717314000 because target called exit() diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini index b055586ab..892e458ed 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini @@ -80,7 +80,7 @@ dcache_port=system.cpu.dcache.cpu_side icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -156,7 +156,7 @@ sys=system port=system.cpu.toL2Bus.slave[3] [system.cpu.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -266,7 +266,7 @@ sys=system port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=8 diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout b/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout index 9d7fb2434..d5cd58d2c 100755 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout @@ -1,17 +1,19 @@ +Redirecting stdout to build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing/simout +Redirecting stderr to build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2014 12:08:08 -gem5 started Jan 23 2014 17:29:04 -gem5 executing on u200540-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing +gem5 compiled Sep 14 2015 23:29:19 +gem5 started Sep 15 2015 03:56:42 +gem5 executing on ribera.cs.wisc.edu +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing + Global frequency set at 1000000000000 ticks per second - 0: system.cpu.isa: ISA system set to: 0 0x4c37d00 info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Eon, Version 1.1 info: Increasing stack size by one page. info: Increasing stack size by one page. info: Increasing stack size by one page. -OO-style eon Time= 0.520000 -Exiting @ tick 525834342000 because target called exit() +OO-style eon Time= 0.510000 +Exiting @ tick 517235407500 because target called exit() |