diff options
Diffstat (limited to 'tests/long/se/30.eon/ref/arm')
9 files changed, 176 insertions, 62 deletions
diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini index 1cf41a172..b166901dc 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini @@ -492,9 +492,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -525,9 +524,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout index f0a5e284e..fd4ba336e 100755 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:17:37 -gem5 started May 8 2012 16:35:18 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:14:06 +gem5 started Jun 4 2012 17:54:41 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index 969b86901..154ddb0a7 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -4,22 +4,29 @@ sim_seconds 0.071775 # Nu sim_ticks 71774859500 # Number of ticks simulated final_tick 71774859500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 69606 # Simulator instruction rate (inst/s) -host_op_rate 88987 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 18296996 # Simulator tick rate (ticks/s) -host_mem_usage 240272 # Number of bytes of host memory used -host_seconds 3922.77 # Real time elapsed on the host +host_inst_rate 120484 # Simulator instruction rate (inst/s) +host_op_rate 154032 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 31671128 # Simulator tick rate (ticks/s) +host_mem_usage 240520 # Number of bytes of host memory used +host_seconds 2266.26 # Real time elapsed on the host sim_insts 273048474 # Number of instructions simulated sim_ops 349076199 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 472896 # Number of bytes read from this memory -system.physmem.bytes_inst_read 199168 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 7389 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 6588602 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 2774899 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 6588602 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 199168 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 273728 # Number of bytes read from this memory +system.physmem.bytes_read::total 472896 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 199168 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 199168 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3112 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 4277 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7389 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2774899 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3813703 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6588602 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2774899 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2774899 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2774899 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3813703 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6588602 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -368,11 +375,17 @@ system.cpu.icache.demand_accesses::total 39951299 # nu system.cpu.icache.overall_accesses::cpu.inst 39951299 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 39951299 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000426 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000426 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000426 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000426 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000426 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000426 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 12404.519807 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 12404.519807 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 12404.519807 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 12404.519807 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 12404.519807 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 12404.519807 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -400,11 +413,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 139714000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 139714000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 139714000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000403 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000403 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000403 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000403 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000403 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000403 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8670.348765 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 8670.348765 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8670.348765 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 8670.348765 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8670.348765 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 8670.348765 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 1427 # number of replacements system.cpu.dcache.tagsinuse 3127.647604 # Cycle average of tags in use @@ -460,15 +479,25 @@ system.cpu.dcache.demand_accesses::total 172497310 # nu system.cpu.dcache.overall_accesses::cpu.data 172497310 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 172497310 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000040 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000040 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000238 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000238 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000143 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000143 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000134 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000134 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000134 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000134 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32138.410228 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 32138.410228 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33299.569848 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33299.569848 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 38000 # average LoadLockedReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 33118.913777 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 33118.913777 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 33118.913777 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 33118.913777 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 315000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -506,13 +535,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 156453500 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 156453500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 156453500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000020 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000020 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30396.733112 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30396.733112 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35546.727336 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35546.727336 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 33552.112374 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 33552.112374 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33552.112374 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 33552.112374 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 69 # number of replacements system.cpu.l2cache.tagsinuse 4034.301662 # Cycle average of tags in use @@ -581,19 +618,28 @@ system.cpu.l2cache.overall_accesses::cpu.data 4641 system.cpu.l2cache.overall_accesses::total 20733 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.194009 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.834903 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.258647 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994006 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.994006 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.194009 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.932127 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.359234 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.194009 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.932127 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.359234 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34267.136451 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34345.388188 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34292.611795 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34476.055339 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34476.055339 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34267.136451 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34430.536292 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34362.043502 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34267.136451 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34430.536292 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34362.043502 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -639,20 +685,30 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 133876000 system.cpu.l2cache.overall_mshr_miss_latency::total 230619500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.193388 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.807756 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.255350 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994006 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994006 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.193388 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.921569 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.356388 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.193388 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.921569 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.356388 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31087.242931 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31322.359396 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31162.253829 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31290.528556 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31290.528556 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31087.242931 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31301.379472 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31211.192313 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31087.242931 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31301.379472 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31211.192313 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini index 72280076c..796e4e4fa 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini @@ -112,9 +112,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout index 51d5089a3..80d4c141d 100755 --- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:17:37 -gem5 started May 8 2012 16:37:41 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:14:06 +gem5 started Jun 4 2012 18:01:26 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt index 30e59a4c3..1239fc01a 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt @@ -4,23 +4,35 @@ sim_seconds 0.212344 # Nu sim_ticks 212344048000 # Number of ticks simulated final_tick 212344048000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 841557 # Simulator instruction rate (inst/s) -host_op_rate 1075889 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 654486612 # Simulator tick rate (ticks/s) -host_mem_usage 228648 # Number of bytes of host memory used -host_seconds 324.44 # Real time elapsed on the host +host_inst_rate 1586428 # Simulator instruction rate (inst/s) +host_op_rate 2028172 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1233780581 # Simulator tick rate (ticks/s) +host_mem_usage 229108 # Number of bytes of host memory used +host_seconds 172.11 # Real time elapsed on the host sim_insts 273037671 # Number of instructions simulated sim_ops 349065408 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 1875350709 # Number of bytes read from this memory -system.physmem.bytes_inst_read 1394641440 # Number of instructions bytes read from this memory -system.physmem.bytes_written 400047783 # Number of bytes written to this memory -system.physmem.num_reads 443242866 # Number of read requests responded to by this memory -system.physmem.num_writes 82063572 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 8831661291 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 6567838624 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 1883960425 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 10715621716 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 1394641440 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 480709269 # Number of bytes read from this memory +system.physmem.bytes_read::total 1875350709 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1394641440 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1394641440 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 400047783 # Number of bytes written to this memory +system.physmem.bytes_written::total 400047783 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 348660360 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 94582506 # Number of read requests responded to by this memory +system.physmem.num_reads::total 443242866 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 82063572 # Number of write requests responded to by this memory +system.physmem.num_writes::total 82063572 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 6567838624 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2263822667 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 8831661291 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 6567838624 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 6567838624 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1883960425 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1883960425 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 6567838624 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4147783092 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 10715621716 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini index 28132d5a1..f88d3c19b 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini @@ -161,9 +161,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -194,9 +193,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout b/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout index 85721b4bd..02e894db6 100755 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:17:37 -gem5 started May 8 2012 16:38:02 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:14:06 +gem5 started Jun 4 2012 18:04:29 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt index 1725766a3..ce6e736cb 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt @@ -4,22 +4,29 @@ sim_seconds 0.525854 # Nu sim_ticks 525854475000 # Number of ticks simulated final_tick 525854475000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 425859 # Simulator instruction rate (inst/s) -host_op_rate 544445 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 821076045 # Simulator tick rate (ticks/s) -host_mem_usage 237820 # Number of bytes of host memory used -host_seconds 640.45 # Real time elapsed on the host +host_inst_rate 697015 # Simulator instruction rate (inst/s) +host_op_rate 891108 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1343878935 # Simulator tick rate (ticks/s) +host_mem_usage 238268 # Number of bytes of host memory used +host_seconds 391.30 # Real time elapsed on the host sim_insts 272739291 # Number of instructions simulated sim_ops 348687131 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 437312 # Number of bytes read from this memory -system.physmem.bytes_inst_read 167040 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 6833 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 831622 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 317654 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 831622 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 167040 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 270272 # Number of bytes read from this memory +system.physmem.bytes_read::total 437312 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 167040 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 167040 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 2610 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 4223 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6833 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 317654 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 513967 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 831622 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 317654 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 317654 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 317654 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 513967 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 831622 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -119,11 +126,17 @@ system.cpu.icache.demand_accesses::total 348660359 # nu system.cpu.icache.overall_accesses::cpu.inst 348660359 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 348660359 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000045 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000045 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000045 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000045 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000045 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21025.572005 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 21025.572005 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 21025.572005 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 21025.572005 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 21025.572005 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 21025.572005 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -145,11 +158,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 281253000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281253000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 281253000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000045 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18025.572005 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18025.572005 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18025.572005 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 18025.572005 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18025.572005 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 18025.572005 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 1332 # number of replacements system.cpu.dcache.tagsinuse 3078.396238 # Cycle average of tags in use @@ -201,13 +220,21 @@ system.cpu.dcache.demand_accesses::total 176624288 # nu system.cpu.dcache.overall_accesses::cpu.data 176624288 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 176624288 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000017 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000017 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000035 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000035 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49749.688667 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 49749.688667 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55766.016713 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55766.016713 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 53608.307280 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 53608.307280 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 53608.307280 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 53608.307280 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -235,13 +262,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 226624000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 226624000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 226624000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000017 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000017 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46749.688667 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46749.688667 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52766.016713 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52766.016713 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50608.307280 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 50608.307280 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50608.307280 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 50608.307280 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 48 # number of replacements system.cpu.l2cache.tagsinuse 3475.672922 # Cycle average of tags in use @@ -306,18 +341,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 4478 system.cpu.l2cache.overall_accesses::total 20081 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.167276 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.851183 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.231100 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994429 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.994429 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.167276 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.943055 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.340272 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.167276 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.943055 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.340272 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -350,18 +393,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 168920000 system.cpu.l2cache.overall_mshr_miss_latency::total 273320000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.167276 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.851183 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.231100 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994429 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994429 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.167276 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943055 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.340272 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.167276 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943055 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.340272 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |