diff options
Diffstat (limited to 'tests/long/se/30.eon/ref')
9 files changed, 1709 insertions, 1632 deletions
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini index d73c26c02..d18ed7c2f 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -29,7 +30,7 @@ system_port=system.membus.slave[0] [system.cpu] type=InOrderCPU -children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 RASSize=16 @@ -54,8 +55,6 @@ do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb fetchBuffSize=4 -functionTrace=false -functionTraceStart=0 function_trace=false function_trace_start=0 globalCtrBits=2 @@ -63,6 +62,7 @@ globalHistoryBits=13 globalPredictorSize=8192 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa itb=system.cpu.itb localCtrBits=2 localHistoryBits=11 @@ -76,7 +76,6 @@ memBlockSize=64 multLatency=1 multRepeatRate=1 numThreads=1 -phase=0 predType=tournament profile=0 progress_interval=0 @@ -94,20 +93,22 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=262144 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -123,20 +124,22 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=131072 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -146,6 +149,9 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=AlphaInterrupts +[system.cpu.isa] +type=AlphaISA + [system.cpu.itb] type=AlphaTLB size=48 @@ -153,22 +159,24 @@ size=48 [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=20 is_top_level=false -latency=10000 max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -178,10 +186,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -191,12 +199,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -cwd=build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/inorder-timing +cwd=build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/inorder-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon +executable=/projects/pd/randd/dist/cpu2000/binaries/alpha/tru64/eon gid=100 input=cin max_stack_size=67108864 @@ -214,18 +222,32 @@ clock=1000 header_cycles=1 use_default_range=false width=8 -master=system.physmem.port[0] +master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleMemory +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false -file= in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout index f78d992b7..063caa36a 100755 --- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout @@ -1,14 +1,14 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 08:30:56 -gem5 started Jul 2 2012 09:12:34 -gem5 executing on zizzer -command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/inorder-timing +gem5 compiled Oct 30 2012 11:02:14 +gem5 started Oct 30 2012 11:24:52 +gem5 executing on u200540-lin +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Eon, Version 1.1 info: Increasing stack size by one page. OO-style eon Time= 0.133333 -Exiting @ tick 141187061500 because target called exit() +Exiting @ tick 139846906500 because target called exit() diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt index a158074c5..1ee5829a5 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.141089 # Number of seconds simulated -sim_ticks 141089296500 # Number of ticks simulated -final_tick 141089296500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.139847 # Number of seconds simulated +sim_ticks 139846906500 # Number of ticks simulated +final_tick 139846906500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 83115 # Simulator instruction rate (inst/s) -host_op_rate 83115 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 29414893 # Simulator tick rate (ticks/s) -host_mem_usage 223012 # Number of bytes of host memory used -host_seconds 4796.53 # Real time elapsed on the host +host_inst_rate 122154 # Simulator instruction rate (inst/s) +host_op_rate 122154 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 42850332 # Simulator tick rate (ticks/s) +host_mem_usage 220236 # Number of bytes of host memory used +host_seconds 3263.61 # Real time elapsed on the host sim_insts 398664595 # Number of instructions simulated sim_ops 398664595 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 214976 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 214976 # Nu system.physmem.num_reads::cpu.inst 3359 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 3969 # Number of read requests responded to by this memory system.physmem.num_reads::total 7328 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1523688 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1800392 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3324079 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1523688 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1523688 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1523688 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1800392 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3324079 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1537224 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1816386 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3353610 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1537224 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1537224 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1537224 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1816386 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3353610 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 7328 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 7328 # Reqs generatd by CPU via cache - shady @@ -37,7 +37,7 @@ system.physmem.bytesConsumedWr 0 # by system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 465 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 464 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 465 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 518 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 520 # Track reads on a per bank basis system.physmem.perBankRdReqs::4 382 # Track reads on a per bank basis @@ -48,7 +48,7 @@ system.physmem.perBankRdReqs::8 407 # Tr system.physmem.perBankRdReqs::9 457 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 588 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 397 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 529 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 528 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 418 # Track reads on a per bank basis system.physmem.perBankRdReqs::14 396 # Track reads on a per bank basis system.physmem.perBankRdReqs::15 488 # Track reads on a per bank basis @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 141089244500 # Total gap between requests +system.physmem.totGap 139846854500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -98,11 +98,11 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 4661 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1890 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 520 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 190 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 66 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4654 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1888 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 524 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 196 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 65 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -164,47 +164,47 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 39617295 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 175175295 # Sum of mem lat for all requests +system.physmem.totQLat 39390791 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 174626791 # Sum of mem lat for all requests system.physmem.totBusLat 29312000 # Total cycles spent in databus access -system.physmem.totBankLat 106246000 # Total cycles spent in bank access -system.physmem.avgQLat 5406.29 # Average queueing delay per request -system.physmem.avgBankLat 14498.64 # Average bank access latency per request +system.physmem.totBankLat 105924000 # Total cycles spent in bank access +system.physmem.avgQLat 5375.38 # Average queueing delay per request +system.physmem.avgBankLat 14454.69 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 23904.93 # Average memory access latency -system.physmem.avgRdBW 3.32 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 23830.08 # Average memory access latency +system.physmem.avgRdBW 3.35 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 3.32 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 3.35 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 6442 # Number of row buffer hits during reads +system.physmem.readRowHits 6444 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.91 # Row buffer hit rate for reads +system.physmem.readRowHitRate 87.94 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 19253444.94 # Average gap between requests +system.physmem.avgGap 19083904.82 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 94754611 # DTB read hits +system.cpu.dtb.read_hits 94754613 # DTB read hits system.cpu.dtb.read_misses 21 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 94754632 # DTB read accesses -system.cpu.dtb.write_hits 73521102 # DTB write hits +system.cpu.dtb.read_accesses 94754634 # DTB read accesses +system.cpu.dtb.write_hits 73521103 # DTB write hits system.cpu.dtb.write_misses 35 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 73521137 # DTB write accesses -system.cpu.dtb.data_hits 168275713 # DTB hits +system.cpu.dtb.write_accesses 73521138 # DTB write accesses +system.cpu.dtb.data_hits 168275716 # DTB hits system.cpu.dtb.data_misses 56 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 168275769 # DTB accesses -system.cpu.itb.fetch_hits 49091192 # ITB hits -system.cpu.itb.fetch_misses 88817 # ITB misses +system.cpu.dtb.data_accesses 168275772 # DTB accesses +system.cpu.itb.fetch_hits 48611354 # ITB hits +system.cpu.itb.fetch_misses 44520 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 49180009 # ITB accesses +system.cpu.itb.fetch_accesses 48655874 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -218,42 +218,42 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 282178594 # number of cpu cycles simulated +system.cpu.numCycles 279693814 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 53863325 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 30909619 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 16029157 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 33388385 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 15622160 # Number of BTB hits +system.cpu.branch_predictor.lookups 53489670 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 30685393 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 15149659 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 32882351 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 15212538 # Number of BTB hits system.cpu.branch_predictor.usedRAS 8007516 # Number of times the RAS was used to get a target. -system.cpu.branch_predictor.RASInCorrect 19 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 46.789205 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 29654286 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 24209039 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 280812298 # Number of Reads from Int. Register File +system.cpu.branch_predictor.RASInCorrect 20 # Number of incorrect RAS predictions. +system.cpu.branch_predictor.BTBHitPct 46.263535 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 29230505 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 24259165 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 280386588 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 159335859 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 440148157 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 119908557 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 439722447 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 119631948 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 100196481 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 220105038 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 100451904 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 168699560 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 14461353 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 1567145 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 16028498 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 28559053 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 35.948370 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 205751378 # Number of Instructions Executed. -system.cpu.mult_div_unit.multiplies 2124332 # Number of Multipy Operations Executed +system.cpu.regfile_manager.floatRegFileAccesses 219828429 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 100484563 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 168485322 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 14315634 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 833366 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 15149000 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 29438551 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 33.975851 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 205475782 # Number of Instructions Executed. +system.cpu.mult_div_unit.multiplies 2124323 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 281883987 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 279400729 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 7632 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 13336617 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 268841977 # Number of cycles cpu stages are processed. -system.cpu.activity 95.273696 # Percentage of cycles cpu is active +system.cpu.timesIdled 7654 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 13387179 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 266306635 # Number of cycles cpu stages are processed. +system.cpu.activity 95.213631 # Percentage of cycles cpu is active system.cpu.comLoads 94754489 # Number of Load instructions committed system.cpu.comStores 73520729 # Number of Store instructions committed system.cpu.comBranches 44587532 # Number of Branches instructions committed @@ -265,245 +265,137 @@ system.cpu.committedInsts 398664595 # Nu system.cpu.committedOps 398664595 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 398664595 # Number of Instructions committed (Total) -system.cpu.cpi 0.707810 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.701577 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.707810 # CPI: Total CPI of All Threads -system.cpu.ipc 1.412809 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.701577 # CPI: Total CPI of All Threads +system.cpu.ipc 1.425361 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.412809 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 78396963 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 203781631 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 72.217254 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 108683745 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 173494849 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 61.484058 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 104474173 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 177704421 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 62.975869 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 183396585 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 98782009 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 35.006911 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 92487828 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 189690766 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 67.223656 # Percentage of cycles stage was utilized (processing insts). -system.cpu.icache.replacements 1982 # number of replacements -system.cpu.icache.tagsinuse 1831.235862 # Cycle average of tags in use -system.cpu.icache.total_refs 49086683 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 3910 # Sample count of references to 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(read+write) misses -system.cpu.icache.demand_misses::total 4508 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 4508 # number of overall misses -system.cpu.icache.overall_misses::total 4508 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 196984000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 196984000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 196984000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 196984000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 196984000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 196984000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 49091191 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 49091191 # number of ReadReq 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0.000093 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000093 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000093 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000093 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000093 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000093 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43365.542489 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 43365.542489 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 43365.542489 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 43365.542489 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 43365.542489 # average overall miss latency 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+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35919.490938 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35249.941352 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37197.660872 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 36304.867495 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35249.941352 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37197.660872 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 36304.867495 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 764 # number of replacements +system.cpu.dcache.tagsinuse 3285.615449 # Cycle average of tags in use +system.cpu.dcache.total_refs 168254423 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 40523.704961 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 3285.615449 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.802152 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.802152 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 94753185 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 94753185 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 73501238 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73501238 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 168254423 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168254423 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168254423 # number of overall hits +system.cpu.dcache.overall_hits::total 168254423 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1304 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1304 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 19491 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 19491 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 20795 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 20795 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 20795 # number of overall misses +system.cpu.dcache.overall_misses::total 20795 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 64310000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 64310000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 715525500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 715525500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 779835500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 779835500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 779835500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 779835500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 94754489 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 94754489 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 73520729 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 168275218 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 168275218 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 168275218 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 168275218 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000014 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000014 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000265 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000265 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000124 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000124 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000124 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000124 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49317.484663 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 49317.484663 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36710.558719 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 36710.558719 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 37501.106035 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 37501.106035 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 37501.106035 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 37501.106035 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 16708 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 535 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.229907 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 649 # number of writebacks +system.cpu.dcache.writebacks::total 649 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 354 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 354 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16289 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16289 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 16643 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 16643 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 16643 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 16643 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 950 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 950 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3202 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 3202 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4152 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 47442500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 47442500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 155739500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 155739500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 203182000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 203182000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 203182000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 203182000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000044 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49939.473684 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49939.473684 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48638.194878 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48638.194878 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48935.934489 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 48935.934489 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48935.934489 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 48935.934489 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini index 50694257d..8e356eaf5 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -29,7 +30,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -77,6 +78,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -95,7 +97,6 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 -phase=0 predType=tournament profile=0 progress_interval=0 @@ -129,16 +130,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=262144 subblock_size=0 system=system @@ -421,16 +424,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=131072 subblock_size=0 system=system @@ -444,6 +449,9 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=AlphaInterrupts +[system.cpu.isa] +type=AlphaISA + [system.cpu.itb] type=AlphaTLB size=48 @@ -451,22 +459,24 @@ size=48 [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=20 is_top_level=false -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -476,10 +486,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -489,12 +499,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -cwd=build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/o3-timing +cwd=build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon +executable=/projects/pd/randd/dist/cpu2000/binaries/alpha/tru64/eon gid=100 input=cin max_stack_size=67108864 @@ -512,18 +522,32 @@ clock=1000 header_cycles=1 use_default_range=false width=8 -master=system.physmem.port[0] +master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleMemory +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false -file= in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout index cf6e41473..c6043774f 100755 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout @@ -1,14 +1,14 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 08:30:56 -gem5 started Jul 2 2012 09:15:17 -gem5 executing on zizzer -command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/o3-timing +gem5 compiled Oct 30 2012 11:02:14 +gem5 started Oct 30 2012 11:29:31 +gem5 executing on u200540-lin +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Eon, Version 1.1 info: Increasing stack size by one page. OO-style eon Time= 0.066667 -Exiting @ tick 80362284000 because target called exit() +Exiting @ tick 77336466500 because target called exit() diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt index 698b9cfa0..d6188dabe 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.080478 # Number of seconds simulated -sim_ticks 80478305500 # Number of ticks simulated -final_tick 80478305500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.077336 # Number of seconds simulated +sim_ticks 77336466500 # Number of ticks simulated +final_tick 77336466500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 240864 # Simulator instruction rate (inst/s) -host_op_rate 240864 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 51612452 # Simulator tick rate (ticks/s) -host_mem_usage 224036 # Number of bytes of host memory used -host_seconds 1559.28 # Real time elapsed on the host +host_inst_rate 195499 # Simulator instruction rate (inst/s) +host_op_rate 195499 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 40256068 # Simulator tick rate (ticks/s) +host_mem_usage 221208 # Number of bytes of host memory used +host_seconds 1921.11 # Real time elapsed on the host sim_insts 375574808 # Number of instructions simulated sim_ops 375574808 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 222272 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 255360 # Number of bytes read from this memory -system.physmem.bytes_read::total 477632 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 222272 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 222272 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3473 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3990 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7463 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2761887 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3173029 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 5934916 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2761887 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2761887 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2761887 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3173029 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 5934916 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7463 # Total number of read requests seen +system.physmem.bytes_read::cpu.inst 220800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 255488 # Number of bytes read from this memory +system.physmem.bytes_read::total 476288 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 220800 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 220800 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3450 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3992 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7442 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2855057 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3303590 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6158647 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2855057 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2855057 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2855057 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3303590 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6158647 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7442 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 7463 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 477632 # Total number of bytes read from memory +system.physmem.cpureqs 7442 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 476288 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 477632 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 476288 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 488 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 483 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 481 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 480 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 530 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 529 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 388 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 386 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 401 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 460 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 447 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 457 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 448 # Track reads on a per bank basis system.physmem.perBankRdReqs::8 405 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 456 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 590 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 408 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 548 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 428 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 407 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 545 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 424 # Track reads on a per bank basis system.physmem.perBankRdReqs::14 399 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 503 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 504 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 80478237000 # Total gap between requests +system.physmem.totGap 77336398000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 7463 # Categorize read packet sizes +system.physmem.readPktSize::6 7442 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -98,10 +98,10 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 4283 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2068 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 746 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 275 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4251 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2073 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 754 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 273 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 88 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -164,47 +164,47 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 40041940 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 178323940 # Sum of mem lat for all requests -system.physmem.totBusLat 29852000 # Total cycles spent in databus access -system.physmem.totBankLat 108430000 # Total cycles spent in bank access -system.physmem.avgQLat 5365.39 # Average queueing delay per request -system.physmem.avgBankLat 14529.01 # Average bank access latency per request +system.physmem.totQLat 40921923 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 178783923 # Sum of mem lat for all requests +system.physmem.totBusLat 29768000 # Total cycles spent in databus access +system.physmem.totBankLat 108094000 # Total cycles spent in bank access +system.physmem.avgQLat 5498.78 # Average queueing delay per request +system.physmem.avgBankLat 14524.86 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 23894.40 # Average memory access latency -system.physmem.avgRdBW 5.93 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 24023.64 # Average memory access latency +system.physmem.avgRdBW 6.16 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 5.93 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 6.16 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 6524 # Number of row buffer hits during reads +system.physmem.readRowHits 6502 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.42 # Row buffer hit rate for reads +system.physmem.readRowHitRate 87.37 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 10783630.85 # Average gap between requests +system.physmem.avgGap 10391883.63 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 103426473 # DTB read hits -system.cpu.dtb.read_misses 88806 # DTB read misses -system.cpu.dtb.read_acv 48603 # DTB read access violations -system.cpu.dtb.read_accesses 103515279 # DTB read accesses -system.cpu.dtb.write_hits 79003400 # DTB write hits -system.cpu.dtb.write_misses 1622 # DTB write misses -system.cpu.dtb.write_acv 2 # DTB write access violations -system.cpu.dtb.write_accesses 79005022 # DTB write accesses -system.cpu.dtb.data_hits 182429873 # DTB hits -system.cpu.dtb.data_misses 90428 # DTB misses -system.cpu.dtb.data_acv 48605 # DTB access violations -system.cpu.dtb.data_accesses 182520301 # DTB accesses -system.cpu.itb.fetch_hits 52621913 # ITB hits -system.cpu.itb.fetch_misses 460 # ITB misses +system.cpu.dtb.read_hits 101791760 # DTB read hits +system.cpu.dtb.read_misses 77689 # DTB read misses +system.cpu.dtb.read_acv 48604 # DTB read access violations +system.cpu.dtb.read_accesses 101869449 # DTB read accesses +system.cpu.dtb.write_hits 78414713 # DTB write hits +system.cpu.dtb.write_misses 1485 # DTB write misses +system.cpu.dtb.write_acv 3 # DTB write access violations +system.cpu.dtb.write_accesses 78416198 # DTB write accesses +system.cpu.dtb.data_hits 180206473 # DTB hits +system.cpu.dtb.data_misses 79174 # DTB misses +system.cpu.dtb.data_acv 48607 # DTB access violations +system.cpu.dtb.data_accesses 180285647 # DTB accesses +system.cpu.itb.fetch_hits 50234226 # ITB hits +system.cpu.itb.fetch_misses 374 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 52622373 # ITB accesses +system.cpu.itb.fetch_accesses 50234600 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -218,246 +218,246 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 160956613 # number of cpu cycles simulated +system.cpu.numCycles 154672935 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 52100857 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 30315970 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1626186 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 28771875 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 24368935 # Number of BTB hits +system.cpu.BPredUnit.lookups 50254079 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 29238788 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1202354 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 26185724 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 23237791 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 9361706 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 1114 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 53696929 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 462928228 # Number of instructions fetch has processed -system.cpu.fetch.Branches 52100857 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 33730641 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 81620286 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 7858922 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 19257347 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 187 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 9632 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 29 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 52621913 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 634331 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 160777203 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.879315 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.313319 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 9009650 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 1041 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 51121474 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 448760218 # Number of instructions fetch has processed +system.cpu.fetch.Branches 50254079 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 32247441 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 78789768 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6120508 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 19691338 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 182 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 9175 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 31 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 50234226 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 409224 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 154491833 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.904750 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.325280 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 79156917 49.23% 49.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4375069 2.72% 51.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 7280350 4.53% 56.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 5649836 3.51% 60.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 12467952 7.75% 67.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 8098174 5.04% 72.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5694595 3.54% 76.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1921777 1.20% 77.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 36132533 22.47% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 75702065 49.00% 49.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4283300 2.77% 51.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 6877325 4.45% 56.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 5367764 3.47% 59.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 11752749 7.61% 67.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 7805511 5.05% 72.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5606089 3.63% 75.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1832349 1.19% 77.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 35264681 22.83% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 160777203 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.323695 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.876106 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 59247838 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 14720272 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 76811336 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3809242 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 6188515 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 9757922 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 4354 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 457314858 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 12387 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 6188515 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 62549995 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4761260 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 404034 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 77430709 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 9442690 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 451606730 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 77 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 23776 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 7810662 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 295220073 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 593857298 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 314533396 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 279323902 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 154491833 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.324905 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.901349 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 56470400 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 15041439 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 74166392 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3937938 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4875664 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 9475904 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 4278 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 444843868 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 12237 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4875664 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 59604786 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4871643 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 401502 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 75064420 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 9673818 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 440376827 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 86 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 19255 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 7994088 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 287328410 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 578957076 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 306311574 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 272645502 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259532329 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 35687744 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 38419 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 331 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 27285006 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 107056185 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 81810329 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 8900910 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 6383401 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 416688223 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 322 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 407927915 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1196295 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 40854151 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 20088069 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 107 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 160777203 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.537225 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.006885 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 27796081 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 36810 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 298 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 27798585 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 104665260 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 80564409 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 8907082 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 6393839 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 408148309 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 288 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 401749536 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 973581 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 32442077 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 15221672 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 73 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 154491833 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.600458 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.995634 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 32206126 20.03% 20.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 26582948 16.53% 36.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 26044704 16.20% 52.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 24850018 15.46% 68.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 21542644 13.40% 81.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15495200 9.64% 91.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8651076 5.38% 96.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 4083423 2.54% 99.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1321064 0.82% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 28272588 18.30% 18.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 25828142 16.72% 35.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 25544882 16.53% 51.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 24283906 15.72% 67.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 21283015 13.78% 81.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15483551 10.02% 91.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8467826 5.48% 96.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 4000243 2.59% 99.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1327680 0.86% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 160777203 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 154491833 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 35727 0.30% 0.30% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 0.30% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.30% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 75761 0.64% 0.94% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 4382 0.04% 0.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 3108 0.03% 1.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 1825209 15.42% 16.43% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 1783394 15.07% 31.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 31.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 31.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 31.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 31.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 31.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 31.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 31.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 31.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 31.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 31.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 31.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 31.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 31.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 31.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 31.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 31.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 31.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 31.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 31.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 31.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 31.49% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 5084367 42.96% 74.45% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3023635 25.55% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 34079 0.29% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 57868 0.49% 0.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 5831 0.05% 0.83% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 5354 0.05% 0.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 1930027 16.34% 17.21% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 1748928 14.81% 32.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 32.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 32.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.02% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 5061323 42.85% 74.87% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2967669 25.13% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 158069721 38.75% 38.76% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2126542 0.52% 39.28% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 39.28% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 33490518 8.21% 47.49% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 7849895 1.92% 49.41% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2841429 0.70% 50.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 16561983 4.06% 54.17% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 1589872 0.39% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 105338931 25.82% 80.38% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 80025443 19.62% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 155748072 38.77% 38.78% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2126114 0.53% 39.31% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 39.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 32812204 8.17% 47.47% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 7499410 1.87% 49.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2793875 0.70% 50.03% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 16556840 4.12% 54.16% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 1578743 0.39% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.55% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 103369723 25.73% 80.28% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 79230974 19.72% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 407927915 # Type of FU issued -system.cpu.iq.rate 2.534397 # Inst issue rate -system.cpu.iq.fu_busy_cnt 11835583 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.029014 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 648317888 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 270248085 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 237722545 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 341347023 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 187344847 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 162957273 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 245426205 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 174303712 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 14794032 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 401749536 # Type of FU issued +system.cpu.iq.rate 2.597413 # Inst issue rate +system.cpu.iq.fu_busy_cnt 11811079 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.029399 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 634008068 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 260192564 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 234721556 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 336767497 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 180447135 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 161345688 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 241449037 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 172077997 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 15060402 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 12301698 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 125436 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 50278 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 8289600 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 9910773 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 111367 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 49045 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 7043680 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 260794 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 2630 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 260907 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 2589 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 6188515 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2498531 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 365597 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 441640864 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 208656 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 107056185 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 81810329 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 322 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 105 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 92 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 50278 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1277121 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 568437 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1845558 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 403336755 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 103563942 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 4591160 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4875664 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2512017 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 367237 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 432932337 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 125430 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 104665260 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 80564409 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 288 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 91 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 94 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 49045 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 948042 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 404840 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1352882 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 398223090 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 101918095 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3526446 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 24952319 # number of nop insts executed -system.cpu.iew.exec_refs 182568992 # number of memory reference insts executed -system.cpu.iew.exec_branches 47207101 # Number of branches executed -system.cpu.iew.exec_stores 79005050 # Number of stores executed -system.cpu.iew.exec_rate 2.505873 # Inst execution rate -system.cpu.iew.wb_sent 401526892 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 400679818 # cumulative count of insts written-back -system.cpu.iew.wb_producers 195200441 # num instructions producing a value -system.cpu.iew.wb_consumers 273221552 # num instructions consuming a value +system.cpu.iew.exec_nop 24783740 # number of nop insts executed +system.cpu.iew.exec_refs 180334326 # number of memory reference insts executed +system.cpu.iew.exec_branches 46552042 # Number of branches executed +system.cpu.iew.exec_stores 78416231 # Number of stores executed +system.cpu.iew.exec_rate 2.574614 # Inst execution rate +system.cpu.iew.wb_sent 396695169 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 396067244 # cumulative count of insts written-back +system.cpu.iew.wb_producers 193570018 # num instructions producing a value +system.cpu.iew.wb_consumers 271138332 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.489365 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.714440 # average fanout of values written-back +system.cpu.iew.wb_rate 2.560676 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.713916 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 43021782 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 34296903 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1621908 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 154588688 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.578873 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.965339 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1198153 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 149616169 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.664582 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.996061 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 58995602 38.16% 38.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 23401293 15.14% 53.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13308874 8.61% 61.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11694068 7.56% 69.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 8446337 5.46% 74.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 5505575 3.56% 78.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 5146283 3.33% 81.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3352831 2.17% 84.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 24737825 16.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 55282421 36.95% 36.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 22517619 15.05% 52.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13057157 8.73% 60.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11465050 7.66% 68.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 8178831 5.47% 73.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 5460295 3.65% 77.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 5171821 3.46% 80.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3274025 2.19% 83.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 25208950 16.85% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 154588688 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 149616169 # Number of insts commited each cycle system.cpu.commit.committedInsts 398664583 # Number of instructions committed system.cpu.commit.committedOps 398664583 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -468,204 +468,340 @@ system.cpu.commit.branches 44587533 # Nu system.cpu.commit.fp_insts 155295106 # Number of committed floating point instructions. system.cpu.commit.int_insts 316365839 # Number of committed integer instructions. system.cpu.commit.function_calls 8007752 # Number of function calls committed. -system.cpu.commit.bw_lim_events 24737825 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 25208950 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 571534251 # The number of ROB reads -system.cpu.rob.rob_writes 889574996 # The number of ROB writes -system.cpu.timesIdled 3393 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 179410 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 557365728 # The number of ROB reads +system.cpu.rob.rob_writes 870806965 # The number of ROB writes +system.cpu.timesIdled 3403 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 181102 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 375574808 # Number of Instructions Simulated system.cpu.committedOps 375574808 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 375574808 # Number of Instructions Simulated -system.cpu.cpi 0.428561 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.428561 # CPI: Total CPI of All Threads -system.cpu.ipc 2.333392 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.333392 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 402843963 # number of integer regfile reads -system.cpu.int_regfile_writes 172601197 # number of integer regfile writes -system.cpu.fp_regfile_reads 158371131 # number of floating regfile reads -system.cpu.fp_regfile_writes 105217877 # number of floating regfile writes +system.cpu.cpi 0.411830 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.411830 # CPI: Total CPI of All Threads +system.cpu.ipc 2.428187 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.428187 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 398054965 # number of integer regfile reads +system.cpu.int_regfile_writes 170113807 # number of integer regfile writes +system.cpu.fp_regfile_reads 156515246 # number of floating regfile reads +system.cpu.fp_regfile_writes 104037972 # number of floating regfile writes system.cpu.misc_regfile_reads 350572 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 2196 # number of replacements -system.cpu.icache.tagsinuse 1834.742216 # Cycle average of tags in use -system.cpu.icache.total_refs 52616364 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 4124 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 12758.575170 # Average number of references to valid blocks. +system.cpu.icache.replacements 2129 # number of replacements +system.cpu.icache.tagsinuse 1832.082194 # Cycle average of tags in use +system.cpu.icache.total_refs 50228789 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 4056 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 12383.823718 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1834.742216 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.895870 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.895870 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 52616364 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 52616364 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 52616364 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 52616364 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 52616364 # number of overall hits -system.cpu.icache.overall_hits::total 52616364 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5549 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5549 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5549 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5549 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5549 # number of overall misses -system.cpu.icache.overall_misses::total 5549 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 228035499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 228035499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 228035499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 228035499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 228035499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 228035499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 52621913 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 52621913 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 52621913 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 52621913 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 52621913 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 52621913 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000105 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000105 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000105 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000105 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000105 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000105 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41094.881781 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 41094.881781 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 41094.881781 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 41094.881781 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 41094.881781 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 41094.881781 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 278 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1832.082194 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.894571 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.894571 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 50228789 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 50228789 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 50228789 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 50228789 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 50228789 # number of overall hits +system.cpu.icache.overall_hits::total 50228789 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5437 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5437 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5437 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5437 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5437 # number of overall misses +system.cpu.icache.overall_misses::total 5437 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 226400000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 226400000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 226400000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 226400000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 226400000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 226400000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 50234226 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 50234226 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 50234226 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 50234226 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 50234226 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 50234226 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000108 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000108 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000108 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000108 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000108 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000108 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41640.610631 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 41640.610631 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 41640.610631 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 41640.610631 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 41640.610631 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 41640.610631 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 238 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 46.333333 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 59.500000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1425 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1425 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1425 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1425 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1425 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1425 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4124 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 4124 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 4124 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 4124 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 4124 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 4124 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 176594499 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 176594499 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 176594499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 176594499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 176594499 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 176594499 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000078 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000078 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000078 # mshr miss rate for demand accesses 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demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000081 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000081 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 43351.084813 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 43351.084813 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 43351.084813 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 43351.084813 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 43351.084813 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 43351.084813 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 785 # number of replacements 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replacements +system.cpu.dcache.tagsinuse 3297.205890 # Cycle average of tags in use +system.cpu.dcache.total_refs 159967351 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 4182 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 38251.399091 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3296.121228 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.804717 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.804717 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 88367648 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 88367648 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73500876 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73500876 # number of WriteReq hits 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# number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 206315000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 206315000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 206315000 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 657 # number of writebacks +system.cpu.dcache.writebacks::total 657 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 819 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 819 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16676 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16676 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 17495 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 17495 # number of demand (read+write) MSHR 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+system.cpu.dcache.ReadReq_mshr_miss_latency::total 51550500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 155023000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 155023000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 206573500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 206573500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 206573500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 206573500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000011 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for WriteReq accesses @@ -674,150 +810,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000026 system.cpu.dcache.demand_mshr_miss_rate::total 0.000026 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000026 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000026 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51669.028340 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51669.028340 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48566.155771 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48566.155771 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49298.685783 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 49298.685783 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49298.685783 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 49298.685783 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52018.668012 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52018.668012 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48581.322469 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48581.322469 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49395.863223 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 49395.863223 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49395.863223 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 49395.863223 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 4033.088389 # Cycle average of tags in use -system.cpu.l2cache.total_refs 872 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 4868 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.179129 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 372.600673 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 3001.103813 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 659.383903 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.011371 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.091586 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.020123 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.123080 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 651 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 130 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 781 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 663 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 663 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 65 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 65 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 651 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 195 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 846 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 651 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 195 # number of overall hits -system.cpu.l2cache.overall_hits::total 846 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3473 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 858 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 4331 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 3132 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 3132 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3473 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 3990 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 7463 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3473 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 3990 # number of overall misses -system.cpu.l2cache.overall_misses::total 7463 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 165942000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 48709500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 214651500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 151316000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 151316000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 165942000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 200025500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 365967500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 165942000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 200025500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 365967500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 4124 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 988 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 5112 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 663 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 663 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 3197 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 3197 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 4124 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 4185 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 8309 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 4124 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 4185 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 8309 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.842144 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.868421 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.847222 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.979668 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.979668 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.842144 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.953405 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.898183 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.842144 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.953405 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.898183 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47780.593147 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 56770.979021 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 49561.648580 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 48312.899106 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 48312.899106 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47780.593147 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 50131.704261 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 49037.585421 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47780.593147 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 50131.704261 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 49037.585421 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3473 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 858 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 4331 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3132 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 3132 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3473 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 3990 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 7463 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3473 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 3990 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 7463 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 122186799 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 38051999 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 160238798 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 112625004 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 112625004 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 122186799 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 150677003 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 272863802 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 122186799 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 150677003 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 272863802 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.842144 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.868421 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.847222 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.979668 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.979668 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.842144 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.953405 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.898183 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.842144 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.953405 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.898183 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35181.917363 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 44349.649184 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36998.106211 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35959.452107 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35959.452107 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35181.917363 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37763.659900 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 36562.213855 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35181.917363 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37763.659900 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 36562.213855 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini index ca4ea2a9a..f736a3c63 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a -clock=1 +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -30,7 +30,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -78,6 +78,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -129,18 +130,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=262144 subblock_size=0 system=system @@ -159,7 +160,7 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -432,18 +433,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=131072 subblock_size=0 system=system @@ -457,6 +458,23 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=ArmInterrupts +[system.cpu.isa] +type=ArmISA +fpsid=1090793632 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=3 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=4027589137 +id_pfr0=49 +id_pfr1=1 +midr=890224640 + [system.cpu.itb] type=ArmTLB children=walker @@ -465,7 +483,7 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -473,24 +491,24 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=20 is_top_level=false max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -500,10 +518,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port @@ -540,15 +558,28 @@ master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clock=1 +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout index 2e2e5579e..4b90608f0 100755 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 21 2012 11:19:00 -gem5 started Sep 21 2012 13:21:28 +gem5 compiled Oct 30 2012 11:20:14 +gem5 started Oct 30 2012 19:45:28 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -12,5 +12,5 @@ Eon, Version 1.1 info: Increasing stack size by one page. info: Increasing stack size by one page. info: Increasing stack size by one page. -OO-style eon Time= 0.070000 -Exiting @ tick 70907303500 because target called exit() +OO-style eon Time= 0.060000 +Exiting @ tick 68267465500 because target called exit() diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index d021c65df..e8af9a733 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.071124 # Number of seconds simulated -sim_ticks 71123520500 # Number of ticks simulated -final_tick 71123520500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.068267 # Number of seconds simulated +sim_ticks 68267465500 # Number of ticks simulated +final_tick 68267465500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 165652 # Simulator instruction rate (inst/s) -host_op_rate 211776 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 43149002 # Simulator tick rate (ticks/s) -host_mem_usage 241844 # Number of bytes of host memory used -host_seconds 1648.32 # Real time elapsed on the host -sim_insts 273048466 # Number of instructions simulated -sim_ops 349076190 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 194944 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 272832 # Number of bytes read from this memory -system.physmem.bytes_read::total 467776 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 194944 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 194944 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3046 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 4263 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7309 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2740922 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3836031 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6576952 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2740922 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2740922 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2740922 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3836031 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6576952 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7309 # Total number of read requests seen +host_inst_rate 130031 # Simulator instruction rate (inst/s) +host_op_rate 166236 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 32510221 # Simulator tick rate (ticks/s) +host_mem_usage 238756 # Number of bytes of host memory used +host_seconds 2099.88 # Real time elapsed on the host +sim_insts 273048375 # Number of instructions simulated +sim_ops 349076099 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 193920 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 273088 # Number of bytes read from this memory +system.physmem.bytes_read::total 467008 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 193920 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 193920 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3030 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 4267 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7297 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2840592 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 4000266 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6840857 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2840592 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2840592 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2840592 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4000266 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6840857 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7297 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 7309 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 467776 # Total number of bytes read from memory +system.physmem.cpureqs 7297 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 467008 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 467776 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 467008 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 346 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 470 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 344 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 467 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 514 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 578 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 477 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 456 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 440 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 507 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 480 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 494 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 484 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 551 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 365 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 581 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 475 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 457 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 437 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 505 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 483 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 495 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 481 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 558 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 359 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 416 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 368 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 363 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 365 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 360 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 71123348000 # Total gap between requests +system.physmem.totGap 68267282000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 7309 # Categorize read packet sizes +system.physmem.readPktSize::6 7297 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -98,12 +98,12 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 4384 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2130 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 552 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 174 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 67 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4347 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2135 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 568 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 183 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 64 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -164,27 +164,27 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 38077286 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 170549286 # Sum of mem lat for all requests -system.physmem.totBusLat 29236000 # Total cycles spent in databus access -system.physmem.totBankLat 103236000 # Total cycles spent in bank access -system.physmem.avgQLat 5209.64 # Average queueing delay per request -system.physmem.avgBankLat 14124.50 # Average bank access latency per request +system.physmem.totQLat 36802775 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 167840775 # Sum of mem lat for all requests +system.physmem.totBusLat 29188000 # Total cycles spent in databus access +system.physmem.totBankLat 101850000 # Total cycles spent in bank access +system.physmem.avgQLat 5043.55 # Average queueing delay per request +system.physmem.avgBankLat 13957.79 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 23334.15 # Average memory access latency -system.physmem.avgRdBW 6.58 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 23001.34 # Average memory access latency +system.physmem.avgRdBW 6.84 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 6.58 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 6.84 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 6380 # Number of row buffer hits during reads +system.physmem.readRowHits 6392 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.29 # Row buffer hit rate for reads +system.physmem.readRowHitRate 87.60 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 9730927.35 # Average gap between requests +system.physmem.avgGap 9355527.20 # Average gap between requests system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -228,108 +228,108 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 142247042 # number of cpu cycles simulated +system.cpu.numCycles 136534932 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 43100384 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 21816758 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 2115490 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 28214597 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 17877846 # Number of BTB hits +system.cpu.BPredUnit.lookups 41739250 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 21065104 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1640413 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 26027262 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 16735646 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 6960493 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 7483 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 41104486 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 329097721 # Number of instructions fetch has processed -system.cpu.fetch.Branches 43100384 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 24838339 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 73741038 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 8424830 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 20890852 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 101 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 3376 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 52 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 39439386 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 697861 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 142038328 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.976886 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.453881 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 6736138 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 7270 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 38860071 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 317518566 # Number of instructions fetch has processed +system.cpu.fetch.Branches 41739250 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 23471784 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 70794265 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6760095 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 21559516 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 34 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1854 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 30 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 37487912 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 519564 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 136324280 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.989165 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.456365 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 68979513 48.56% 48.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 7395782 5.21% 53.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 5795573 4.08% 57.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 6270161 4.41% 62.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4963047 3.49% 65.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4315752 3.04% 68.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3304919 2.33% 71.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 4334607 3.05% 74.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 36678974 25.82% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 66156807 48.53% 48.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 6761816 4.96% 53.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 5641032 4.14% 57.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 6022575 4.42% 62.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4881557 3.58% 65.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4156543 3.05% 68.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3204825 2.35% 71.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4146681 3.04% 74.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 35352444 25.93% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 142038328 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.302997 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.313565 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 47965638 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 16109831 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 69363004 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 2371211 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 6228644 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 7501471 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 70557 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 414890822 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 218836 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 6228644 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 53736634 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1580220 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 347679 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 65886950 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 14258201 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 404388597 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 136 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1669522 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 10203430 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 860 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 443737755 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2388674830 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1302452182 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1086222648 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 384584986 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 59152769 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 14467 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 14465 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 35681480 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 105493757 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 93214934 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 4606734 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5678105 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 392069014 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 25544 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 378019437 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1377395 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 42071369 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 110527513 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1062 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 142038328 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.661390 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.043453 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 136324280 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.305704 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.325548 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 45389084 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 16729555 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 66615921 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 2549925 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 5039795 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 7269016 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 69099 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 401164000 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 213330 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 5039795 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 50891753 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1911896 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 347462 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 63595531 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 14537843 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 393365757 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 50 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1668272 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 10291112 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 1086 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 431881386 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2329985493 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1257436076 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1072549417 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 384584833 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 47296553 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 14334 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 14333 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 36353497 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 103432229 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 91356063 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 4280154 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5359345 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 383896453 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 25411 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 373948163 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1224653 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 34098402 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 84823076 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 961 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 136324280 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.743078 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.023492 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 29008018 20.42% 20.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 20551186 14.47% 34.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 20935508 14.74% 49.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 18224796 12.83% 62.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 24071271 16.95% 79.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15985787 11.25% 90.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 9045864 6.37% 97.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3293540 2.32% 99.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 922358 0.65% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 24852306 18.23% 18.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 19962410 14.64% 32.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 20554570 15.08% 47.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 18105177 13.28% 61.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 23977307 17.59% 78.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15767707 11.57% 90.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8831817 6.48% 96.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3361471 2.47% 99.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 911515 0.67% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 142038328 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 136324280 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9132 0.05% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 4698 0.03% 0.08% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 8956 0.05% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 4688 0.03% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.08% # attempts to use FU when none available @@ -348,349 +348,494 @@ system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.08% # at system.cpu.iq.fu_full::SimdShift 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 45614 0.25% 0.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 7807 0.04% 0.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 399 0.00% 0.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 3 0.00% 0.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 193826 1.08% 1.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 4889 0.03% 1.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 240972 1.34% 2.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.82% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9466915 52.66% 55.48% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 8004617 44.52% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 46185 0.26% 0.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 7671 0.04% 0.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 470 0.00% 0.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 2 0.00% 0.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 190051 1.07% 1.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 6041 0.03% 1.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 241741 1.36% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9330966 52.43% 55.27% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 7960919 44.73% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 128267116 33.93% 33.93% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2174674 0.58% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 6840592 1.81% 36.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 8692743 2.30% 38.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 3457219 0.91% 39.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1621907 0.43% 39.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 21346208 5.65% 45.61% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 7171870 1.90% 47.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 7135741 1.89% 49.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 49.44% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 102459140 27.10% 76.54% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 88676941 23.46% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 126153074 33.74% 33.74% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2174128 0.58% 34.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 34.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 6786226 1.81% 36.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 8470375 2.27% 38.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 3426412 0.92% 39.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1600673 0.43% 39.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 20911148 5.59% 45.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 7171927 1.92% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 7134560 1.91% 49.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 49.21% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 101505429 27.14% 76.35% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 88438925 23.65% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 378019437 # Type of FU issued -system.cpu.iq.rate 2.657485 # Inst issue rate -system.cpu.iq.fu_busy_cnt 17978872 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.047561 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 666289235 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 301587031 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 252300909 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 251144234 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 132592793 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 118832927 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 266512180 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 129486129 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 10875090 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 373948163 # Type of FU issued +system.cpu.iq.rate 2.738846 # Inst issue rate +system.cpu.iq.fu_busy_cnt 17797690 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.047594 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 653530496 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 287597541 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 249877083 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 249712453 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 130436942 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 118161488 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 262975786 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 128770067 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 11107823 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 10842660 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 119827 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14278 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 10836994 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 8781151 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 113920 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14326 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 8978150 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 19866 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1167 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 176383 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1158 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 6228644 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 80063 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 4890 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 392103714 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1113019 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 105493757 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 93214934 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 14372 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 353 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 361 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14278 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1696490 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 500488 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 2196978 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 373371007 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 101101213 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 4648430 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 5039795 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 281091 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 41482 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 383923458 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 951525 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 103432229 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 91356063 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 14236 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 345 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 384 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14326 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1283309 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 356464 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1639773 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 370071311 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 100289689 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3876852 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9156 # number of nop insts executed -system.cpu.iew.exec_refs 188456752 # number of memory reference insts executed -system.cpu.iew.exec_branches 38701393 # Number of branches executed -system.cpu.iew.exec_stores 87355539 # Number of stores executed -system.cpu.iew.exec_rate 2.624807 # Inst execution rate -system.cpu.iew.wb_sent 371934669 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 371133836 # cumulative count of insts written-back -system.cpu.iew.wb_producers 184775670 # num instructions producing a value -system.cpu.iew.wb_consumers 367646771 # num instructions consuming a value +system.cpu.iew.exec_nop 1594 # number of nop insts executed +system.cpu.iew.exec_refs 187642898 # number of memory reference insts executed +system.cpu.iew.exec_branches 38279004 # Number of branches executed +system.cpu.iew.exec_stores 87353209 # Number of stores executed +system.cpu.iew.exec_rate 2.710451 # Inst execution rate +system.cpu.iew.wb_sent 368702519 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 368038571 # cumulative count of insts written-back +system.cpu.iew.wb_producers 182991065 # num instructions producing a value +system.cpu.iew.wb_consumers 363891400 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.609079 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.502590 # average fanout of values written-back +system.cpu.iew.wb_rate 2.695563 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.502873 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 43027028 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 24482 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 2045711 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 135809685 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.570338 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.654112 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 34846819 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 24450 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 1571698 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 131284486 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.658933 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.660928 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 38417531 28.29% 28.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 29199317 21.50% 49.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13525216 9.96% 59.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11128430 8.19% 67.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 13789447 10.15% 78.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7275712 5.36% 83.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 3957925 2.91% 86.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3970991 2.92% 89.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 14545116 10.71% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 34526115 26.30% 26.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 28464962 21.68% 47.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13313072 10.14% 58.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11375196 8.66% 66.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 13798040 10.51% 77.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7398451 5.64% 82.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 3831320 2.92% 85.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3930958 2.99% 88.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 14646372 11.16% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 135809685 # Number of insts commited each cycle -system.cpu.commit.committedInsts 273049078 # Number of instructions committed -system.cpu.commit.committedOps 349076802 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 131284486 # Number of insts commited each cycle +system.cpu.commit.committedInsts 273048987 # Number of instructions committed +system.cpu.commit.committedOps 349076711 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 177029037 # Number of memory references committed -system.cpu.commit.loads 94651097 # Number of loads committed +system.cpu.commit.refs 177028991 # Number of memory references committed +system.cpu.commit.loads 94651078 # Number of loads committed system.cpu.commit.membars 11033 # Number of memory barriers committed -system.cpu.commit.branches 36549060 # Number of branches committed +system.cpu.commit.branches 36549040 # Number of branches committed system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions. -system.cpu.commit.int_insts 279594003 # Number of committed integer instructions. +system.cpu.commit.int_insts 279593931 # Number of committed integer instructions. system.cpu.commit.function_calls 6225112 # Number of function calls committed. -system.cpu.commit.bw_lim_events 14545116 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 14646372 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 513365876 # The number of ROB reads -system.cpu.rob.rob_writes 790440754 # The number of ROB writes -system.cpu.timesIdled 6359 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 208714 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 273048466 # Number of Instructions Simulated -system.cpu.committedOps 349076190 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 273048466 # Number of Instructions Simulated -system.cpu.cpi 0.520959 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.520959 # CPI: Total CPI of All Threads -system.cpu.ipc 1.919537 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.919537 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1783321389 # number of integer regfile reads -system.cpu.int_regfile_writes 236147934 # number of integer regfile writes -system.cpu.fp_regfile_reads 189806588 # number of floating regfile reads -system.cpu.fp_regfile_writes 133619756 # number of floating regfile writes -system.cpu.misc_regfile_reads 991070858 # number of misc regfile reads -system.cpu.misc_regfile_writes 34426479 # number of misc regfile writes -system.cpu.icache.replacements 14002 # number of replacements -system.cpu.icache.tagsinuse 1857.450296 # Cycle average of tags in use -system.cpu.icache.total_refs 39422164 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 15897 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 2479.849280 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 500559121 # The number of ROB reads +system.cpu.rob.rob_writes 772890927 # The number of ROB writes +system.cpu.timesIdled 6411 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 210652 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 273048375 # Number of Instructions Simulated +system.cpu.committedOps 349076099 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 273048375 # Number of Instructions Simulated +system.cpu.cpi 0.500039 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.500039 # CPI: Total CPI of All Threads +system.cpu.ipc 1.999843 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.999843 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1769305779 # number of integer regfile reads +system.cpu.int_regfile_writes 232713829 # number of integer regfile writes +system.cpu.fp_regfile_reads 188383123 # number of floating regfile reads +system.cpu.fp_regfile_writes 132609484 # number of floating regfile writes +system.cpu.misc_regfile_reads 973808735 # number of misc regfile reads +system.cpu.misc_regfile_writes 34426415 # number of misc regfile writes +system.cpu.icache.replacements 13908 # number of replacements +system.cpu.icache.tagsinuse 1849.811927 # Cycle average of tags in use +system.cpu.icache.total_refs 37470862 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 15795 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 2372.324280 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1857.450296 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.906958 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.906958 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 39422164 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 39422164 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 39422164 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 39422164 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 39422164 # number of overall hits -system.cpu.icache.overall_hits::total 39422164 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 17219 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 17219 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 17219 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 17219 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 17219 # number of overall misses -system.cpu.icache.overall_misses::total 17219 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 362034000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 362034000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 362034000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 362034000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 362034000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 362034000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 39439383 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 39439383 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 39439383 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 39439383 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 39439383 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 39439383 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000437 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000437 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000437 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000437 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000437 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000437 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21025.262791 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 21025.262791 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 21025.262791 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 21025.262791 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 21025.262791 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 21025.262791 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 660 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1849.811927 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.903228 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.903228 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 37470862 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 37470862 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 37470862 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 37470862 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 37470862 # number of overall hits +system.cpu.icache.overall_hits::total 37470862 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 17049 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 17049 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 17049 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 17049 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 17049 # number of overall misses +system.cpu.icache.overall_misses::total 17049 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 356549497 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 356549497 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 356549497 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 356549497 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 356549497 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 356549497 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 37487911 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 37487911 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 37487911 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 37487911 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 37487911 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 37487911 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000455 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000455 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000455 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000455 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000455 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000455 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20913.220541 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 20913.220541 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 20913.220541 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 20913.220541 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 20913.220541 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 20913.220541 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 585 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 15 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 19 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 44 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 30.789474 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1322 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1322 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1322 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1322 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1322 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1322 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15897 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 15897 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 15897 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 15897 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 15897 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 15897 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 295359000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 295359000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 295359000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 295359000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 295359000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 295359000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000403 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000403 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000403 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000403 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000403 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000403 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18579.543310 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18579.543310 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18579.543310 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 18579.543310 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18579.543310 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 18579.543310 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1254 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1254 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1254 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1254 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1254 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1254 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15795 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 15795 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 15795 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 15795 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 15795 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 15795 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 291702997 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 291702997 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 291702997 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 291702997 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 291702997 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 291702997 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000421 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000421 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000421 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000421 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000421 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000421 # mshr miss rate for overall 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0.000148 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000148 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000147 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000147 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000147 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000147 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40455.183452 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 40455.183452 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39020.440260 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 39020.440260 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40704.399407 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 40704.399407 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39423.502061 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 39423.502061 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 57500 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 57500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 39250.936823 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 39250.936823 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 39250.936823 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 39250.936823 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 13009 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 844 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 400 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 16 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 32.522500 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 52.750000 # average number of cycles each access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 39629.574297 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 39629.574297 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 39629.574297 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 39629.574297 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 13562 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 751 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 431 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 12 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.466357 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 62.583333 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1035 # number of writebacks -system.cpu.dcache.writebacks::total 1035 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2253 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2253 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18405 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 18405 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 1040 # number of writebacks +system.cpu.dcache.writebacks::total 1040 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2234 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2234 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18291 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 18291 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 20658 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 20658 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 20658 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 20658 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1808 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1808 # number of ReadReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 20525 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 20525 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 20525 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 20525 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1812 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1812 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2812 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 2812 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4620 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4620 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4620 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4620 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 79609500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 79609500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 131989000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 131989000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 211598500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 211598500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 211598500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 211598500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 4624 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4624 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4624 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4624 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 79757000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 79757000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 131966500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 131966500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 211723500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 211723500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 211723500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 211723500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000020 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000020 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000034 # mshr miss rate for WriteReq accesses @@ -699,159 +844,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 44031.803097 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 44031.803097 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46937.766714 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46937.766714 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45800.541126 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 45800.541126 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45800.541126 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 45800.541126 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 44016.004415 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 44016.004415 # average ReadReq mshr miss latency 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-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 94353475 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 111924644 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 149192671 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 261117315 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 111924644 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 149192671 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 261117315 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.191621 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.811843 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.254929 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.993957 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.993957 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.191621 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.922727 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.356259 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.191621 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922727 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.356259 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 36744.794485 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37381.865031 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36951.881232 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33745.878040 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33745.878040 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 36744.794485 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34997.107905 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 35725.450130 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 36744.794485 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34997.107905 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 35725.450130 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |