diff options
Diffstat (limited to 'tests/long/se/30.eon')
5 files changed, 1479 insertions, 1479 deletions
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt index c000798eb..63bbc9ea5 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.141187 # Number of seconds simulated -sim_ticks 141187061500 # Number of ticks simulated -final_tick 141187061500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.141181 # Number of seconds simulated +sim_ticks 141180939500 # Number of ticks simulated +final_tick 141180939500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 158597 # Simulator instruction rate (inst/s) -host_op_rate 158597 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 56167220 # Simulator tick rate (ticks/s) -host_mem_usage 225028 # Number of bytes of host memory used -host_seconds 2513.69 # Real time elapsed on the host +host_inst_rate 88431 # Simulator instruction rate (inst/s) +host_op_rate 88431 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 31316360 # Simulator tick rate (ticks/s) +host_mem_usage 225476 # Number of bytes of host memory used +host_seconds 4508.22 # Real time elapsed on the host sim_insts 398664595 # Number of instructions simulated sim_ops 398664595 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 214592 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 214592 # Nu system.physmem.num_reads::cpu.inst 3353 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 3969 # Number of read requests responded to by this memory system.physmem.num_reads::total 7322 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1519913 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1799145 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3319058 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1519913 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1519913 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1519913 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1799145 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3319058 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1519979 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1799223 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3319202 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1519979 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1519979 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1519979 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1799223 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3319202 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -35,18 +35,18 @@ system.cpu.dtb.read_hits 94755019 # DT system.cpu.dtb.read_misses 21 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations system.cpu.dtb.read_accesses 94755040 # DTB read accesses -system.cpu.dtb.write_hits 73522100 # DTB write hits +system.cpu.dtb.write_hits 73522102 # DTB write hits system.cpu.dtb.write_misses 35 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 73522135 # DTB write accesses -system.cpu.dtb.data_hits 168277119 # DTB hits +system.cpu.dtb.write_accesses 73522137 # DTB write accesses +system.cpu.dtb.data_hits 168277121 # DTB hits system.cpu.dtb.data_misses 56 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 168277175 # DTB accesses -system.cpu.itb.fetch_hits 49112134 # ITB hits -system.cpu.itb.fetch_misses 88783 # ITB misses +system.cpu.dtb.data_accesses 168277177 # DTB accesses +system.cpu.itb.fetch_hits 49111833 # ITB hits +system.cpu.itb.fetch_misses 88782 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 49200917 # ITB accesses +system.cpu.itb.fetch_accesses 49200615 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -60,42 +60,42 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 282374124 # number of cpu cycles simulated +system.cpu.numCycles 282361880 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 53870034 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 30921446 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 16037248 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 33426490 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 15653868 # Number of BTB hits +system.cpu.branch_predictor.lookups 53870354 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 30921657 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 16037209 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 33426941 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 15653987 # Number of BTB hits system.cpu.branch_predictor.usedRAS 8007516 # Number of times the RAS was used to get a target. -system.cpu.branch_predictor.RASInCorrect 19 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 46.830726 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 29683710 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 24186324 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 280818505 # Number of Reads from Int. Register File +system.cpu.branch_predictor.RASInCorrect 18 # Number of incorrect RAS predictions. +system.cpu.branch_predictor.BTBHitPct 46.830450 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 29683846 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 24186508 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 280818440 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 159335859 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 440154364 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 119907678 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 440154299 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 119907695 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 100196481 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 220104159 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 100457715 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 168700471 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 14475138 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 1561451 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 16036589 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 28550962 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 35.966517 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 205751085 # Number of Instructions Executed. -system.cpu.mult_div_unit.multiplies 2124334 # Number of Multipy Operations Executed +system.cpu.regfile_manager.floatRegFileAccesses 220104176 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 100457653 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 168700458 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 14475221 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 1561329 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 16036550 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 28551001 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 35.966429 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 205750873 # Number of Instructions Executed. +system.cpu.mult_div_unit.multiplies 2124330 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 281932231 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 281927927 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 9236 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 13499283 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 268874841 # Number of cycles cpu stages are processed. -system.cpu.activity 95.219363 # Percentage of cycles cpu is active +system.cpu.timesIdled 8028 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 13487383 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 268874497 # Number of cycles cpu stages are processed. +system.cpu.activity 95.223370 # Percentage of cycles cpu is active system.cpu.comLoads 94754489 # Number of Load instructions committed system.cpu.comStores 73520729 # Number of Store instructions committed system.cpu.comBranches 44587532 # Number of Branches instructions committed @@ -107,72 +107,72 @@ system.cpu.committedInsts 398664595 # Nu system.cpu.committedOps 398664595 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 398664595 # Number of Instructions committed (Total) -system.cpu.cpi 0.708300 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.708269 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.708300 # CPI: Total CPI of All Threads -system.cpu.ipc 1.411831 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.708269 # CPI: Total CPI of All Threads +system.cpu.ipc 1.411892 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.411831 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 78560366 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 203813758 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 72.178624 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 108887705 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 173486419 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 61.438497 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 104664774 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 177709350 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 62.934007 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 183592728 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 98781396 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 34.982453 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 92681683 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 189692441 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 67.177700 # Percentage of cycles stage was utilized (processing insts). -system.cpu.icache.replacements 1973 # number of replacements -system.cpu.icache.tagsinuse 1829.856986 # Cycle average of tags in use -system.cpu.icache.total_refs 49107743 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 3900 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 12591.728974 # Average number of references to valid blocks. +system.cpu.ipc_total 1.411892 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 78547913 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 203813967 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 72.181828 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 108875170 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 173486710 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 61.441265 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 104652466 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 177709414 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 62.936758 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 183580459 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 98781421 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 34.983979 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 92669372 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 189692508 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 67.180636 # Percentage of cycles stage was utilized (processing insts). +system.cpu.icache.replacements 1974 # number of replacements +system.cpu.icache.tagsinuse 1829.872355 # Cycle average of tags in use +system.cpu.icache.total_refs 49107443 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 3901 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 12588.424250 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1829.856986 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.893485 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.893485 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 49107743 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 49107743 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 49107743 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 49107743 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 49107743 # number of overall hits -system.cpu.icache.overall_hits::total 49107743 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 4390 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 4390 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 4390 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 4390 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 4390 # number of overall misses -system.cpu.icache.overall_misses::total 4390 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 220305000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 220305000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 220305000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 220305000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 220305000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 220305000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 49112133 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 49112133 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 49112133 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 49112133 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 49112133 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 49112133 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 1829.872355 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.893492 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.893492 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 49107443 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 49107443 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 49107443 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 49107443 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 49107443 # number of overall hits +system.cpu.icache.overall_hits::total 49107443 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 4389 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 4389 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 4389 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 4389 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 4389 # number of overall misses +system.cpu.icache.overall_misses::total 4389 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 215239500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 215239500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 215239500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 215239500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 215239500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 215239500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 49111832 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 49111832 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 49111832 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 49111832 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 49111832 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 49111832 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000089 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000089 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000089 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000089 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000089 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000089 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 50183.371298 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 50183.371298 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 50183.371298 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 50183.371298 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 50183.371298 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 50183.371298 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49040.669856 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 49040.669856 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 49040.669856 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 49040.669856 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 49040.669856 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 49040.669856 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 45000 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -181,70 +181,70 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets 45000 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 490 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 490 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 490 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 490 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 490 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 490 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3900 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 3900 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 3900 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 3900 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 3900 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 3900 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 190927000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 190927000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 190927000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 190927000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 190927000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 190927000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 488 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 488 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 488 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 488 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 488 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 488 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3901 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 3901 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 3901 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 3901 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 3901 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 3901 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 190519000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 190519000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 190519000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 190519000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 190519000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 190519000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000079 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000079 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000079 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48955.641026 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48955.641026 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48955.641026 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 48955.641026 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48955.641026 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 48955.641026 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48838.502948 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48838.502948 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48838.502948 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 48838.502948 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48838.502948 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 48838.502948 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 764 # number of replacements -system.cpu.dcache.tagsinuse 3284.708505 # Cycle average of tags in use -system.cpu.dcache.total_refs 168261813 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 3284.744401 # Cycle average of tags in use +system.cpu.dcache.total_refs 168261808 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 40525.484827 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 40525.483622 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3284.708505 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.801931 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.801931 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 3284.744401 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.801940 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.801940 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 94753261 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 94753261 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73508552 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73508552 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 168261813 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168261813 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168261813 # number of overall hits -system.cpu.dcache.overall_hits::total 168261813 # number of overall hits +system.cpu.dcache.WriteReq_hits::cpu.data 73508547 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73508547 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 168261808 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168261808 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168261808 # number of overall hits +system.cpu.dcache.overall_hits::total 168261808 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 1228 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 1228 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 12177 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 12177 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 13405 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 13405 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 13405 # number of overall misses -system.cpu.dcache.overall_misses::total 13405 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 68612500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 68612500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 712613500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 712613500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 781226000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 781226000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 781226000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 781226000 # number of overall miss cycles +system.cpu.dcache.WriteReq_misses::cpu.data 12182 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 12182 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 13410 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 13410 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 13410 # number of overall misses +system.cpu.dcache.overall_misses::total 13410 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 65498000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 65498000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 641953000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 641953000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 707451000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 707451000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 707451000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 707451000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 94754489 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 94754489 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) @@ -261,32 +261,32 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000080 system.cpu.dcache.demand_miss_rate::total 0.000080 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000080 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000080 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55873.371336 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 55873.371336 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 58521.269607 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 58521.269607 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 58278.701977 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 58278.701977 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 58278.701977 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 58278.701977 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53337.133550 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 53337.133550 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52696.847808 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 52696.847808 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 52755.480984 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 52755.480984 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 52755.480984 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 52755.480984 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 86009500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 85964000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 1905 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 1907 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 45149.343832 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 45078.133193 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 649 # number of writebacks system.cpu.dcache.writebacks::total 649 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 278 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 278 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 8975 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 8975 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 9253 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 9253 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 9253 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 9253 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 8980 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 8980 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 9258 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 9258 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 9258 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 9258 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 950 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 950 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3202 # number of WriteReq MSHR misses @@ -295,14 +295,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4152 system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 48743500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 48743500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 176149500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 176149500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 224893000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 224893000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 224893000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 224893000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 48495500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 48495500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 175965000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 175965000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 224460500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 224460500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 224460500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 224460500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses @@ -311,41 +311,41 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51308.947368 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51308.947368 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 55012.336040 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 55012.336040 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 54164.980732 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 54164.980732 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54164.980732 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 54164.980732 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51047.894737 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51047.894737 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54954.715803 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54954.715803 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 54060.814066 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 54060.814066 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54060.814066 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 54060.814066 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 3900.249221 # Cycle average of tags in use -system.cpu.l2cache.total_refs 753 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 3900.293758 # Cycle average of tags in use +system.cpu.l2cache.total_refs 754 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 4711 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.159839 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.160051 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 370.495467 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2902.223601 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 627.530153 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 370.502388 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2902.254610 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 627.536760 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.011307 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.088569 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.088570 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.019151 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.119026 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 547 # number of ReadReq hits +system.cpu.l2cache.occ_percent::total 0.119028 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 548 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 123 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 670 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 671 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 649 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 649 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 60 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 60 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 547 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 548 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 183 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 730 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 547 # number of overall hits +system.cpu.l2cache.demand_hits::total 731 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 548 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 183 # number of overall hits -system.cpu.l2cache.overall_hits::total 730 # number of overall hits +system.cpu.l2cache.overall_hits::total 731 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 3353 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 824 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 4177 # number of ReadReq misses @@ -357,52 +357,52 @@ system.cpu.l2cache.demand_misses::total 7322 # nu system.cpu.l2cache.overall_misses::cpu.inst 3353 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 3969 # number of overall misses system.cpu.l2cache.overall_misses::total 7322 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 180755000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 45853500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 226608500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 171775500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 171775500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 180755000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 217629000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 398384000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 180755000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 217629000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 398384000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 3900 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 181079500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 46077000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 227156500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 172190500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 172190500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 181079500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 218267500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 399347000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 181079500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 218267500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 399347000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 3901 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 947 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 4847 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 4848 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 649 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 649 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 3205 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 3205 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 3900 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 3901 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 4152 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 8052 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 3900 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 8053 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 3901 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 4152 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 8052 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.859744 # miss rate for ReadReq accesses +system.cpu.l2cache.overall_accesses::total 8053 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.859523 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.870116 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.861770 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.861592 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.981279 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.981279 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.859744 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.859523 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.955925 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.909339 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.859744 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.909226 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.859523 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.955925 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.909339 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53908.440203 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55647.451456 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 54251.496289 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 54618.600954 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 54618.600954 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53908.440203 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54832.199546 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 54409.177820 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53908.440203 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54832.199546 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 54409.177820 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.909226 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 54005.219207 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55918.689320 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 54382.690927 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 54750.556439 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 54750.556439 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 54005.219207 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54993.071303 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 54540.699262 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 54005.219207 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54993.071303 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 54540.699262 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -422,39 +422,39 @@ system.cpu.l2cache.demand_mshr_misses::total 7322 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3353 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 3969 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7322 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 139951500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 35886500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 175838000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 133424000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 133424000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 139951500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 169310500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 309262000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 139951500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 169310500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 309262000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.859744 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 140250000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 36053500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 176303500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 133849000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 133849000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 140250000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 169902500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 310152500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 140250000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 169902500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 310152500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.859523 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.870116 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.861770 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.861592 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.981279 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.981279 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.859744 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.859523 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.909339 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.859744 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.909226 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.859523 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.909339 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41739.188786 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43551.577670 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42096.720134 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42424.165342 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42424.165342 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41739.188786 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42658.226253 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42237.366840 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41739.188786 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42658.226253 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42237.366840 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.909226 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41828.213540 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43754.247573 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42208.163754 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42559.300477 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42559.300477 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41828.213540 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42807.382212 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42358.986616 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41828.213540 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42807.382212 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42358.986616 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt index 33f2699f3..9ec4bfca0 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -1,52 +1,52 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.080362 # Number of seconds simulated -sim_ticks 80362284000 # Number of ticks simulated -final_tick 80362284000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.080354 # Number of seconds simulated +sim_ticks 80354154000 # Number of ticks simulated +final_tick 80354154000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 277812 # Simulator instruction rate (inst/s) -host_op_rate 277812 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 59443930 # Simulator tick rate (ticks/s) -host_mem_usage 226052 # Number of bytes of host memory used -host_seconds 1351.90 # Real time elapsed on the host +host_inst_rate 172564 # Simulator instruction rate (inst/s) +host_op_rate 172564 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 36920064 # Simulator tick rate (ticks/s) +host_mem_usage 226504 # Number of bytes of host memory used +host_seconds 2176.44 # Real time elapsed on the host sim_insts 375574808 # Number of instructions simulated sim_ops 375574808 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 222528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 255296 # Number of bytes read from this memory -system.physmem.bytes_read::total 477824 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 222528 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 222528 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3477 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3989 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7466 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2769060 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3176814 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 5945874 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2769060 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2769060 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2769060 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3176814 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 5945874 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 222976 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 255424 # Number of bytes read from this memory +system.physmem.bytes_read::total 478400 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 222976 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 222976 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3484 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3991 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7475 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2774916 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3178728 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 5953644 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2774916 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2774916 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2774916 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3178728 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 5953644 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 103417276 # DTB read hits -system.cpu.dtb.read_misses 89602 # DTB read misses +system.cpu.dtb.read_hits 103401614 # DTB read hits +system.cpu.dtb.read_misses 88552 # DTB read misses system.cpu.dtb.read_acv 48603 # DTB read access violations -system.cpu.dtb.read_accesses 103506878 # DTB read accesses -system.cpu.dtb.write_hits 79004376 # DTB write hits -system.cpu.dtb.write_misses 1630 # DTB write misses +system.cpu.dtb.read_accesses 103490166 # DTB read accesses +system.cpu.dtb.write_hits 79056152 # DTB write hits +system.cpu.dtb.write_misses 1601 # DTB write misses system.cpu.dtb.write_acv 2 # DTB write access violations -system.cpu.dtb.write_accesses 79006006 # DTB write accesses -system.cpu.dtb.data_hits 182421652 # DTB hits -system.cpu.dtb.data_misses 91232 # DTB misses +system.cpu.dtb.write_accesses 79057753 # DTB write accesses +system.cpu.dtb.data_hits 182457766 # DTB hits +system.cpu.dtb.data_misses 90153 # DTB misses system.cpu.dtb.data_acv 48605 # DTB access violations -system.cpu.dtb.data_accesses 182512884 # DTB accesses -system.cpu.itb.fetch_hits 52579177 # ITB hits -system.cpu.itb.fetch_misses 445 # ITB misses +system.cpu.dtb.data_accesses 182547919 # DTB accesses +system.cpu.itb.fetch_hits 52578444 # ITB hits +system.cpu.itb.fetch_misses 446 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 52579622 # ITB accesses +system.cpu.itb.fetch_accesses 52578890 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -60,146 +60,146 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 160724570 # number of cpu cycles simulated +system.cpu.numCycles 160708310 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 52097236 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 30296765 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1606699 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 28205553 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 24320024 # Number of BTB hits +system.cpu.BPredUnit.lookups 52055858 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 30270064 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1609565 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 28583053 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 24291253 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 9390300 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 1099 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 53639869 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 462587639 # Number of instructions fetch has processed -system.cpu.fetch.Branches 52097236 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 33710324 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 81534889 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 7793517 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 19277229 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 188 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 9332 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 52579177 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 630275 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 160609062 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.880209 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.314061 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 9363483 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 1125 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 53630506 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 462761975 # Number of instructions fetch has processed +system.cpu.fetch.Branches 52055858 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 33654736 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 81569260 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 7805922 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 19227823 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 182 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 8640 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 52578444 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 632985 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 160593743 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.881569 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.314206 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 79074173 49.23% 49.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4377828 2.73% 51.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 7270092 4.53% 56.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 5630004 3.51% 59.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 12402470 7.72% 67.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 8106533 5.05% 72.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5708692 3.55% 76.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1929242 1.20% 77.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 36110028 22.48% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 79024483 49.21% 49.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4373999 2.72% 51.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 7277585 4.53% 56.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 5624285 3.50% 59.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 12451588 7.75% 67.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 8090347 5.04% 72.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5701462 3.55% 76.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1906860 1.19% 77.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 36143134 22.51% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 160609062 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.324140 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.878139 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 59173788 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 14742505 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 76724469 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3825000 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 6143300 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 9747252 # Number of times decode resolved a branch +system.cpu.fetch.rateDist::total 160593743 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.323915 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.879515 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 59159628 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 14701180 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 76777373 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3802489 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 6153073 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 9767212 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 4329 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 457055568 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 12267 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 6143300 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 62453650 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4799000 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 401905 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 77381021 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 9430186 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 451385457 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 27 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 23697 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 7813364 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 295061939 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 593486774 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 314314250 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 279172524 # Number of floating rename lookups +system.cpu.decode.DecodedInsts 457201252 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 12277 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 6153073 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 62463630 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4784250 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 400809 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 77384574 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 9407407 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 451419869 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 14 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 20713 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 7782416 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 295098377 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 593658097 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 314398187 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 279259910 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259532329 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 35529610 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 38241 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 341 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 27266716 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 107002651 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 81768344 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 8923759 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 6384538 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 416452671 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 325 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 407888910 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1078553 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 40628099 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 19685259 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 110 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 160609062 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.539638 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.007756 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 35566048 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 38393 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 348 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 27305396 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 107006158 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 81864884 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 8914753 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 6402170 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 416586090 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 336 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 407940469 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1092011 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 40751586 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 19838559 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 121 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 160593743 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.540202 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.007855 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 32138937 20.01% 20.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 26538030 16.52% 36.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 25997150 16.19% 52.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 24815453 15.45% 68.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 21510440 13.39% 81.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15487887 9.64% 91.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8719479 5.43% 96.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 4101336 2.55% 99.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1300350 0.81% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 32107491 19.99% 19.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 26532573 16.52% 36.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 26024058 16.20% 52.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 24782303 15.43% 68.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 21577160 13.44% 81.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15465247 9.63% 91.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8675795 5.40% 96.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 4109702 2.56% 99.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1319414 0.82% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 160609062 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 160593743 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 35567 0.30% 0.30% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 35836 0.30% 0.30% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 0.30% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.30% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 73106 0.62% 0.92% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 5073 0.04% 0.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 3115 0.03% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 1847413 15.60% 16.59% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 1780061 15.04% 31.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 31.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 31.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 31.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 31.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 31.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 31.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 31.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 31.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 31.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 31.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 31.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 31.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 31.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 31.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 31.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 31.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 31.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 31.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 31.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 31.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 31.63% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 5074453 42.86% 74.49% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3020406 25.51% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 73145 0.62% 0.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 5467 0.05% 0.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 3221 0.03% 0.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 1851348 15.57% 16.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 1774625 14.92% 31.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 31.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 31.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 31.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 31.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 31.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 31.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 31.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 31.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 31.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 31.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 31.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 31.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 31.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 31.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 31.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 31.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 31.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 31.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 31.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 31.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 31.48% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 5106562 42.94% 74.43% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3040891 25.57% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 158124852 38.77% 38.77% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2126520 0.52% 39.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 39.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 33455961 8.20% 47.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 7846153 1.92% 49.42% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2842255 0.70% 50.12% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 16560349 4.06% 54.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 1591354 0.39% 54.57% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 158120657 38.76% 38.77% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2126534 0.52% 39.29% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 39.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 33463281 8.20% 47.49% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 7848056 1.92% 49.42% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2840409 0.70% 50.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 16567576 4.06% 54.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 1592675 0.39% 54.57% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.57% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.57% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.57% # Type of FU issued @@ -221,84 +221,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.57% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.57% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.57% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.57% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 105304781 25.82% 80.39% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 80003104 19.61% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 105294166 25.81% 80.38% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 80053534 19.62% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 407888910 # Type of FU issued -system.cpu.iq.rate 2.537813 # Inst issue rate -system.cpu.iq.fu_busy_cnt 11839194 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.029026 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 648060515 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 269929713 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 237794597 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 341244114 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 187202465 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 162943481 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 245434368 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 174260155 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 14844596 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 407940469 # Type of FU issued +system.cpu.iq.rate 2.538391 # Inst issue rate +system.cpu.iq.fu_busy_cnt 11891095 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.029149 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 648130283 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 270005016 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 237809508 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 341327504 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 187383841 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 162964934 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 245490516 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 174307467 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 14797790 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 12248164 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 129765 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 51115 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 8247615 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 12251671 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 123751 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 50882 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 8344155 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 260830 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 260839 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 3 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 6143300 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2503230 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 370145 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 441398780 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 177151 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 107002651 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 81768344 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 325 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 147 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 68 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 51115 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1257944 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 570703 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1828647 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 403351252 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 103555560 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 4537658 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 6153073 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2493888 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 367103 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 441513906 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 235069 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 107006158 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 81864884 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 336 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 120 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 76 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 50882 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1249323 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 568752 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1818075 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 403380721 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 103538845 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 4559748 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 24945784 # number of nop insts executed -system.cpu.iew.exec_refs 182561595 # number of memory reference insts executed -system.cpu.iew.exec_branches 47229945 # Number of branches executed -system.cpu.iew.exec_stores 79006035 # Number of stores executed -system.cpu.iew.exec_rate 2.509581 # Inst execution rate -system.cpu.iew.wb_sent 401565360 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 400738078 # cumulative count of insts written-back -system.cpu.iew.wb_producers 195225884 # num instructions producing a value -system.cpu.iew.wb_consumers 273294717 # num instructions consuming a value +system.cpu.iew.exec_nop 24927480 # number of nop insts executed +system.cpu.iew.exec_refs 182596628 # number of memory reference insts executed +system.cpu.iew.exec_branches 47226669 # Number of branches executed +system.cpu.iew.exec_stores 79057783 # Number of stores executed +system.cpu.iew.exec_rate 2.510018 # Inst execution rate +system.cpu.iew.wb_sent 401610425 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 400774442 # cumulative count of insts written-back +system.cpu.iew.wb_producers 195308199 # num instructions producing a value +system.cpu.iew.wb_consumers 273451305 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.493322 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.714342 # average fanout of values written-back +system.cpu.iew.wb_rate 2.493800 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.714234 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 42764408 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 42890401 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1602444 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 154465762 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.580925 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.966951 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1605306 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 154440670 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.581345 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.965853 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 58951255 38.16% 38.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 23354970 15.12% 53.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13285334 8.60% 61.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11679330 7.56% 69.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 8439151 5.46% 74.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 5483127 3.55% 78.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 5136953 3.33% 81.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3378138 2.19% 83.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 24757504 16.03% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 58870445 38.12% 38.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 23396206 15.15% 53.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13280012 8.60% 61.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11680215 7.56% 69.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 8466998 5.48% 74.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 5501467 3.56% 78.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 5150112 3.33% 81.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3370011 2.18% 83.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 24725204 16.01% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 154465762 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 154440670 # Number of insts commited each cycle system.cpu.commit.committedInsts 398664583 # Number of instructions committed system.cpu.commit.committedOps 398664583 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -309,70 +309,70 @@ system.cpu.commit.branches 44587533 # Nu system.cpu.commit.fp_insts 155295106 # Number of committed floating point instructions. system.cpu.commit.int_insts 316365839 # Number of committed integer instructions. system.cpu.commit.function_calls 8007752 # Number of function calls committed. -system.cpu.commit.bw_lim_events 24757504 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 24725204 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 571134272 # The number of ROB reads -system.cpu.rob.rob_writes 889015019 # The number of ROB writes -system.cpu.timesIdled 3240 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 115508 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 571267473 # The number of ROB reads +system.cpu.rob.rob_writes 889277309 # The number of ROB writes +system.cpu.timesIdled 3039 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 114567 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 375574808 # Number of Instructions Simulated system.cpu.committedOps 375574808 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 375574808 # Number of Instructions Simulated -system.cpu.cpi 0.427943 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.427943 # CPI: Total CPI of All Threads -system.cpu.ipc 2.336760 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.336760 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 402895481 # number of integer regfile reads -system.cpu.int_regfile_writes 172638002 # number of integer regfile writes -system.cpu.fp_regfile_reads 158340215 # number of floating regfile reads -system.cpu.fp_regfile_writes 105188641 # number of floating regfile writes +system.cpu.cpi 0.427900 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.427900 # CPI: Total CPI of All Threads +system.cpu.ipc 2.336997 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.336997 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 402957504 # number of integer regfile reads +system.cpu.int_regfile_writes 172619998 # number of integer regfile writes +system.cpu.fp_regfile_reads 158343155 # number of floating regfile reads +system.cpu.fp_regfile_writes 105226626 # number of floating regfile writes system.cpu.misc_regfile_reads 350572 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 2209 # number of replacements -system.cpu.icache.tagsinuse 1834.486163 # Cycle average of tags in use -system.cpu.icache.total_refs 52573796 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 4140 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 12698.984541 # Average number of references to valid blocks. +system.cpu.icache.replacements 2218 # number of replacements +system.cpu.icache.tagsinuse 1836.523631 # Cycle average of tags in use +system.cpu.icache.total_refs 52573018 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 4149 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 12671.250422 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1834.486163 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.895745 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.895745 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 52573796 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 52573796 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 52573796 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 52573796 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 52573796 # number of overall hits -system.cpu.icache.overall_hits::total 52573796 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5381 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5381 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5381 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5381 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5381 # number of overall misses -system.cpu.icache.overall_misses::total 5381 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 173584500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 173584500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 173584500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 173584500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 173584500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 173584500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 52579177 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 52579177 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 52579177 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 52579177 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 52579177 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 52579177 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000102 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000102 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000102 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000102 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000102 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000102 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 32258.780896 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 32258.780896 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 32258.780896 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 32258.780896 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 32258.780896 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 32258.780896 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1836.523631 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.896740 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.896740 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 52573018 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 52573018 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 52573018 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 52573018 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 52573018 # number of overall hits +system.cpu.icache.overall_hits::total 52573018 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5426 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5426 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5426 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5426 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5426 # number of overall misses +system.cpu.icache.overall_misses::total 5426 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 168571000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 168571000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 168571000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 168571000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 168571000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 168571000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 52578444 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 52578444 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 52578444 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 52578444 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 52578444 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 52578444 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000103 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000103 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000103 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000103 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000103 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000103 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 31067.268706 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 31067.268706 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 31067.268706 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 31067.268706 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 31067.268706 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 31067.268706 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -381,98 +381,98 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1241 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1241 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1241 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1241 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1241 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1241 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4140 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 4140 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 4140 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 4140 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 4140 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 4140 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 130333500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 130333500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 130333500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 130333500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 130333500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 130333500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1277 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1277 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1277 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1277 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1277 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1277 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4149 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 4149 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 4149 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 4149 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 4149 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 4149 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 129086500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 129086500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 129086500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 129086500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 129086500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 129086500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000079 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000079 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000079 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 31481.521739 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 31481.521739 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 31481.521739 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 31481.521739 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 31481.521739 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 31481.521739 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 31112.677754 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 31112.677754 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 31112.677754 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 31112.677754 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 31112.677754 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 31112.677754 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 796 # number of replacements -system.cpu.dcache.tagsinuse 3296.720309 # Cycle average of tags in use -system.cpu.dcache.total_refs 161811337 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 4197 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 38554.047415 # Average number of references to valid blocks. +system.cpu.dcache.replacements 788 # number of replacements +system.cpu.dcache.tagsinuse 3297.853996 # Cycle average of tags in use +system.cpu.dcache.total_refs 161841661 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 4190 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 38625.694749 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3296.720309 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.804863 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.804863 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 88310042 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 88310042 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73501280 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73501280 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 15 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 15 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 161811322 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 161811322 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 161811322 # number of overall hits -system.cpu.dcache.overall_hits::total 161811322 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1790 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1790 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 19449 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 19449 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 21239 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 21239 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 21239 # number of overall misses -system.cpu.dcache.overall_misses::total 21239 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 68481500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 68481500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 731423000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 731423000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 799904500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 799904500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 799904500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 799904500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 88311832 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 88311832 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::cpu.data 3297.853996 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.805140 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.805140 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 88341162 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 88341162 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 73500481 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73500481 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 18 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 18 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 161841643 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 161841643 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 161841643 # number of overall hits +system.cpu.dcache.overall_hits::total 161841643 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1802 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1802 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 20248 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 20248 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 22050 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 22050 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 22050 # number of overall misses +system.cpu.dcache.overall_misses::total 22050 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 62316500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 62316500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 625415500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 625415500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 687732000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 687732000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 687732000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 687732000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 88342964 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 88342964 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 73520729 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 15 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 161832561 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 161832561 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 161832561 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 161832561 # number of overall (read+write) accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 18 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 18 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 161863693 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 161863693 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 161863693 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 161863693 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000020 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000020 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000265 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000265 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000131 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000131 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000131 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000131 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 38257.821229 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 38257.821229 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37607.229163 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 37607.229163 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 37662.060361 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 37662.060361 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 37662.060361 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 37662.060361 # average overall miss latency +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000275 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000275 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000136 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000136 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000136 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000136 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34581.853496 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 34581.853496 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30887.766693 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 30887.766693 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31189.659864 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31189.659864 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31189.659864 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31189.659864 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 7500 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -481,32 +481,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs 7500 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 676 # number of writebacks -system.cpu.dcache.writebacks::total 676 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 798 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 798 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16244 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16244 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 17042 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 17042 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 17042 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 17042 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 992 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 992 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3205 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 3205 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4197 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4197 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4197 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4197 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36143000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 36143000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 129182000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 129182000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 165325000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 165325000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 165325000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 165325000 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 667 # number of writebacks +system.cpu.dcache.writebacks::total 667 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 813 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 813 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 17047 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 17047 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 17860 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 17860 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 17860 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 17860 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 989 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 989 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3201 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 3201 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4190 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4190 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4190 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4190 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 35672500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 35672500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 129053000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 129053000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 164725500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 164725500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 164725500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 164725500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000011 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses @@ -515,150 +515,150 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000026 system.cpu.dcache.demand_mshr_miss_rate::total 0.000026 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000026 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000026 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 36434.475806 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 36434.475806 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40306.396256 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40306.396256 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 39391.231832 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 39391.231832 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 39391.231832 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 39391.231832 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 36069.261881 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 36069.261881 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40316.463605 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40316.463605 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 39313.961814 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 112975000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 147757500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 260732500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.839720 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.868554 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.845271 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.978444 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.978444 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.839720 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.952506 # 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average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37022.676021 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34880.602007 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32426.808266 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37022.676021 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34880.602007 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt index df4992494..10dc822fe 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.567366 # Number of seconds simulated -sim_ticks 567365869000 # Number of ticks simulated -final_tick 567365869000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.567335 # Number of seconds simulated +sim_ticks 567335093000 # Number of ticks simulated +final_tick 567335093000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2066411 # Simulator instruction rate (inst/s) -host_op_rate 2066411 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2940844836 # Simulator tick rate (ticks/s) -host_mem_usage 224004 # Number of bytes of host memory used -host_seconds 192.93 # Real time elapsed on the host +host_inst_rate 1259990 # Simulator instruction rate (inst/s) +host_op_rate 1259990 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1793077476 # Simulator tick rate (ticks/s) +host_mem_usage 225476 # Number of bytes of host memory used +host_seconds 316.40 # Real time elapsed on the host sim_insts 398664609 # Number of instructions simulated sim_ops 398664609 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 205120 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 205120 # Nu system.physmem.num_reads::cpu.inst 3205 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 3969 # Number of read requests responded to by this memory system.physmem.num_reads::total 7174 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 361530 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 447711 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 809241 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 361530 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 361530 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 361530 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 447711 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 809241 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 361550 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 447735 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 809285 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 361550 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 361550 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 361550 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 447735 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 809285 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -60,7 +60,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 1134731738 # number of cpu cycles simulated +system.cpu.numCycles 1134670186 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 398664609 # Number of instructions committed @@ -79,18 +79,18 @@ system.cpu.num_mem_refs 168275276 # nu system.cpu.num_load_insts 94754511 # Number of load instructions system.cpu.num_store_insts 73520765 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 1134731738 # Number of busy cycles +system.cpu.num_busy_cycles 1134670186 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 1769 # number of replacements -system.cpu.icache.tagsinuse 1795.107538 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1795.138964 # Cycle average of tags in use system.cpu.icache.total_refs 398660993 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 3673 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 108538.250204 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1795.107538 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.876517 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.876517 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 1795.138964 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.876533 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.876533 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 398660993 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 398660993 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 398660993 # number of demand (read+write) hits @@ -103,12 +103,12 @@ system.cpu.icache.demand_misses::cpu.inst 3673 # n system.cpu.icache.demand_misses::total 3673 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 3673 # number of overall misses system.cpu.icache.overall_misses::total 3673 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 186108000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 186108000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 186108000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 186108000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 186108000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 186108000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 182359000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 182359000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 182359000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 182359000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 182359000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 182359000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 398664666 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 398664666 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 398664666 # number of demand (read+write) accesses @@ -121,12 +121,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000009 system.cpu.icache.demand_miss_rate::total 0.000009 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000009 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000009 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 50669.207732 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 50669.207732 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 50669.207732 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 50669.207732 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 50669.207732 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 50669.207732 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49648.516199 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 49648.516199 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 49648.516199 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 49648.516199 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 49648.516199 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 49648.516199 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -141,34 +141,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 3673 system.cpu.icache.demand_mshr_misses::total 3673 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 3673 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 3673 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 175089000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 175089000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 175089000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 175089000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 175089000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 175089000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 175013000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 175013000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 175013000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 175013000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 175013000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 175013000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000009 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000009 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 47669.207732 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 47669.207732 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 47669.207732 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 47669.207732 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47669.207732 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 47669.207732 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 47648.516199 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 47648.516199 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 47648.516199 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 47648.516199 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47648.516199 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 47648.516199 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 764 # number of replacements -system.cpu.dcache.tagsinuse 3288.859436 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 3288.930576 # Cycle average of tags in use system.cpu.dcache.total_refs 168271068 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 40527.713873 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3288.859436 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.802944 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.802944 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 3288.930576 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.802962 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.802962 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 94753540 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 94753540 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 73517528 # number of WriteReq hits @@ -185,14 +185,14 @@ system.cpu.dcache.demand_misses::cpu.data 4152 # n system.cpu.dcache.demand_misses::total 4152 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 4152 # number of overall misses system.cpu.dcache.overall_misses::total 4152 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 48094000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 48094000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 176797000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 176797000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 224891000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 224891000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 224891000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 224891000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 47084000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 47084000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 173590000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 173590000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 220674000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 220674000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 220674000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 220674000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 94754490 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 94754490 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520730 # number of WriteReq accesses(hits+misses) @@ -209,14 +209,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50625.263158 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 50625.263158 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55214.553404 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55214.553404 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 54164.499037 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 54164.499037 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 54164.499037 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 54164.499037 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49562.105263 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 49562.105263 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54212.991880 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54212.991880 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 53148.843931 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 53148.843931 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 53148.843931 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 53148.843931 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -235,14 +235,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4152 system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 45244000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 45244000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 167191000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 167191000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 212435000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 212435000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 212435000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 212435000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 45184000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 45184000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 167186000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 167186000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 212370000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 212370000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 212370000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 212370000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses @@ -251,28 +251,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47625.263158 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47625.263158 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52214.553404 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52214.553404 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51164.499037 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 51164.499037 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51164.499037 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 51164.499037 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47562.105263 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47562.105263 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52212.991880 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52212.991880 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51148.843931 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 51148.843931 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51148.843931 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 51148.843931 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 3772.396394 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 3772.485305 # Cycle average of tags in use system.cpu.l2cache.total_refs 674 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 4566 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.147613 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 371.526936 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2770.408528 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 630.460931 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.011338 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.084546 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.019240 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.115124 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 371.540221 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2770.469924 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 630.475161 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.011339 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.084548 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.019241 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.115127 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 468 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 123 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 591 # number of ReadReq hits diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index 57c2e3ca3..8292ba84e 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -1,32 +1,32 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.070907 # Number of seconds simulated -sim_ticks 70907303500 # Number of ticks simulated -final_tick 70907303500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.070882 # Number of seconds simulated +sim_ticks 70882487500 # Number of ticks simulated +final_tick 70882487500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 128530 # Simulator instruction rate (inst/s) -host_op_rate 164318 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 33377575 # Simulator tick rate (ticks/s) -host_mem_usage 237852 # Number of bytes of host memory used -host_seconds 2124.40 # Real time elapsed on the host -sim_insts 273048456 # Number of instructions simulated -sim_ops 349076180 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 194688 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 272448 # Number of bytes read from this memory -system.physmem.bytes_read::total 467136 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 194688 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 194688 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3042 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 4257 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7299 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2745669 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3842312 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6587981 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2745669 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2745669 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2745669 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3842312 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6587981 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 119635 # Simulator instruction rate (inst/s) +host_op_rate 152946 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 31056895 # Simulator tick rate (ticks/s) +host_mem_usage 243232 # Number of bytes of host memory used +host_seconds 2282.34 # Real time elapsed on the host +sim_insts 273048441 # Number of instructions simulated +sim_ops 349076165 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 194880 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 272768 # Number of bytes read from this memory +system.physmem.bytes_read::total 467648 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 194880 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 194880 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3045 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 4262 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7307 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2749339 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3848172 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6597511 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2749339 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2749339 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2749339 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3848172 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6597511 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -70,107 +70,107 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 141814608 # number of cpu cycles simulated +system.cpu.numCycles 141764976 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 43021564 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 21750711 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 2101631 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 27856122 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 17838153 # Number of BTB hits +system.cpu.BPredUnit.lookups 43022632 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 21746290 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 2100537 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 27784307 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 17845610 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 6966793 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 7520 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 40921334 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 328638556 # Number of instructions fetch has processed -system.cpu.fetch.Branches 43021564 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 24804946 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 73672457 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 8389816 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 20828697 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 32 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 3338 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 39391876 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 684935 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 141703595 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.981779 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.454940 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 6965581 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 7462 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 40878725 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 328721134 # Number of instructions fetch has processed +system.cpu.fetch.Branches 43022632 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 24811191 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 73667201 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 8391169 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 20823021 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 27 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 3522 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 39401519 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 692730 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 141652682 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.982295 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.454701 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 68712087 48.49% 48.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 7380491 5.21% 53.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 5816522 4.10% 57.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 6226633 4.39% 62.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4949598 3.49% 65.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4317646 3.05% 68.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3315601 2.34% 71.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 4325062 3.05% 74.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 36659955 25.87% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 68666188 48.48% 48.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 7372946 5.20% 53.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 5824782 4.11% 57.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 6228810 4.40% 62.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4953654 3.50% 65.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4319066 3.05% 68.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3319868 2.34% 71.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4326916 3.05% 74.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 36640452 25.87% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 141703595 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.303365 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.317382 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 47754995 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 16062481 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 69284862 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 2393411 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 6207846 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 7495010 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 70679 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 414601239 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 219868 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 6207846 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 53518393 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1558450 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 341275 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 65839797 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 14237834 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 404012192 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 94 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1667987 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 10221278 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 1168 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 443337202 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2387138833 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1300349332 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1086789501 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 384584970 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 58752232 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 14504 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 14503 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 35673328 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 105504454 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 93209227 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 4624259 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5728531 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 391940261 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 25587 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 377964584 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1402397 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 41905319 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 110211682 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1107 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 141703595 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.667290 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.042913 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 141652682 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.303479 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.318775 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 47724056 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 16047440 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 69280897 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 2389978 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 6210311 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 7496443 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 70615 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 414536105 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 220570 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 6210311 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 53491207 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1558118 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 338571 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 65828585 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 14225890 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 403967880 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 63 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1665803 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 10197275 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 723 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 443295910 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2386846444 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1300310044 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1086536400 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 384584946 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 58710964 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 14469 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 14467 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 35655672 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 105463248 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 93220202 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 4594940 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5698907 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 391915159 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 25548 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 378021086 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1395950 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 41892562 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 109796784 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1071 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 141652682 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.668648 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.042717 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 28741246 20.28% 20.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 20522205 14.48% 34.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 20900588 14.75% 49.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 18202387 12.85% 62.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 24092550 17.00% 79.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15957128 11.26% 90.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 9055746 6.39% 97.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3310234 2.34% 99.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 921511 0.65% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 28697410 20.26% 20.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 20492119 14.47% 34.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 20907256 14.76% 49.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 18207035 12.85% 62.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 24094157 17.01% 79.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15966233 11.27% 90.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 9051361 6.39% 97.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3319497 2.34% 99.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 917614 0.65% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 141703595 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 141652682 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9264 0.05% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 4697 0.03% 0.08% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 8869 0.05% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 4699 0.03% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.08% # attempts to use FU when none available @@ -189,22 +189,22 @@ system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.08% # at system.cpu.iq.fu_full::SimdShift 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 45902 0.26% 0.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 45720 0.25% 0.33% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 7808 0.04% 0.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 380 0.00% 0.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 7848 0.04% 0.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 429 0.00% 0.38% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatDiv 3 0.00% 0.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 193577 1.08% 1.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 5090 0.03% 1.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 240664 1.34% 2.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 193652 1.08% 1.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 4980 0.03% 1.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 240582 1.34% 2.82% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.82% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9480378 52.69% 55.51% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 8006063 44.49% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9467921 52.63% 55.44% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 8015707 44.56% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 128177934 33.91% 33.91% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2174662 0.58% 34.49% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 128195849 33.91% 33.91% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2174611 0.58% 34.49% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.49% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.49% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.49% # Type of FU issued @@ -223,167 +223,167 @@ system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.49% # Ty system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.49% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.49% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 6842006 1.81% 36.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 6839706 1.81% 36.30% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 8692020 2.30% 38.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 3461453 0.92% 39.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1621602 0.43% 39.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 21340607 5.65% 45.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 7172753 1.90% 47.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 7136617 1.89% 49.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 175287 0.05% 49.42% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 102440165 27.10% 76.52% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 88729478 23.48% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 8692181 2.30% 38.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 3465000 0.92% 39.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1622054 0.43% 39.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 21343322 5.65% 45.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 7172329 1.90% 47.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 7135364 1.89% 49.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 49.42% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 102447083 27.10% 76.52% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 88758301 23.48% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 377964584 # Type of FU issued -system.cpu.iq.rate 2.665202 # Inst issue rate -system.cpu.iq.fu_busy_cnt 17993826 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.047607 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 665793984 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 301139104 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 252255785 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 251235002 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 132745901 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 118864658 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 266433376 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 129525034 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 10838927 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 378021086 # Type of FU issued +system.cpu.iq.rate 2.666534 # Inst issue rate +system.cpu.iq.fu_busy_cnt 17990410 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.047591 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 665853263 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 301144367 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 252283124 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 251227951 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 132702727 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 118872712 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 266490153 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 129521343 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 10844694 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 10853359 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 121041 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14368 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 10831289 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 10812156 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 121101 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14360 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 10842267 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 20682 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 118 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 29815 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 119 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 6207846 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 63522 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 8302 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 391975437 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1065471 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 105504454 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 93209227 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 14418 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 255 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 232 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14368 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1674842 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 501476 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 2176318 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 373329400 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 101074307 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 4635184 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 6210311 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 59816 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 7651 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 391949728 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1062817 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 105463248 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 93220202 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 14378 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 211 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 349 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14360 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1675475 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 499111 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 2174586 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 373364048 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 101084784 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 4657038 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9589 # number of nop insts executed -system.cpu.iew.exec_refs 188479981 # number of memory reference insts executed -system.cpu.iew.exec_branches 38700000 # Number of branches executed -system.cpu.iew.exec_stores 87405674 # Number of stores executed -system.cpu.iew.exec_rate 2.632517 # Inst execution rate -system.cpu.iew.wb_sent 371919298 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 371120443 # cumulative count of insts written-back -system.cpu.iew.wb_producers 184768812 # num instructions producing a value -system.cpu.iew.wb_consumers 367722333 # num instructions consuming a value +system.cpu.iew.exec_nop 9021 # number of nop insts executed +system.cpu.iew.exec_refs 188503459 # number of memory reference insts executed +system.cpu.iew.exec_branches 38700482 # Number of branches executed +system.cpu.iew.exec_stores 87418675 # Number of stores executed +system.cpu.iew.exec_rate 2.633683 # Inst execution rate +system.cpu.iew.wb_sent 371949572 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 371155836 # cumulative count of insts written-back +system.cpu.iew.wb_producers 184798274 # num instructions producing a value +system.cpu.iew.wb_consumers 367725403 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.616941 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.502468 # average fanout of values written-back +system.cpu.iew.wb_rate 2.618107 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.502544 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 42898696 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 24480 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 2031740 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 135495750 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.576293 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.655015 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 42873018 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 24477 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 2030662 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 135442372 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.577309 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.655328 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 38151746 28.16% 28.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 29172803 21.53% 49.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13488501 9.95% 59.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11127648 8.21% 67.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 13794811 10.18% 78.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7272808 5.37% 83.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 3959931 2.92% 86.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3978843 2.94% 89.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 14548659 10.74% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 38119190 28.14% 28.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 29150867 21.52% 49.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13483643 9.96% 59.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11130935 8.22% 67.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 13797972 10.19% 78.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7276796 5.37% 83.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 3948237 2.92% 86.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3977327 2.94% 89.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 14557405 10.75% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 135495750 # Number of insts commited each cycle -system.cpu.commit.committedInsts 273049068 # Number of instructions committed -system.cpu.commit.committedOps 349076792 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 135442372 # Number of insts commited each cycle +system.cpu.commit.committedInsts 273049053 # Number of instructions committed +system.cpu.commit.committedOps 349076777 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 177029033 # Number of memory references committed -system.cpu.commit.loads 94651095 # Number of loads committed +system.cpu.commit.refs 177029027 # Number of memory references committed +system.cpu.commit.loads 94651092 # Number of loads committed system.cpu.commit.membars 11033 # Number of memory barriers committed -system.cpu.commit.branches 36549058 # Number of branches committed +system.cpu.commit.branches 36549055 # Number of branches committed system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions. -system.cpu.commit.int_insts 279593995 # Number of committed integer instructions. +system.cpu.commit.int_insts 279593983 # Number of committed integer instructions. system.cpu.commit.function_calls 6225112 # Number of function calls committed. -system.cpu.commit.bw_lim_events 14548659 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 14557405 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 512920056 # The number of ROB reads -system.cpu.rob.rob_writes 790163258 # The number of ROB writes -system.cpu.timesIdled 3290 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 111013 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 273048456 # Number of Instructions Simulated -system.cpu.committedOps 349076180 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 273048456 # Number of Instructions Simulated -system.cpu.cpi 0.519375 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.519375 # CPI: Total CPI of All Threads -system.cpu.ipc 1.925390 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.925390 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1783222925 # number of integer regfile reads -system.cpu.int_regfile_writes 236048544 # number of integer regfile writes -system.cpu.fp_regfile_reads 189858898 # number of floating regfile reads -system.cpu.fp_regfile_writes 133648833 # number of floating regfile writes -system.cpu.misc_regfile_reads 990710631 # number of misc regfile reads -system.cpu.misc_regfile_writes 34426475 # number of misc regfile writes -system.cpu.icache.replacements 13954 # number of replacements -system.cpu.icache.tagsinuse 1852.950065 # Cycle average of tags in use -system.cpu.icache.total_refs 39375254 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 15846 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 2484.870251 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 512832239 # The number of ROB reads +system.cpu.rob.rob_writes 790114412 # The number of ROB writes +system.cpu.timesIdled 3064 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 112294 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 273048441 # Number of Instructions Simulated +system.cpu.committedOps 349076165 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 273048441 # Number of Instructions Simulated +system.cpu.cpi 0.519194 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.519194 # CPI: Total CPI of All Threads +system.cpu.ipc 1.926064 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.926064 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1783379175 # number of integer regfile reads +system.cpu.int_regfile_writes 236079321 # number of integer regfile writes +system.cpu.fp_regfile_reads 189868959 # number of floating regfile reads +system.cpu.fp_regfile_writes 133650660 # number of floating regfile writes +system.cpu.misc_regfile_reads 990849298 # number of misc regfile reads +system.cpu.misc_regfile_writes 34426469 # number of misc regfile writes +system.cpu.icache.replacements 13928 # number of replacements +system.cpu.icache.tagsinuse 1856.985526 # Cycle average of tags in use +system.cpu.icache.total_refs 39384906 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 15824 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 2488.934909 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1852.950065 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.904761 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.904761 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 39375254 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 39375254 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 39375254 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 39375254 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 39375254 # number of overall hits -system.cpu.icache.overall_hits::total 39375254 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 16622 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 16622 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 16622 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 16622 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 16622 # number of overall misses -system.cpu.icache.overall_misses::total 16622 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 210340000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 210340000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 210340000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 210340000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 210340000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 210340000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 39391876 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 39391876 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 39391876 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 39391876 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 39391876 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 39391876 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 1856.985526 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.906731 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.906731 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 39384906 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 39384906 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 39384906 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 39384906 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 39384906 # number of overall hits +system.cpu.icache.overall_hits::total 39384906 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 16613 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 16613 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 16613 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 16613 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 16613 # number of overall misses +system.cpu.icache.overall_misses::total 16613 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 188398500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 188398500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 188398500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 188398500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 188398500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 188398500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 39401519 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 39401519 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 39401519 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 39401519 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 39401519 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 39401519 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000422 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000422 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000422 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000422 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000422 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000422 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 12654.313560 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 12654.313560 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 12654.313560 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 12654.313560 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 12654.313560 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 12654.313560 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 11340.426172 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 11340.426172 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 11340.426172 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 11340.426172 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 11340.426172 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 11340.426172 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -392,146 +392,146 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 775 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 775 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 775 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 775 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 775 # 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number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 138958000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 138958000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 789 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 789 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 789 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 789 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 789 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 789 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15824 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 15824 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 15824 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 15824 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 15824 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 15824 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 136475000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 136475000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 136475000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 136475000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 136475000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 136475000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000402 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000402 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000402 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000402 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000402 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000402 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8768.725942 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 8768.725942 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8768.725942 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 8768.725942 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8768.725942 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 8768.725942 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8624.557634 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 8624.557634 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8624.557634 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 8624.557634 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8624.557634 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 8624.557634 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1429 # number of replacements -system.cpu.dcache.tagsinuse 3114.485618 # Cycle average of tags in use -system.cpu.dcache.total_refs 172071632 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 4623 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 37220.772658 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1417 # number of replacements +system.cpu.dcache.tagsinuse 3115.188705 # Cycle average of tags in use +system.cpu.dcache.total_refs 172067508 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 4618 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 37260.179298 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3114.485618 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.760372 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.760372 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 90013475 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 90013475 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 82031354 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 82031354 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 13548 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 13548 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 13255 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 13255 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 172044829 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 172044829 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 172044829 # number of overall hits -system.cpu.dcache.overall_hits::total 172044829 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 3882 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 3882 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 21306 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 21306 # number of WriteReq misses +system.cpu.dcache.occ_blocks::cpu.data 3115.188705 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.760544 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.760544 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 90009194 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 90009194 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 82031517 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 82031517 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 13545 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 13545 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 13252 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 13252 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 172040711 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 172040711 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 172040711 # number of overall hits +system.cpu.dcache.overall_hits::total 172040711 # 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number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 25079 # number of overall misses +system.cpu.dcache.overall_misses::total 25079 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 123444000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 123444000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 700240500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 700240500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 74000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 74000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 823684500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 823684500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 823684500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 823684500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 90013130 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 90013130 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052660 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052660 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13550 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 13550 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 13255 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 13255 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 172070017 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 172070017 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 172070017 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 172070017 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000043 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000043 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000260 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000260 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13547 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 13547 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 13252 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 13252 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 172065790 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 172065790 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 172065790 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 172065790 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000044 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000044 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000258 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000258 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000148 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000148 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000146 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000146 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000146 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000146 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36021.380732 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 36021.380732 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38765.605933 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38765.605933 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 38000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 38342.663173 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 38342.663173 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 38342.663173 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 38342.663173 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31362.804878 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 31362.804878 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33119.259329 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33119.259329 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 37000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 37000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 32843.594242 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 32843.594242 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 32843.594242 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 32843.594242 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 306000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 313000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 12 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 16 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 25500 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 19562.500000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1044 # 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number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1041 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 2813 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 2813 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 15823 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 4618 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 20441 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 15823 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 4618 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 20441 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.193642 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.835457 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.259360 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.993957 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.993957 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.193642 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.932005 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.360452 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.193642 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.932005 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.360452 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35189.458225 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 37412.466844 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 35922.681540 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 37404.864092 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 37404.864092 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35189.458225 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 37407.527881 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 36485.138436 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35189.458225 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 37407.527881 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 36485.138436 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -640,59 +640,59 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 18 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 38 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 56 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 18 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 38 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 56 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 18 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 38 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 56 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3042 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 19 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 42 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 61 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 19 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 42 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 61 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 19 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 42 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 61 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3045 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1466 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 4508 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2791 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 2791 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3042 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 4257 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 7299 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3042 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 4257 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 7299 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 97581500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 50217500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 147799000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 95213500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 95213500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 97581500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 145431000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 243012500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 97581500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 145431000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 243012500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.191961 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.808159 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.255252 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.993592 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.993592 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.191961 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.920831 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.356571 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.191961 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.920831 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.356571 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32078.073636 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 34254.774898 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32785.936114 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 34114.475099 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 34114.475099 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32078.073636 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34162.790698 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33293.944376 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32078.073636 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34162.790698 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33293.944376 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::total 4511 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2796 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 2796 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3045 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 4262 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 7307 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3045 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 4262 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 7307 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 97703000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 50497000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 148200000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 95754500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 95754500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 97703000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 146251500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 243954500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 97703000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 146251500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 243954500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.192441 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.812188 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.255900 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.993957 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.993957 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.192441 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.922910 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.357468 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.192441 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922910 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.357468 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32086.371100 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 34445.429741 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32853.025937 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 34246.959943 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 34246.959943 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32086.371100 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34315.227593 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33386.410292 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32086.371100 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34315.227593 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33386.410292 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt index 7b678cb0b..793868398 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.525920 # Number of seconds simulated -sim_ticks 525920061000 # Number of ticks simulated -final_tick 525920061000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.525834 # Number of seconds simulated +sim_ticks 525834342000 # Number of ticks simulated +final_tick 525834342000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 787177 # Simulator instruction rate (inst/s) -host_op_rate 1006377 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1517904458 # Simulator tick rate (ticks/s) -host_mem_usage 235608 # Number of bytes of host memory used -host_seconds 346.48 # Real time elapsed on the host +host_inst_rate 739511 # Simulator instruction rate (inst/s) +host_op_rate 945437 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1425757824 # Simulator tick rate (ticks/s) +host_mem_usage 241188 # Number of bytes of host memory used +host_seconds 368.81 # Real time elapsed on the host sim_insts 272739283 # Number of instructions simulated sim_ops 348687122 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 166976 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 166976 # Nu system.physmem.num_reads::cpu.inst 2609 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 4223 # Number of read requests responded to by this memory system.physmem.num_reads::total 6832 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 317493 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 513903 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 831396 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 317493 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 317493 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 317493 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 513903 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 831396 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 317545 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 513987 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 831532 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 317545 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 317545 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 317545 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 513987 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 831532 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -70,7 +70,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 1051840122 # number of cpu cycles simulated +system.cpu.numCycles 1051668684 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 272739283 # Number of instructions committed @@ -89,18 +89,18 @@ system.cpu.num_mem_refs 177024356 # nu system.cpu.num_load_insts 94648757 # Number of load instructions system.cpu.num_store_insts 82375599 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 1051840122 # Number of busy cycles +system.cpu.num_busy_cycles 1051668684 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 13796 # number of replacements -system.cpu.icache.tagsinuse 1765.965460 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1765.993223 # Cycle average of tags in use system.cpu.icache.total_refs 348644747 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 15603 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 22344.725181 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1765.965460 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.862288 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.862288 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 1765.993223 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.862301 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.862301 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 348644747 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 348644747 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 348644747 # number of demand (read+write) hits @@ -113,12 +113,12 @@ system.cpu.icache.demand_misses::cpu.inst 15603 # n system.cpu.icache.demand_misses::total 15603 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 15603 # number of overall misses system.cpu.icache.overall_misses::total 15603 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 328087000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 328087000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 328087000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 328087000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 328087000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 328087000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 312417000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 312417000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 312417000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 312417000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 312417000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 312417000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 348660350 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 348660350 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 348660350 # number of demand (read+write) accesses @@ -131,12 +131,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000045 system.cpu.icache.demand_miss_rate::total 0.000045 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000045 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000045 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21027.174261 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 21027.174261 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 21027.174261 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 21027.174261 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 21027.174261 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 21027.174261 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20022.880215 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 20022.880215 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 20022.880215 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 20022.880215 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 20022.880215 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 20022.880215 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -151,34 +151,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 15603 system.cpu.icache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 15603 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 15603 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281278000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 281278000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281278000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 281278000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281278000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 281278000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281211000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 281211000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281211000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 281211000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281211000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 281211000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000045 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18027.174261 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18027.174261 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18027.174261 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 18027.174261 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18027.174261 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 18027.174261 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18022.880215 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18022.880215 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18022.880215 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 18022.880215 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18022.880215 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 18022.880215 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 1332 # number of replacements -system.cpu.dcache.tagsinuse 3078.361570 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 3078.412981 # Cycle average of tags in use system.cpu.dcache.total_refs 176641599 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 4478 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 39446.538410 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3078.361570 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.751553 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.751553 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 3078.412981 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.751566 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.751566 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 94570004 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 94570004 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 82049805 # number of WriteReq hits @@ -199,14 +199,14 @@ system.cpu.dcache.demand_misses::cpu.data 4478 # n system.cpu.dcache.demand_misses::total 4478 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 4478 # number of overall misses system.cpu.dcache.overall_misses::total 4478 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 80120000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 80120000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 160192000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 160192000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 240312000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 240312000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 240312000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 240312000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 78292000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 78292000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 157288000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 157288000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 235580000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 235580000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 235580000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 235580000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 94571610 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 94571610 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) @@ -227,14 +227,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49887.920299 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 49887.920299 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55777.158774 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55777.158774 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 53665.029031 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 53665.029031 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 53665.029031 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 53665.029031 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48749.688667 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 48749.688667 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54766.016713 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54766.016713 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 52608.307280 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 52608.307280 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 52608.307280 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 52608.307280 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -253,14 +253,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4478 system.cpu.dcache.demand_mshr_misses::total 4478 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4478 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4478 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75302000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 75302000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 151576000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 151576000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 226878000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 226878000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 226878000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 226878000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75080000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 75080000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 151544000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 151544000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 226624000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 226624000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 226624000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 226624000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000017 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000017 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses @@ -269,28 +269,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46887.920299 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46887.920299 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52777.158774 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52777.158774 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50665.029031 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 50665.029031 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50665.029031 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 50665.029031 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46749.688667 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46749.688667 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52766.016713 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52766.016713 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50608.307280 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 50608.307280 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50608.307280 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 50608.307280 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 3487.655618 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 3487.723791 # Cycle average of tags in use system.cpu.l2cache.total_refs 13310 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 4882 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 2.726342 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 341.607182 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2408.352970 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 737.695465 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 341.616093 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2408.399470 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 737.708228 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.010425 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.073497 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.073499 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.022513 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.106435 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.106437 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 12994 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 239 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 13233 # number of ReadReq hits |