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-rw-r--r--tests/long/se/30.eon/ref/alpha/tru64/minor-timing/config.ini877
-rwxr-xr-xtests/long/se/30.eon/ref/alpha/tru64/minor-timing/simerr53
-rwxr-xr-xtests/long/se/30.eon/ref/alpha/tru64/minor-timing/simout17
-rw-r--r--tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt794
-rw-r--r--tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini825
-rwxr-xr-xtests/long/se/30.eon/ref/alpha/tru64/o3-timing/simerr53
-rwxr-xr-xtests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout17
-rw-r--r--tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt1059
-rw-r--r--tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini366
-rwxr-xr-xtests/long/se/30.eon/ref/alpha/tru64/simple-timing/simerr52
-rwxr-xr-xtests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout17
-rw-r--r--tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt555
12 files changed, 0 insertions, 4685 deletions
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/config.ini
deleted file mode 100644
index 63271ea71..000000000
--- a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/config.ini
+++ /dev/null
@@ -1,877 +0,0 @@
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=false
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=System
-children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
-boot_osflags=a
-cache_line_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-exit_on_work_items=false
-init_param=0
-kernel=
-kernel_addr_check=true
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=timing
-mem_ranges=
-memories=system.physmem
-mmap_using_noreserve=false
-multi_thread=false
-num_work_ids=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-readfile=
-symbolfile=
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[0]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu]
-type=MinorCPU
-children=branchPred dcache dtb executeFuncUnits icache interrupts isa itb l2cache toL2Bus tracer workload
-branchPred=system.cpu.branchPred
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=0
-decodeCycleInput=true
-decodeInputBufferSize=3
-decodeInputWidth=2
-decodeToExecuteForwardDelay=1
-default_p_state=UNDEFINED
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu.dtb
-enableIdling=true
-eventq_index=0
-executeAllowEarlyMemoryIssue=true
-executeBranchDelay=1
-executeCommitLimit=2
-executeCycleInput=true
-executeFuncUnits=system.cpu.executeFuncUnits
-executeInputBufferSize=7
-executeInputWidth=2
-executeIssueLimit=2
-executeLSQMaxStoreBufferStoresPerCycle=2
-executeLSQRequestsQueueSize=1
-executeLSQStoreBufferSize=5
-executeLSQTransfersQueueSize=2
-executeMaxAccessesInMemory=2
-executeMemoryCommitLimit=1
-executeMemoryIssueLimit=1
-executeMemoryWidth=0
-executeSetTraceTimeOnCommit=true
-executeSetTraceTimeOnIssue=false
-fetch1FetchLimit=1
-fetch1LineSnapWidth=0
-fetch1LineWidth=0
-fetch1ToFetch2BackwardDelay=1
-fetch1ToFetch2ForwardDelay=1
-fetch2CycleInput=true
-fetch2InputBufferSize=2
-fetch2ToDecodeForwardDelay=1
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu.interrupts
-isa=system.cpu.isa
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-simpoint_start_insts=
-socket_id=0
-switched_out=false
-system=system
-threadPolicy=RoundRobin
-tracer=system.cpu.tracer
-workload=system.cpu.workload
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.branchPred]
-type=TournamentBP
-BTBEntries=4096
-BTBTagSize=16
-RASSize=16
-choiceCtrBits=2
-choicePredictorSize=8192
-eventq_index=0
-globalCtrBits=2
-globalPredictorSize=8192
-indirectHashGHR=true
-indirectHashTargets=true
-indirectPathLength=3
-indirectSets=256
-indirectTagSize=16
-indirectWays=2
-instShiftAmt=2
-localCtrBits=2
-localHistoryTableSize=2048
-localPredictorSize=2048
-numThreads=1
-useIndirect=true
-
-[system.cpu.dcache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=2
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=false
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=262144
-system=system
-tags=system.cpu.dcache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.slave[1]
-
-[system.cpu.dcache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=262144
-
-[system.cpu.dtb]
-type=AlphaTLB
-eventq_index=0
-size=64
-
-[system.cpu.executeFuncUnits]
-type=MinorFUPool
-children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6
-eventq_index=0
-funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6
-
-[system.cpu.executeFuncUnits.funcUnits0]
-type=MinorFU
-children=opClasses timings
-cantForwardFromFUIndices=
-eventq_index=0
-issueLat=1
-opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses
-opLat=3
-timings=system.cpu.executeFuncUnits.funcUnits0.timings
-
-[system.cpu.executeFuncUnits.funcUnits0.opClasses]
-type=MinorOpClassSet
-children=opClasses
-eventq_index=0
-opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses
-
-[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses]
-type=MinorOpClass
-eventq_index=0
-opClass=IntAlu
-
-[system.cpu.executeFuncUnits.funcUnits0.timings]
-type=MinorFUTiming
-children=opClasses
-description=Int
-eventq_index=0
-extraAssumedLat=0
-extraCommitLat=0
-extraCommitLatExpr=Null
-mask=0
-match=0
-opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses
-srcRegsRelativeLats=2
-suppress=false
-
-[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses]
-type=MinorOpClassSet
-eventq_index=0
-opClasses=
-
-[system.cpu.executeFuncUnits.funcUnits1]
-type=MinorFU
-children=opClasses timings
-cantForwardFromFUIndices=
-eventq_index=0
-issueLat=1
-opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses
-opLat=3
-timings=system.cpu.executeFuncUnits.funcUnits1.timings
-
-[system.cpu.executeFuncUnits.funcUnits1.opClasses]
-type=MinorOpClassSet
-children=opClasses
-eventq_index=0
-opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses
-
-[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses]
-type=MinorOpClass
-eventq_index=0
-opClass=IntAlu
-
-[system.cpu.executeFuncUnits.funcUnits1.timings]
-type=MinorFUTiming
-children=opClasses
-description=Int
-eventq_index=0
-extraAssumedLat=0
-extraCommitLat=0
-extraCommitLatExpr=Null
-mask=0
-match=0
-opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses
-srcRegsRelativeLats=2
-suppress=false
-
-[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses]
-type=MinorOpClassSet
-eventq_index=0
-opClasses=
-
-[system.cpu.executeFuncUnits.funcUnits2]
-type=MinorFU
-children=opClasses timings
-cantForwardFromFUIndices=
-eventq_index=0
-issueLat=1
-opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses
-opLat=3
-timings=system.cpu.executeFuncUnits.funcUnits2.timings
-
-[system.cpu.executeFuncUnits.funcUnits2.opClasses]
-type=MinorOpClassSet
-children=opClasses
-eventq_index=0
-opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses
-
-[system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses]
-type=MinorOpClass
-eventq_index=0
-opClass=IntMult
-
-[system.cpu.executeFuncUnits.funcUnits2.timings]
-type=MinorFUTiming
-children=opClasses
-description=Mul
-eventq_index=0
-extraAssumedLat=0
-extraCommitLat=0
-extraCommitLatExpr=Null
-mask=0
-match=0
-opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses
-srcRegsRelativeLats=0
-suppress=false
-
-[system.cpu.executeFuncUnits.funcUnits2.timings.opClasses]
-type=MinorOpClassSet
-eventq_index=0
-opClasses=
-
-[system.cpu.executeFuncUnits.funcUnits3]
-type=MinorFU
-children=opClasses
-cantForwardFromFUIndices=
-eventq_index=0
-issueLat=9
-opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses
-opLat=9
-timings=
-
-[system.cpu.executeFuncUnits.funcUnits3.opClasses]
-type=MinorOpClassSet
-children=opClasses
-eventq_index=0
-opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses
-
-[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses]
-type=MinorOpClass
-eventq_index=0
-opClass=IntDiv
-
-[system.cpu.executeFuncUnits.funcUnits4]
-type=MinorFU
-children=opClasses timings
-cantForwardFromFUIndices=
-eventq_index=0
-issueLat=1
-opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses
-opLat=6
-timings=system.cpu.executeFuncUnits.funcUnits4.timings
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses]
-type=MinorOpClassSet
-children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25
-eventq_index=0
-opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00]
-type=MinorOpClass
-eventq_index=0
-opClass=FloatAdd
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01]
-type=MinorOpClass
-eventq_index=0
-opClass=FloatCmp
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02]
-type=MinorOpClass
-eventq_index=0
-opClass=FloatCvt
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03]
-type=MinorOpClass
-eventq_index=0
-opClass=FloatMult
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04]
-type=MinorOpClass
-eventq_index=0
-opClass=FloatDiv
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05]
-type=MinorOpClass
-eventq_index=0
-opClass=FloatSqrt
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdAdd
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdAddAcc
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdAlu
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdCmp
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdCvt
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdMisc
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdMult
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdMultAcc
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdShift
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdShiftAcc
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdSqrt
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdFloatAdd
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdFloatAlu
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdFloatCmp
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdFloatCvt
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdFloatDiv
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdFloatMisc
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdFloatMult
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdFloatMultAcc
-
-[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25]
-type=MinorOpClass
-eventq_index=0
-opClass=SimdFloatSqrt
-
-[system.cpu.executeFuncUnits.funcUnits4.timings]
-type=MinorFUTiming
-children=opClasses
-description=FloatSimd
-eventq_index=0
-extraAssumedLat=0
-extraCommitLat=0
-extraCommitLatExpr=Null
-mask=0
-match=0
-opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses
-srcRegsRelativeLats=2
-suppress=false
-
-[system.cpu.executeFuncUnits.funcUnits4.timings.opClasses]
-type=MinorOpClassSet
-eventq_index=0
-opClasses=
-
-[system.cpu.executeFuncUnits.funcUnits5]
-type=MinorFU
-children=opClasses timings
-cantForwardFromFUIndices=
-eventq_index=0
-issueLat=1
-opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses
-opLat=1
-timings=system.cpu.executeFuncUnits.funcUnits5.timings
-
-[system.cpu.executeFuncUnits.funcUnits5.opClasses]
-type=MinorOpClassSet
-children=opClasses0 opClasses1
-eventq_index=0
-opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1
-
-[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0]
-type=MinorOpClass
-eventq_index=0
-opClass=MemRead
-
-[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1]
-type=MinorOpClass
-eventq_index=0
-opClass=MemWrite
-
-[system.cpu.executeFuncUnits.funcUnits5.timings]
-type=MinorFUTiming
-children=opClasses
-description=Mem
-eventq_index=0
-extraAssumedLat=2
-extraCommitLat=0
-extraCommitLatExpr=Null
-mask=0
-match=0
-opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses
-srcRegsRelativeLats=1
-suppress=false
-
-[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses]
-type=MinorOpClassSet
-eventq_index=0
-opClasses=
-
-[system.cpu.executeFuncUnits.funcUnits6]
-type=MinorFU
-children=opClasses
-cantForwardFromFUIndices=
-eventq_index=0
-issueLat=1
-opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses
-opLat=1
-timings=
-
-[system.cpu.executeFuncUnits.funcUnits6.opClasses]
-type=MinorOpClassSet
-children=opClasses0 opClasses1
-eventq_index=0
-opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1
-
-[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0]
-type=MinorOpClass
-eventq_index=0
-opClass=IprAccess
-
-[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1]
-type=MinorOpClass
-eventq_index=0
-opClass=InstPrefetch
-
-[system.cpu.icache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=2
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=true
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=131072
-system=system
-tags=system.cpu.icache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=true
-cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.slave[0]
-
-[system.cpu.icache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=131072
-
-[system.cpu.interrupts]
-type=AlphaInterrupts
-eventq_index=0
-
-[system.cpu.isa]
-type=AlphaISA
-eventq_index=0
-system=system
-
-[system.cpu.itb]
-type=AlphaTLB
-eventq_index=0
-size=48
-
-[system.cpu.l2cache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=8
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=20
-is_read_only=false
-max_miss_count=0
-mshrs=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
-sequential_access=false
-size=2097152
-system=system
-tags=system.cpu.l2cache.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.toL2Bus.master[0]
-mem_side=system.membus.slave[1]
-
-[system.cpu.l2cache.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=2097152
-
-[system.cpu.toL2Bus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=false
-power_model=Null
-response_latency=1
-snoop_filter=system.cpu.toL2Bus.snoop_filter
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
-
-[system.cpu.toL2Bus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=0
-max_capacity=8388608
-system=system
-
-[system.cpu.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
-cwd=build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/minor-timing
-drivers=
-egid=100
-env=
-errout=cerr
-euid=100
-eventq_index=0
-executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/eon
-gid=100
-input=cin
-kvmInSE=false
-max_stack_size=67108864
-output=cout
-pid=100
-ppid=99
-simpoint=0
-system=system
-uid=100
-useArchPT=false
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.membus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=true
-power_model=Null
-response_latency=2
-snoop_filter=system.membus.snoop_filter
-snoop_response_latency=4
-system=system
-use_default_range=false
-width=16
-master=system.physmem.port
-slave=system.system_port system.cpu.l2cache.mem_side
-
-[system.membus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=1
-max_capacity=8388608
-system=system
-
-[system.physmem]
-type=DRAMCtrl
-IDD0=0.055000
-IDD02=0.000000
-IDD2N=0.032000
-IDD2N2=0.000000
-IDD2P0=0.000000
-IDD2P02=0.000000
-IDD2P1=0.032000
-IDD2P12=0.000000
-IDD3N=0.038000
-IDD3N2=0.000000
-IDD3P0=0.000000
-IDD3P02=0.000000
-IDD3P1=0.038000
-IDD3P12=0.000000
-IDD4R=0.157000
-IDD4R2=0.000000
-IDD4W=0.125000
-IDD4W2=0.000000
-IDD5=0.235000
-IDD52=0.000000
-IDD6=0.020000
-IDD62=0.000000
-VDD=1.500000
-VDD2=0.000000
-activation_limit=4
-addr_mapping=RoRaBaCoCh
-bank_groups_per_rank=0
-banks_per_rank=8
-burst_length=8
-channels=1
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-device_bus_width=8
-device_rowbuffer_size=1024
-device_size=536870912
-devices_per_rank=8
-dll=true
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-max_accesses_per_row=16
-mem_sched_policy=frfcfs
-min_writes_per_switch=16
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-page_policy=open_adaptive
-power_model=Null
-range=0:134217727:0:0:0:0
-ranks_per_channel=2
-read_buffer_size=32
-static_backend_latency=10000
-static_frontend_latency=10000
-tBURST=5000
-tCCD_L=0
-tCK=1250
-tCL=13750
-tCS=2500
-tRAS=35000
-tRCD=13750
-tREFI=7800000
-tRFC=260000
-tRP=13750
-tRRD=6000
-tRRD_L=0
-tRTP=7500
-tRTW=2500
-tWR=15000
-tWTR=7500
-tXAW=30000
-tXP=6000
-tXPDLL=0
-tXS=270000
-tXSDLL=0
-write_buffer_size=64
-write_high_thresh_perc=85
-write_low_thresh_perc=50
-port=system.membus.master[0]
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/simerr b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/simerr
deleted file mode 100755
index 9c10deefc..000000000
--- a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/simerr
+++ /dev/null
@@ -1,53 +0,0 @@
-warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
-warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-warn: Prefetch instructions in Alpha do not do anything
-warn: Prefetch instructions in Alpha do not do anything
-warn: Prefetch instructions in Alpha do not do anything
-getting pixel output filename pixels_out.cook
-opening control file chair.control.cook
-opening camera file chair.camera
-opening surfaces file chair.surfaces
-reading data
-processing 8parts
-Grid measure is 6 by 3.0001 by 6
-cell dimension is 0.863065
-Creating grid for list of length 21
-Grid size = 7 by 4 by 7
-Total occupancy = 236
-reading control stream
-reading camera stream
-Writing to chair.cook.ppm
-calculating 15 by 15 image with 196 samples
-col 0. . .
-col 1. . .
-col 2. . .
-col 3. . .
-col 4. . .
-col 5. . .
-col 6. . .
-col 7. . .
-col 8. . .
-col 9. . .
-col 10. . .
-col 11. . .
-col 12. . .
-col 13. . .
-col 14. . .
-Writing to chair.cook.ppm
-0 8 14
-1 8 14
-2 8 14
-3 8 14
-4 8 14
-5 8 14
-6 8 14
-7 8 14
-8 8 14
-9 8 14
-10 8 14
-11 8 14
-12 8 14
-13 8 14
-14 8 14
-warn: ignoring syscall sigprocmask(1, ...)
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/simout
deleted file mode 100755
index 6a622d0db..000000000
--- a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/simout
+++ /dev/null
@@ -1,17 +0,0 @@
-Redirecting stdout to build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/minor-timing/simout
-Redirecting stderr to build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/minor-timing/simerr
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Oct 11 2016 00:00:58
-gem5 started Oct 13 2016 20:19:45
-gem5 executing on e108600-lin, pid 28070
-command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/30.eon/alpha/tru64/minor-timing
-
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-info: Increasing stack size by one page.
-Eon, Version 1.1
-info: Increasing stack size by one page.
-OO-style eon Time= 0.233333
-Exiting @ tick 233641094500 because target called exit()
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt
deleted file mode 100644
index 2ec97b33e..000000000
--- a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt
+++ /dev/null
@@ -1,794 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.233641 # Number of seconds simulated
-sim_ticks 233641094500 # Number of ticks simulated
-final_tick 233641094500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 449379 # Simulator instruction rate (inst/s)
-host_op_rate 449379 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 263362780 # Simulator tick rate (ticks/s)
-host_mem_usage 260228 # Number of bytes of host memory used
-host_seconds 887.15 # Real time elapsed on the host
-sim_insts 398664651 # Number of instructions simulated
-sim_ops 398664651 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 233641094500 # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst 249280 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 254592 # Number of bytes read from this memory
-system.physmem.bytes_read::total 503872 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 249280 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 249280 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 3895 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 3978 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 7873 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1066936 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 1089671 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 2156607 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1066936 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1066936 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1066936 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 1089671 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 2156607 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 7873 # Number of read requests accepted
-system.physmem.writeReqs 0 # Number of write requests accepted
-system.physmem.readBursts 7873 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 503872 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
-system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 503872 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 548 # Per bank write bursts
-system.physmem.perBankRdBursts::1 675 # Per bank write bursts
-system.physmem.perBankRdBursts::2 473 # Per bank write bursts
-system.physmem.perBankRdBursts::3 633 # Per bank write bursts
-system.physmem.perBankRdBursts::4 475 # Per bank write bursts
-system.physmem.perBankRdBursts::5 477 # Per bank write bursts
-system.physmem.perBankRdBursts::6 563 # Per bank write bursts
-system.physmem.perBankRdBursts::7 560 # Per bank write bursts
-system.physmem.perBankRdBursts::8 471 # Per bank write bursts
-system.physmem.perBankRdBursts::9 437 # Per bank write bursts
-system.physmem.perBankRdBursts::10 354 # Per bank write bursts
-system.physmem.perBankRdBursts::11 323 # Per bank write bursts
-system.physmem.perBankRdBursts::12 430 # Per bank write bursts
-system.physmem.perBankRdBursts::13 556 # Per bank write bursts
-system.physmem.perBankRdBursts::14 473 # Per bank write bursts
-system.physmem.perBankRdBursts::15 425 # Per bank write bursts
-system.physmem.perBankWrBursts::0 0 # Per bank write bursts
-system.physmem.perBankWrBursts::1 0 # Per bank write bursts
-system.physmem.perBankWrBursts::2 0 # Per bank write bursts
-system.physmem.perBankWrBursts::3 0 # Per bank write bursts
-system.physmem.perBankWrBursts::4 0 # Per bank write bursts
-system.physmem.perBankWrBursts::5 0 # Per bank write bursts
-system.physmem.perBankWrBursts::6 0 # Per bank write bursts
-system.physmem.perBankWrBursts::7 0 # Per bank write bursts
-system.physmem.perBankWrBursts::8 0 # Per bank write bursts
-system.physmem.perBankWrBursts::9 0 # Per bank write bursts
-system.physmem.perBankWrBursts::10 0 # Per bank write bursts
-system.physmem.perBankWrBursts::11 0 # Per bank write bursts
-system.physmem.perBankWrBursts::12 0 # Per bank write bursts
-system.physmem.perBankWrBursts::13 0 # Per bank write bursts
-system.physmem.perBankWrBursts::14 0 # Per bank write bursts
-system.physmem.perBankWrBursts::15 0 # Per bank write bursts
-system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 233641000500 # Total gap between requests
-system.physmem.readPktSize::0 0 # Read request sizes (log2)
-system.physmem.readPktSize::1 0 # Read request sizes (log2)
-system.physmem.readPktSize::2 0 # Read request sizes (log2)
-system.physmem.readPktSize::3 0 # Read request sizes (log2)
-system.physmem.readPktSize::4 0 # Read request sizes (log2)
-system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 7873 # Read request sizes (log2)
-system.physmem.writePktSize::0 0 # Write request sizes (log2)
-system.physmem.writePktSize::1 0 # Write request sizes (log2)
-system.physmem.writePktSize::2 0 # Write request sizes (log2)
-system.physmem.writePktSize::3 0 # Write request sizes (log2)
-system.physmem.writePktSize::4 0 # Write request sizes (log2)
-system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 0 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 6664 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 1130 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 79 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 1527 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 328.298625 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 196.524272 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 332.958390 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 522 34.18% 34.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 350 22.92% 57.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 181 11.85% 68.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 105 6.88% 75.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 64 4.19% 80.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 46 3.01% 83.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 30 1.96% 85.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 42 2.75% 87.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 187 12.25% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 1527 # Bytes accessed per row activation
-system.physmem.totQLat 179319500 # Total ticks spent queuing
-system.physmem.totMemAccLat 326938250 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 39365000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 22776.51 # Average queueing delay per DRAM burst
-system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 41526.51 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 2.16 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 2.16 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
-system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 0.02 # Data bus utilization in percentage
-system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
-system.physmem.readRowHits 6337 # Number of row buffer hits during reads
-system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 80.49 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 29676235.30 # Average gap between requests
-system.physmem.pageHitRate 80.49 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 6326040 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 3347190 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 31444560 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 242168160.000000 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 105016230 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 11391840 # Energy for precharge background per rank (pJ)
-system.physmem_0.actPowerDownEnergy 673376340 # Energy for active power-down per rank (pJ)
-system.physmem_0.prePowerDownEnergy 320465280 # Energy for precharge power-down per rank (pJ)
-system.physmem_0.selfRefreshEnergy 55494876360 # Energy for self refresh per rank (pJ)
-system.physmem_0.totalEnergy 56888412000 # Total energy per rank (pJ)
-system.physmem_0.averagePower 243.486327 # Core power per rank (mW)
-system.physmem_0.totalIdleTime 233381065000 # Total Idle time Per DRAM Rank
-system.physmem_0.memoryStateTime::IDLE 19761500 # Time in different power states
-system.physmem_0.memoryStateTime::REF 102860000 # Time in different power states
-system.physmem_0.memoryStateTime::SREF 231069881000 # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN 834517500 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 137354250 # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN 1476720250 # Time in different power states
-system.physmem_1.actEnergy 4641000 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 2447775 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 24768660 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 215124000.000000 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 84187860 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 12227040 # Energy for precharge background per rank (pJ)
-system.physmem_1.actPowerDownEnergy 535263060 # Energy for active power-down per rank (pJ)
-system.physmem_1.prePowerDownEnergy 280836480 # Energy for precharge power-down per rank (pJ)
-system.physmem_1.selfRefreshEnergy 55611059460 # Energy for self refresh per rank (pJ)
-system.physmem_1.totalEnergy 56770555335 # Total energy per rank (pJ)
-system.physmem_1.averagePower 242.981892 # Core power per rank (mW)
-system.physmem_1.totalIdleTime 233423818750 # Total Idle time Per DRAM Rank
-system.physmem_1.memoryStateTime::IDLE 23567500 # Time in different power states
-system.physmem_1.memoryStateTime::REF 91510000 # Time in different power states
-system.physmem_1.memoryStateTime::SREF 231519465750 # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN 731339000 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 101377500 # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN 1173834750 # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 233641094500 # Cumulative time (in ticks) in various power states
-system.cpu.branchPred.lookups 45912950 # Number of BP lookups
-system.cpu.branchPred.condPredicted 26702746 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 565787 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 25186743 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 18811780 # Number of BTB hits
-system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 74.689212 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 8285572 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 323 # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups 2249876 # Number of indirect predictor lookups.
-system.cpu.branchPred.indirectHits 2235903 # Number of indirect target hits.
-system.cpu.branchPred.indirectMisses 13973 # Number of indirect misses.
-system.cpu.branchPredindirectMispredicted 111495 # Number of mispredicted indirect branches.
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.dtb.fetch_hits 0 # ITB hits
-system.cpu.dtb.fetch_misses 0 # ITB misses
-system.cpu.dtb.fetch_acv 0 # ITB acv
-system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 95338456 # DTB read hits
-system.cpu.dtb.read_misses 116 # DTB read misses
-system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 95338572 # DTB read accesses
-system.cpu.dtb.write_hits 73578378 # DTB write hits
-system.cpu.dtb.write_misses 847 # DTB write misses
-system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 73579225 # DTB write accesses
-system.cpu.dtb.data_hits 168916834 # DTB hits
-system.cpu.dtb.data_misses 963 # DTB misses
-system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 168917797 # DTB accesses
-system.cpu.itb.fetch_hits 96959253 # ITB hits
-system.cpu.itb.fetch_misses 1239 # ITB misses
-system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 96960492 # ITB accesses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.read_acv 0 # DTB read access violations
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.itb.write_acv 0 # DTB write access violations
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.data_hits 0 # DTB hits
-system.cpu.itb.data_misses 0 # DTB misses
-system.cpu.itb.data_acv 0 # DTB access violations
-system.cpu.itb.data_accesses 0 # DTB accesses
-system.cpu.workload.num_syscalls 215 # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON 233641094500 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 467282189 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 398664651 # Number of instructions committed
-system.cpu.committedOps 398664651 # Number of ops (including micro ops) committed
-system.cpu.discardedOps 2289293 # Number of ops (including micro ops) which were discarded before commit
-system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
-system.cpu.cpi 1.172118 # CPI: cycles per instruction
-system.cpu.ipc 0.853156 # IPC: instructions per cycle
-system.cpu.op_class_0::No_OpClass 23123356 5.80% 5.80% # Class of committed instruction
-system.cpu.op_class_0::IntAlu 141652555 35.53% 41.33% # Class of committed instruction
-system.cpu.op_class_0::IntMult 2124322 0.53% 41.86% # Class of committed instruction
-system.cpu.op_class_0::IntDiv 0 0.00% 41.86% # Class of committed instruction
-system.cpu.op_class_0::FloatAdd 35620060 8.93% 50.80% # Class of committed instruction
-system.cpu.op_class_0::FloatCmp 7072549 1.77% 52.57% # Class of committed instruction
-system.cpu.op_class_0::FloatCvt 2735231 0.69% 53.26% # Class of committed instruction
-system.cpu.op_class_0::FloatMult 16498021 4.14% 57.40% # Class of committed instruction
-system.cpu.op_class_0::FloatMultAcc 0 0.00% 57.40% # Class of committed instruction
-system.cpu.op_class_0::FloatDiv 1563283 0.39% 57.79% # Class of committed instruction
-system.cpu.op_class_0::FloatMisc 0 0.00% 57.79% # Class of committed instruction
-system.cpu.op_class_0::FloatSqrt 0 0.00% 57.79% # Class of committed instruction
-system.cpu.op_class_0::SimdAdd 0 0.00% 57.79% # Class of committed instruction
-system.cpu.op_class_0::SimdAddAcc 0 0.00% 57.79% # Class of committed instruction
-system.cpu.op_class_0::SimdAlu 0 0.00% 57.79% # Class of committed instruction
-system.cpu.op_class_0::SimdCmp 0 0.00% 57.79% # Class of committed instruction
-system.cpu.op_class_0::SimdCvt 0 0.00% 57.79% # Class of committed instruction
-system.cpu.op_class_0::SimdMisc 0 0.00% 57.79% # Class of committed instruction
-system.cpu.op_class_0::SimdMult 0 0.00% 57.79% # Class of committed instruction
-system.cpu.op_class_0::SimdMultAcc 0 0.00% 57.79% # Class of committed instruction
-system.cpu.op_class_0::SimdShift 0 0.00% 57.79% # Class of committed instruction
-system.cpu.op_class_0::SimdShiftAcc 0 0.00% 57.79% # Class of committed instruction
-system.cpu.op_class_0::SimdSqrt 0 0.00% 57.79% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatAdd 0 0.00% 57.79% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatAlu 0 0.00% 57.79% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatCmp 0 0.00% 57.79% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatCvt 0 0.00% 57.79% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatDiv 0 0.00% 57.79% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatMisc 0 0.00% 57.79% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatMult 0 0.00% 57.79% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 57.79% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 57.79% # Class of committed instruction
-system.cpu.op_class_0::MemRead 46072315 11.56% 69.35% # Class of committed instruction
-system.cpu.op_class_0::MemWrite 30396984 7.62% 76.97% # Class of committed instruction
-system.cpu.op_class_0::FloatMemRead 48682195 12.21% 89.18% # Class of committed instruction
-system.cpu.op_class_0::FloatMemWrite 43123780 10.82% 100.00% # Class of committed instruction
-system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
-system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu.op_class_0::total 398664651 # Class of committed instruction
-system.cpu.tickCycles 455741730 # Number of cycles that the object actually ticked
-system.cpu.idleCycles 11540459 # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 233641094500 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements 771 # number of replacements
-system.cpu.dcache.tags.tagsinuse 3291.586193 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 167817015 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 4165 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 40292.200480 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 3291.586193 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.803610 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.803610 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024 3394 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 216 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4 3113 # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024 0.828613 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 335652183 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 335652183 # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 233641094500 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data 94302219 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 94302219 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 73514796 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 73514796 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 167817015 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 167817015 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 167817015 # number of overall hits
-system.cpu.dcache.overall_hits::total 167817015 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 1061 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 1061 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 5933 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 5933 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 6994 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 6994 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 6994 # number of overall misses
-system.cpu.dcache.overall_misses::total 6994 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 94695000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 94695000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 540363000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 540363000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 635058000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 635058000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 635058000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 635058000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 94303280 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 94303280 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 73520729 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 167824009 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 167824009 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 167824009 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 167824009 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000011 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.000011 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000081 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.000081 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.000042 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.000042 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.000042 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.000042 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 89250.706880 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 89250.706880 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 91077.532446 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 91077.532446 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 90800.400343 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 90800.400343 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 90800.400343 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 90800.400343 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.writebacks::writebacks 654 # number of writebacks
-system.cpu.dcache.writebacks::total 654 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 92 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 92 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2737 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 2737 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 2829 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 2829 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 2829 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 2829 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 969 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 969 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3196 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 3196 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 4165 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 4165 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 4165 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 4165 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 86354000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 86354000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 303749000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 303749000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 390103000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 390103000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 390103000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 390103000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000043 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 89116.615067 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 89116.615067 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 95040.362954 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 95040.362954 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 93662.184874 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 93662.184874 # average overall mshr miss latency
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-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 82541.915407 # average overall mshr miss latency
-system.cpu.toL2Bus.snoop_filter.tot_requests 13302 # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests 3965 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 233641094500 # Cumulative time (in ticks) in various power states
-system.cpu.toL2Bus.trans_dist::ReadResp 6139 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty 654 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean 3194 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict 117 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 3198 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 3198 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq 5172 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq 967 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 13538 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9101 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 22639 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 535424 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 308416 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 843840 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 0 # Total snoops (count)
-system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples 9337 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 9337 100.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 9337 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 10499000 # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 7758000 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 6247500 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.snoop_filter.tot_requests 7873 # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 233641094500 # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadResp 4736 # Transaction distribution
-system.membus.trans_dist::ReadExReq 3137 # Transaction distribution
-system.membus.trans_dist::ReadExResp 3137 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 4736 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15746 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 15746 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 503872 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 503872 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples 7873 # Request fanout histogram
-system.membus.snoop_fanout::mean 0 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 7873 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 7873 # Request fanout histogram
-system.membus.reqLayer0.occupancy 9215000 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer1.occupancy 41791500 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
-
----------- End Simulation Statistics ----------
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini
deleted file mode 100644
index c2a5884c8..000000000
--- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini
+++ /dev/null
@@ -1,825 +0,0 @@
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=false
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=System
-children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
-boot_osflags=a
-cache_line_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-exit_on_work_items=false
-init_param=0
-kernel=
-kernel_addr_check=true
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=timing
-mem_ranges=
-memories=system.physmem
-mmap_using_noreserve=false
-multi_thread=false
-num_work_ids=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-readfile=
-symbolfile=
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[0]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu]
-type=DerivO3CPU
-children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
-LFSTSize=1024
-LQEntries=32
-LSQCheckLoads=true
-LSQDepCheckShift=4
-SQEntries=32
-SSITSize=1024
-activity=0
-backComSize=5
-branchPred=system.cpu.branchPred
-cachePorts=200
-checker=Null
-clk_domain=system.cpu_clk_domain
-commitToDecodeDelay=1
-commitToFetchDelay=1
-commitToIEWDelay=1
-commitToRenameDelay=1
-commitWidth=8
-cpu_id=0
-decodeToFetchDelay=1
-decodeToRenameDelay=1
-decodeWidth=8
-default_p_state=UNDEFINED
-dispatchWidth=8
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu.dtb
-eventq_index=0
-fetchBufferSize=64
-fetchQueueSize=32
-fetchToDecodeDelay=1
-fetchTrapLatency=1
-fetchWidth=8
-forwardComSize=5
-fuPool=system.cpu.fuPool
-function_trace=false
-function_trace_start=0
-iewToCommitDelay=1
-iewToDecodeDelay=1
-iewToFetchDelay=1
-iewToRenameDelay=1
-interrupts=system.cpu.interrupts
-isa=system.cpu.isa
-issueToExecuteDelay=1
-issueWidth=8
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-needsTSO=false
-numIQEntries=64
-numPhysCCRegs=0
-numPhysFloatRegs=256
-numPhysIntRegs=256
-numROBEntries=192
-numRobs=1
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-renameToDecodeDelay=1
-renameToFetchDelay=1
-renameToIEWDelay=2
-renameToROBDelay=1
-renameWidth=8
-simpoint_start_insts=
-smtCommitPolicy=RoundRobin
-smtFetchPolicy=SingleThread
-smtIQPolicy=Partitioned
-smtIQThreshold=100
-smtLSQPolicy=Partitioned
-smtLSQThreshold=100
-smtNumFetchingThreads=1
-smtROBPolicy=Partitioned
-smtROBThreshold=100
-socket_id=0
-squashWidth=8
-store_set_clear_period=250000
-switched_out=false
-system=system
-tracer=system.cpu.tracer
-trapLatency=13
-wbWidth=8
-workload=system.cpu.workload
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.branchPred]
-type=TournamentBP
-BTBEntries=4096
-BTBTagSize=16
-RASSize=16
-choiceCtrBits=2
-choicePredictorSize=8192
-eventq_index=0
-globalCtrBits=2
-globalPredictorSize=8192
-indirectHashGHR=true
-indirectHashTargets=true
-indirectPathLength=3
-indirectSets=256
-indirectTagSize=16
-indirectWays=2
-instShiftAmt=2
-localCtrBits=2
-localHistoryTableSize=2048
-localPredictorSize=2048
-numThreads=1
-useIndirect=true
-
-[system.cpu.dcache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=2
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=false
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=262144
-system=system
-tags=system.cpu.dcache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.slave[1]
-
-[system.cpu.dcache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=262144
-
-[system.cpu.dtb]
-type=AlphaTLB
-eventq_index=0
-size=64
-
-[system.cpu.fuPool]
-type=FUPool
-children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
-eventq_index=0
-
-[system.cpu.fuPool.FUList0]
-type=FUDesc
-children=opList
-count=6
-eventq_index=0
-opList=system.cpu.fuPool.FUList0.opList
-
-[system.cpu.fuPool.FUList0.opList]
-type=OpDesc
-eventq_index=0
-opClass=IntAlu
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList1]
-type=FUDesc
-children=opList0 opList1
-count=2
-eventq_index=0
-opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
-
-[system.cpu.fuPool.FUList1.opList0]
-type=OpDesc
-eventq_index=0
-opClass=IntMult
-opLat=3
-pipelined=true
-
-[system.cpu.fuPool.FUList1.opList1]
-type=OpDesc
-eventq_index=0
-opClass=IntDiv
-opLat=20
-pipelined=false
-
-[system.cpu.fuPool.FUList2]
-type=FUDesc
-children=opList0 opList1 opList2
-count=4
-eventq_index=0
-opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
-
-[system.cpu.fuPool.FUList2.opList0]
-type=OpDesc
-eventq_index=0
-opClass=FloatAdd
-opLat=2
-pipelined=true
-
-[system.cpu.fuPool.FUList2.opList1]
-type=OpDesc
-eventq_index=0
-opClass=FloatCmp
-opLat=2
-pipelined=true
-
-[system.cpu.fuPool.FUList2.opList2]
-type=OpDesc
-eventq_index=0
-opClass=FloatCvt
-opLat=2
-pipelined=true
-
-[system.cpu.fuPool.FUList3]
-type=FUDesc
-children=opList0 opList1 opList2
-count=2
-eventq_index=0
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
-
-[system.cpu.fuPool.FUList3.opList0]
-type=OpDesc
-eventq_index=0
-opClass=FloatMult
-opLat=4
-pipelined=true
-
-[system.cpu.fuPool.FUList3.opList1]
-type=OpDesc
-eventq_index=0
-opClass=FloatDiv
-opLat=12
-pipelined=false
-
-[system.cpu.fuPool.FUList3.opList2]
-type=OpDesc
-eventq_index=0
-opClass=FloatSqrt
-opLat=24
-pipelined=false
-
-[system.cpu.fuPool.FUList4]
-type=FUDesc
-children=opList
-count=0
-eventq_index=0
-opList=system.cpu.fuPool.FUList4.opList
-
-[system.cpu.fuPool.FUList4.opList]
-type=OpDesc
-eventq_index=0
-opClass=MemRead
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5]
-type=FUDesc
-children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
-count=4
-eventq_index=0
-opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
-
-[system.cpu.fuPool.FUList5.opList00]
-type=OpDesc
-eventq_index=0
-opClass=SimdAdd
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList01]
-type=OpDesc
-eventq_index=0
-opClass=SimdAddAcc
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList02]
-type=OpDesc
-eventq_index=0
-opClass=SimdAlu
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList03]
-type=OpDesc
-eventq_index=0
-opClass=SimdCmp
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList04]
-type=OpDesc
-eventq_index=0
-opClass=SimdCvt
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList05]
-type=OpDesc
-eventq_index=0
-opClass=SimdMisc
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList06]
-type=OpDesc
-eventq_index=0
-opClass=SimdMult
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList07]
-type=OpDesc
-eventq_index=0
-opClass=SimdMultAcc
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList08]
-type=OpDesc
-eventq_index=0
-opClass=SimdShift
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList09]
-type=OpDesc
-eventq_index=0
-opClass=SimdShiftAcc
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList10]
-type=OpDesc
-eventq_index=0
-opClass=SimdSqrt
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList11]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatAdd
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList12]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatAlu
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList13]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatCmp
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList14]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatCvt
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList15]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatDiv
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList16]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatMisc
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList17]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatMult
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList18]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatMultAcc
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList5.opList19]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatSqrt
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList6]
-type=FUDesc
-children=opList
-count=0
-eventq_index=0
-opList=system.cpu.fuPool.FUList6.opList
-
-[system.cpu.fuPool.FUList6.opList]
-type=OpDesc
-eventq_index=0
-opClass=MemWrite
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList7]
-type=FUDesc
-children=opList0 opList1
-count=4
-eventq_index=0
-opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
-
-[system.cpu.fuPool.FUList7.opList0]
-type=OpDesc
-eventq_index=0
-opClass=MemRead
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList7.opList1]
-type=OpDesc
-eventq_index=0
-opClass=MemWrite
-opLat=1
-pipelined=true
-
-[system.cpu.fuPool.FUList8]
-type=FUDesc
-children=opList
-count=1
-eventq_index=0
-opList=system.cpu.fuPool.FUList8.opList
-
-[system.cpu.fuPool.FUList8.opList]
-type=OpDesc
-eventq_index=0
-opClass=IprAccess
-opLat=3
-pipelined=false
-
-[system.cpu.icache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=2
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=true
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=131072
-system=system
-tags=system.cpu.icache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=true
-cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.slave[0]
-
-[system.cpu.icache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=131072
-
-[system.cpu.interrupts]
-type=AlphaInterrupts
-eventq_index=0
-
-[system.cpu.isa]
-type=AlphaISA
-eventq_index=0
-system=system
-
-[system.cpu.itb]
-type=AlphaTLB
-eventq_index=0
-size=48
-
-[system.cpu.l2cache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615:0:0:0:0
-assoc=8
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=20
-is_read_only=false
-max_miss_count=0
-mshrs=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
-sequential_access=false
-size=2097152
-system=system
-tags=system.cpu.l2cache.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.toL2Bus.master[0]
-mem_side=system.membus.slave[1]
-
-[system.cpu.l2cache.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=2097152
-
-[system.cpu.toL2Bus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=false
-power_model=Null
-response_latency=1
-snoop_filter=system.cpu.toL2Bus.snoop_filter
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
-
-[system.cpu.toL2Bus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=0
-max_capacity=8388608
-system=system
-
-[system.cpu.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
-cwd=build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing
-drivers=
-egid=100
-env=
-errout=cerr
-euid=100
-eventq_index=0
-executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/eon
-gid=100
-input=cin
-kvmInSE=false
-max_stack_size=67108864
-output=cout
-pid=100
-ppid=99
-simpoint=0
-system=system
-uid=100
-useArchPT=false
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.membus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=true
-power_model=Null
-response_latency=2
-snoop_filter=system.membus.snoop_filter
-snoop_response_latency=4
-system=system
-use_default_range=false
-width=16
-master=system.physmem.port
-slave=system.system_port system.cpu.l2cache.mem_side
-
-[system.membus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=1
-max_capacity=8388608
-system=system
-
-[system.physmem]
-type=DRAMCtrl
-IDD0=0.055000
-IDD02=0.000000
-IDD2N=0.032000
-IDD2N2=0.000000
-IDD2P0=0.000000
-IDD2P02=0.000000
-IDD2P1=0.032000
-IDD2P12=0.000000
-IDD3N=0.038000
-IDD3N2=0.000000
-IDD3P0=0.000000
-IDD3P02=0.000000
-IDD3P1=0.038000
-IDD3P12=0.000000
-IDD4R=0.157000
-IDD4R2=0.000000
-IDD4W=0.125000
-IDD4W2=0.000000
-IDD5=0.235000
-IDD52=0.000000
-IDD6=0.020000
-IDD62=0.000000
-VDD=1.500000
-VDD2=0.000000
-activation_limit=4
-addr_mapping=RoRaBaCoCh
-bank_groups_per_rank=0
-banks_per_rank=8
-burst_length=8
-channels=1
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-device_bus_width=8
-device_rowbuffer_size=1024
-device_size=536870912
-devices_per_rank=8
-dll=true
-eventq_index=0
-in_addr_map=true
-kvm_map=true
-max_accesses_per_row=16
-mem_sched_policy=frfcfs
-min_writes_per_switch=16
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-page_policy=open_adaptive
-power_model=Null
-range=0:134217727:0:0:0:0
-ranks_per_channel=2
-read_buffer_size=32
-static_backend_latency=10000
-static_frontend_latency=10000
-tBURST=5000
-tCCD_L=0
-tCK=1250
-tCL=13750
-tCS=2500
-tRAS=35000
-tRCD=13750
-tREFI=7800000
-tRFC=260000
-tRP=13750
-tRRD=6000
-tRRD_L=0
-tRTP=7500
-tRTW=2500
-tWR=15000
-tWTR=7500
-tXAW=30000
-tXP=6000
-tXPDLL=0
-tXS=270000
-tXSDLL=0
-write_buffer_size=64
-write_high_thresh_perc=85
-write_low_thresh_perc=50
-port=system.membus.master[0]
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simerr b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simerr
deleted file mode 100755
index 9c10deefc..000000000
--- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simerr
+++ /dev/null
@@ -1,53 +0,0 @@
-warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
-warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-warn: Prefetch instructions in Alpha do not do anything
-warn: Prefetch instructions in Alpha do not do anything
-warn: Prefetch instructions in Alpha do not do anything
-getting pixel output filename pixels_out.cook
-opening control file chair.control.cook
-opening camera file chair.camera
-opening surfaces file chair.surfaces
-reading data
-processing 8parts
-Grid measure is 6 by 3.0001 by 6
-cell dimension is 0.863065
-Creating grid for list of length 21
-Grid size = 7 by 4 by 7
-Total occupancy = 236
-reading control stream
-reading camera stream
-Writing to chair.cook.ppm
-calculating 15 by 15 image with 196 samples
-col 0. . .
-col 1. . .
-col 2. . .
-col 3. . .
-col 4. . .
-col 5. . .
-col 6. . .
-col 7. . .
-col 8. . .
-col 9. . .
-col 10. . .
-col 11. . .
-col 12. . .
-col 13. . .
-col 14. . .
-Writing to chair.cook.ppm
-0 8 14
-1 8 14
-2 8 14
-3 8 14
-4 8 14
-5 8 14
-6 8 14
-7 8 14
-8 8 14
-9 8 14
-10 8 14
-11 8 14
-12 8 14
-13 8 14
-14 8 14
-warn: ignoring syscall sigprocmask(1, ...)
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout
deleted file mode 100755
index ee5bfc401..000000000
--- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout
+++ /dev/null
@@ -1,17 +0,0 @@
-Redirecting stdout to build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing/simout
-Redirecting stderr to build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing/simerr
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Oct 11 2016 00:00:58
-gem5 started Oct 13 2016 20:19:44
-gem5 executing on e108600-lin, pid 28057
-command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/30.eon/alpha/tru64/o3-timing
-
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-info: Increasing stack size by one page.
-Eon, Version 1.1
-info: Increasing stack size by one page.
-OO-style eon Time= 0.050000
-Exiting @ tick 64255452000 because target called exit()
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt
deleted file mode 100644
index 54dc9e079..000000000
--- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt
+++ /dev/null
@@ -1,1059 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.064255 # Number of seconds simulated
-sim_ticks 64255452000 # Number of ticks simulated
-final_tick 64255452000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 443081 # Simulator instruction rate (inst/s)
-host_op_rate 443081 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 75804731 # Simulator tick rate (ticks/s)
-host_mem_usage 261252 # Number of bytes of host memory used
-host_seconds 847.64 # Real time elapsed on the host
-sim_insts 375574794 # Number of instructions simulated
-sim_ops 375574794 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 64255452000 # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst 220800 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 255296 # Number of bytes read from this memory
-system.physmem.bytes_read::total 476096 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 220800 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 220800 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 3450 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 3989 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 7439 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 3436284 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 3973141 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 7409426 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 3436284 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 3436284 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 3436284 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 3973141 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 7409426 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 7439 # Number of read requests accepted
-system.physmem.writeReqs 0 # Number of write requests accepted
-system.physmem.readBursts 7439 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 476096 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
-system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 476096 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 524 # Per bank write bursts
-system.physmem.perBankRdBursts::1 651 # Per bank write bursts
-system.physmem.perBankRdBursts::2 450 # Per bank write bursts
-system.physmem.perBankRdBursts::3 600 # Per bank write bursts
-system.physmem.perBankRdBursts::4 446 # Per bank write bursts
-system.physmem.perBankRdBursts::5 454 # Per bank write bursts
-system.physmem.perBankRdBursts::6 513 # Per bank write bursts
-system.physmem.perBankRdBursts::7 524 # Per bank write bursts
-system.physmem.perBankRdBursts::8 438 # Per bank write bursts
-system.physmem.perBankRdBursts::9 408 # Per bank write bursts
-system.physmem.perBankRdBursts::10 339 # Per bank write bursts
-system.physmem.perBankRdBursts::11 306 # Per bank write bursts
-system.physmem.perBankRdBursts::12 414 # Per bank write bursts
-system.physmem.perBankRdBursts::13 540 # Per bank write bursts
-system.physmem.perBankRdBursts::14 452 # Per bank write bursts
-system.physmem.perBankRdBursts::15 380 # Per bank write bursts
-system.physmem.perBankWrBursts::0 0 # Per bank write bursts
-system.physmem.perBankWrBursts::1 0 # Per bank write bursts
-system.physmem.perBankWrBursts::2 0 # Per bank write bursts
-system.physmem.perBankWrBursts::3 0 # Per bank write bursts
-system.physmem.perBankWrBursts::4 0 # Per bank write bursts
-system.physmem.perBankWrBursts::5 0 # Per bank write bursts
-system.physmem.perBankWrBursts::6 0 # Per bank write bursts
-system.physmem.perBankWrBursts::7 0 # Per bank write bursts
-system.physmem.perBankWrBursts::8 0 # Per bank write bursts
-system.physmem.perBankWrBursts::9 0 # Per bank write bursts
-system.physmem.perBankWrBursts::10 0 # Per bank write bursts
-system.physmem.perBankWrBursts::11 0 # Per bank write bursts
-system.physmem.perBankWrBursts::12 0 # Per bank write bursts
-system.physmem.perBankWrBursts::13 0 # Per bank write bursts
-system.physmem.perBankWrBursts::14 0 # Per bank write bursts
-system.physmem.perBankWrBursts::15 0 # Per bank write bursts
-system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 64255349500 # Total gap between requests
-system.physmem.readPktSize::0 0 # Read request sizes (log2)
-system.physmem.readPktSize::1 0 # Read request sizes (log2)
-system.physmem.readPktSize::2 0 # Read request sizes (log2)
-system.physmem.readPktSize::3 0 # Read request sizes (log2)
-system.physmem.readPktSize::4 0 # Read request sizes (log2)
-system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 7439 # Read request sizes (log2)
-system.physmem.writePktSize::0 0 # Write request sizes (log2)
-system.physmem.writePktSize::1 0 # Write request sizes (log2)
-system.physmem.writePktSize::2 0 # Write request sizes (log2)
-system.physmem.writePktSize::3 0 # Write request sizes (log2)
-system.physmem.writePktSize::4 0 # Write request sizes (log2)
-system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 0 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 3982 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 2008 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 898 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 438 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 111 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 1349 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 351.644181 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 209.715239 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 347.080632 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 429 31.80% 31.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 311 23.05% 54.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 151 11.19% 66.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 87 6.45% 72.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 68 5.04% 77.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 39 2.89% 80.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 38 2.82% 83.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 30 2.22% 85.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 196 14.53% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 1349 # Bytes accessed per row activation
-system.physmem.totQLat 165053250 # Total ticks spent queuing
-system.physmem.totMemAccLat 304534500 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 37195000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 22187.56 # Average queueing delay per DRAM burst
-system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 40937.56 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 7.41 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 7.41 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
-system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 0.06 # Data bus utilization in percentage
-system.physmem.busUtilRead 0.06 # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
-system.physmem.readRowHits 6085 # Number of row buffer hits during reads
-system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 81.80 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 8637632.68 # Average gap between requests
-system.physmem.pageHitRate 81.80 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 5454960 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 2880405 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 29716680 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 128459760.000000 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 63558420 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 5463840 # Energy for precharge background per rank (pJ)
-system.physmem_0.actPowerDownEnergy 397888500 # Energy for active power-down per rank (pJ)
-system.physmem_0.prePowerDownEnergy 152192640 # Energy for precharge power-down per rank (pJ)
-system.physmem_0.selfRefreshEnergy 15095921460 # Energy for self refresh per rank (pJ)
-system.physmem_0.totalEnergy 15881536665 # Total energy per rank (pJ)
-system.physmem_0.averagePower 247.162475 # Core power per rank (mW)
-system.physmem_0.totalIdleTime 64101767750 # Total Idle time Per DRAM Rank
-system.physmem_0.memoryStateTime::IDLE 8572500 # Time in different power states
-system.physmem_0.memoryStateTime::REF 54520000 # Time in different power states
-system.physmem_0.memoryStateTime::SREF 62832935750 # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN 396328750 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 90536500 # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN 872558500 # Time in different power states
-system.physmem_1.actEnergy 4212600 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 2239050 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 23397780 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 172713840.000000 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 67790100 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 10409760 # Energy for precharge background per rank (pJ)
-system.physmem_1.actPowerDownEnergy 394655460 # Energy for active power-down per rank (pJ)
-system.physmem_1.prePowerDownEnergy 234464640 # Energy for precharge power-down per rank (pJ)
-system.physmem_1.selfRefreshEnergy 15065735460 # Energy for self refresh per rank (pJ)
-system.physmem_1.totalEnergy 15975618690 # Total energy per rank (pJ)
-system.physmem_1.averagePower 248.626662 # Core power per rank (mW)
-system.physmem_1.totalIdleTime 64079571000 # Total Idle time Per DRAM Rank
-system.physmem_1.memoryStateTime::IDLE 20607500 # Time in different power states
-system.physmem_1.memoryStateTime::REF 73504000 # Time in different power states
-system.physmem_1.memoryStateTime::SREF 62603628000 # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN 610590500 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 81643000 # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN 865479000 # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 64255452000 # Cumulative time (in ticks) in various power states
-system.cpu.branchPred.lookups 47858833 # Number of BP lookups
-system.cpu.branchPred.condPredicted 27887840 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 573531 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 23350857 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 19575248 # Number of BTB hits
-system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 83.830962 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 8687752 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 1405 # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups 2338807 # Number of indirect predictor lookups.
-system.cpu.branchPred.indirectHits 2307668 # Number of indirect target hits.
-system.cpu.branchPred.indirectMisses 31139 # Number of indirect misses.
-system.cpu.branchPredindirectMispredicted 111329 # Number of mispredicted indirect branches.
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.dtb.fetch_hits 0 # ITB hits
-system.cpu.dtb.fetch_misses 0 # ITB misses
-system.cpu.dtb.fetch_acv 0 # ITB acv
-system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 98831063 # DTB read hits
-system.cpu.dtb.read_misses 28342 # DTB read misses
-system.cpu.dtb.read_acv 849 # DTB read access violations
-system.cpu.dtb.read_accesses 98859405 # DTB read accesses
-system.cpu.dtb.write_hits 75501441 # DTB write hits
-system.cpu.dtb.write_misses 1449 # DTB write misses
-system.cpu.dtb.write_acv 3 # DTB write access violations
-system.cpu.dtb.write_accesses 75502890 # DTB write accesses
-system.cpu.dtb.data_hits 174332504 # DTB hits
-system.cpu.dtb.data_misses 29791 # DTB misses
-system.cpu.dtb.data_acv 852 # DTB access violations
-system.cpu.dtb.data_accesses 174362295 # DTB accesses
-system.cpu.itb.fetch_hits 46958874 # ITB hits
-system.cpu.itb.fetch_misses 432 # ITB misses
-system.cpu.itb.fetch_acv 5 # ITB acv
-system.cpu.itb.fetch_accesses 46959306 # ITB accesses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.read_acv 0 # DTB read access violations
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.itb.write_acv 0 # DTB write access violations
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.data_hits 0 # DTB hits
-system.cpu.itb.data_misses 0 # DTB misses
-system.cpu.itb.data_acv 0 # DTB access violations
-system.cpu.itb.data_accesses 0 # DTB accesses
-system.cpu.workload.num_syscalls 215 # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON 64255452000 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 128510907 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 47429437 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 424837073 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 47858833 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 30570668 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 80085665 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 1247776 # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles 13 # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles 297 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 13295 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 79 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 46958874 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 226146 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 128152674 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 3.315086 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.349633 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 53168247 41.49% 41.49% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 4330315 3.38% 44.87% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 6713619 5.24% 50.11% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 5107106 3.99% 54.09% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 10970093 8.56% 62.65% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 7524949 5.87% 68.52% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 5303300 4.14% 72.66% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 1847075 1.44% 74.10% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 33187970 25.90% 100.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 128152674 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.372411 # Number of branch fetches per cycle
-system.cpu.fetch.rate 3.305844 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 42097840 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 13659925 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 67904561 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 3870622 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 619726 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 8883416 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 4205 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 421920314 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 13831 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 619726 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 43662514 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 3075430 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 529984 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 70109441 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 10155579 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 419899923 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 443686 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 2538434 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents 2849903 # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents 3565226 # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands 273976095 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 552171720 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 393714640 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 158457079 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 259532319 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 14443776 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 37564 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 298 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 15805009 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 99734698 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 76520876 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 11857010 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 9264279 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 392184083 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 290 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 389210637 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 196187 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 16609578 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 7664570 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 75 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 128152674 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 3.037086 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 2.181467 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 17313559 13.51% 13.51% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 19411245 15.15% 28.66% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 22012922 17.18% 45.83% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 17948678 14.01% 59.84% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 19074074 14.88% 74.72% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 13271943 10.36% 85.08% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 8797733 6.87% 91.95% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 6095055 4.76% 96.70% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 4227465 3.30% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 128152674 # Number of insts issued each cycle
-system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 253970 1.29% 1.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 2 0.00% 1.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 1.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 138834 0.71% 2.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 79013 0.40% 2.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 3594 0.02% 2.42% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 3443745 17.54% 19.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 19.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 1647907 8.39% 28.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMisc 0 0.00% 28.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 28.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 28.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 3789083 19.30% 47.66% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 1973005 10.05% 57.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMemRead 5150981 26.24% 83.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMemWrite 3150937 16.05% 100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 146989472 37.77% 37.77% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 2128309 0.55% 38.32% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 38.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 36418443 9.36% 47.68% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 7355119 1.89% 49.57% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 2800065 0.72% 50.29% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 16556449 4.25% 54.54% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 54.54% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 1584163 0.41% 54.95% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 54.95% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.95% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.95% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.95% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.95% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.95% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.95% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.95% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.95% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.95% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.95% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.95% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.95% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.95% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.95% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.95% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.95% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.95% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.95% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.95% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.95% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.95% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 48929897 12.57% 67.52% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 31583157 8.11% 75.63% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMemRead 50573051 12.99% 88.63% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMemWrite 44258931 11.37% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 389210637 # Type of FU issued
-system.cpu.iq.rate 3.028619 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 19631071 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.050438 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 593561800 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 242185048 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 227933309 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 332839406 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 166679024 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 158288157 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 235646895 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 173161232 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 19364531 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 4980212 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 92962 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 70485 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 3000148 # Number of stores squashed
-system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 382479 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 3666 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 619726 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 1854972 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 162334 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 415907776 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 109026 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 99734698 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 76520876 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 290 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 8920 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 152322 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 70485 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 412161 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 230865 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 643026 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 387624331 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 98860283 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 1586306 # Number of squashed instructions skipped in execute
-system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 23723403 # number of nop insts executed
-system.cpu.iew.exec_refs 174363211 # number of memory reference insts executed
-system.cpu.iew.exec_branches 45864022 # Number of branches executed
-system.cpu.iew.exec_stores 75502928 # Number of stores executed
-system.cpu.iew.exec_rate 3.016276 # Inst execution rate
-system.cpu.iew.wb_sent 386484413 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 386221466 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 192314001 # num instructions producing a value
-system.cpu.iew.wb_consumers 273852153 # num instructions consuming a value
-system.cpu.iew.wb_rate 3.005359 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.702255 # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts 17244606 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 569369 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 125687681 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 3.171867 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 3.248348 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 42136978 33.53% 33.53% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 17569311 13.98% 47.50% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 8725420 6.94% 54.45% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 9050963 7.20% 61.65% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 6228783 4.96% 66.60% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 4113989 3.27% 69.88% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 4743327 3.77% 73.65% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 2404790 1.91% 75.56% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 30714120 24.44% 100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 125687681 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 398664569 # Number of instructions committed
-system.cpu.commit.committedOps 398664569 # Number of ops (including micro ops) committed
-system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 168275214 # Number of memory references committed
-system.cpu.commit.loads 94754486 # Number of loads committed
-system.cpu.commit.membars 0 # Number of memory barriers committed
-system.cpu.commit.branches 44587530 # Number of branches committed
-system.cpu.commit.fp_insts 155295106 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 316365825 # Number of committed integer instructions.
-system.cpu.commit.function_calls 8007752 # Number of function calls committed.
-system.cpu.commit.op_class_0::No_OpClass 23123356 5.80% 5.80% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu 141652533 35.53% 41.33% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult 2124322 0.53% 41.86% # Class of committed instruction
-system.cpu.commit.op_class_0::IntDiv 0 0.00% 41.86% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatAdd 35620060 8.93% 50.80% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCmp 7072549 1.77% 52.57% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCvt 2735231 0.69% 53.26% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMult 16498021 4.14% 57.40% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 57.40% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatDiv 1563283 0.39% 57.79% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMisc 0 0.00% 57.79% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 57.79% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAdd 0 0.00% 57.79% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 57.79% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAlu 0 0.00% 57.79% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCmp 0 0.00% 57.79% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCvt 0 0.00% 57.79% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMisc 0 0.00% 57.79% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMult 0 0.00% 57.79% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 57.79% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShift 0 0.00% 57.79% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 57.79% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 57.79% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 57.79% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 57.79% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 57.79% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 57.79% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 57.79% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 57.79% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 57.79% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 57.79% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 57.79% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead 46072297 11.56% 69.35% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite 30396955 7.62% 76.97% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMemRead 48682189 12.21% 89.18% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMemWrite 43123773 10.82% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total 398664569 # Class of committed instruction
-system.cpu.commit.bw_lim_events 30714120 # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads 510879759 # The number of ROB reads
-system.cpu.rob.rob_writes 834289662 # The number of ROB writes
-system.cpu.timesIdled 3136 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 358233 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts 375574794 # Number of Instructions Simulated
-system.cpu.committedOps 375574794 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 0.342171 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.342171 # CPI: Total CPI of All Threads
-system.cpu.ipc 2.922513 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 2.922513 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 385452576 # number of integer regfile reads
-system.cpu.int_regfile_writes 165252743 # number of integer regfile writes
-system.cpu.fp_regfile_reads 154537274 # number of floating regfile reads
-system.cpu.fp_regfile_writes 102070951 # number of floating regfile writes
-system.cpu.misc_regfile_reads 350572 # number of misc regfile reads
-system.cpu.misc_regfile_writes 1 # number of misc regfile writes
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 64255452000 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements 774 # number of replacements
-system.cpu.dcache.tags.tagsinuse 3291.451205 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 152580730 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 4174 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 36555.038333 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 3291.451205 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.803577 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.803577 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024 3400 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 211 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4 3116 # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024 0.830078 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 305207642 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 305207642 # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 64255452000 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data 79079190 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 79079190 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 73501534 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 73501534 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 6 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 6 # number of LoadLockedReq hits
-system.cpu.dcache.demand_hits::cpu.data 152580724 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 152580724 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 152580724 # number of overall hits
-system.cpu.dcache.overall_hits::total 152580724 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 1810 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 1810 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 19194 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 19194 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 21004 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 21004 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 21004 # number of overall misses
-system.cpu.dcache.overall_misses::total 21004 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 137671000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 137671000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 1331646003 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 1331646003 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 1469317003 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 1469317003 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 1469317003 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 1469317003 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 79081000 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 79081000 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 73520728 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 73520728 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 6 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 6 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 152601728 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 152601728 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 152601728 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 152601728 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000023 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.000023 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000261 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.000261 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.000138 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.000138 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.000138 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.000138 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 76061.325967 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 76061.325967 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69378.243357 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 69378.243357 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 69954.151733 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 69954.151733 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 69954.151733 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 69954.151733 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 57813 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 94 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 689 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 83.908563 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 94 # average number of cycles each access was blocked
-system.cpu.dcache.writebacks::writebacks 655 # number of writebacks
-system.cpu.dcache.writebacks::total 655 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 824 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 824 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16006 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 16006 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 16830 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 16830 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 16830 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 16830 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 986 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 986 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3188 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 3188 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 4174 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 4174 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 4174 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 4174 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 83512000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 83512000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 299984000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 299984000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 383496000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 383496000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 383496000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 383496000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000012 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000012 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000043 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 84697.768763 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 84697.768763 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 94097.867001 # average WriteReq mshr miss latency
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-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 80020.144928 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 80020.144928 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 83644.018583 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 83644.018583 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 80020.144928 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 84033.467034 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 82172.200565 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 80020.144928 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 84033.467034 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 82172.200565 # average overall mshr miss latency
-system.cpu.toL2Bus.snoop_filter.tot_requests 11139 # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests 2906 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 64255452000 # Cumulative time (in ticks) in various power states
-system.cpu.toL2Bus.trans_dist::ReadResp 5045 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty 655 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean 2132 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict 119 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 3188 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 3188 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq 4059 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq 986 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10250 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9122 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 19372 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 396224 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 309056 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 705280 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 0 # Total snoops (count)
-system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples 8233 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 8233 100.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 8233 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 8356500 # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 6088500 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 6261000 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.snoop_filter.tot_requests 7439 # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 64255452000 # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadResp 4311 # Transaction distribution
-system.membus.trans_dist::ReadExReq 3128 # Transaction distribution
-system.membus.trans_dist::ReadExResp 3128 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 4311 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14878 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 14878 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 476096 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 476096 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples 7439 # Request fanout histogram
-system.membus.snoop_fanout::mean 0 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 7439 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 7439 # Request fanout histogram
-system.membus.reqLayer0.occupancy 9229500 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer1.occupancy 39165500 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
-
----------- End Simulation Statistics ----------
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini
deleted file mode 100644
index 7b7341967..000000000
--- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini
+++ /dev/null
@@ -1,366 +0,0 @@
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=false
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=System
-children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
-boot_osflags=a
-cache_line_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-exit_on_work_items=false
-init_param=0
-kernel=
-kernel_addr_check=true
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=timing
-mem_ranges=
-memories=system.physmem
-mmap_using_noreserve=false
-multi_thread=false
-num_work_ids=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-readfile=
-symbolfile=
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[0]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu]
-type=TimingSimpleCPU
-children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
-branchPred=Null
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=0
-default_p_state=UNDEFINED
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu.dtb
-eventq_index=0
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu.interrupts
-isa=system.cpu.isa
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-simpoint_start_insts=
-socket_id=0
-switched_out=false
-system=system
-tracer=system.cpu.tracer
-workload=system.cpu.workload
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.dcache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=2
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=false
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=262144
-system=system
-tags=system.cpu.dcache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.slave[1]
-
-[system.cpu.dcache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=262144
-
-[system.cpu.dtb]
-type=AlphaTLB
-eventq_index=0
-size=64
-
-[system.cpu.icache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=2
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=true
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=131072
-system=system
-tags=system.cpu.icache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=true
-cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.slave[0]
-
-[system.cpu.icache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=131072
-
-[system.cpu.interrupts]
-type=AlphaInterrupts
-eventq_index=0
-
-[system.cpu.isa]
-type=AlphaISA
-eventq_index=0
-system=system
-
-[system.cpu.itb]
-type=AlphaTLB
-eventq_index=0
-size=48
-
-[system.cpu.l2cache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=8
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=20
-is_read_only=false
-max_miss_count=0
-mshrs=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
-sequential_access=false
-size=2097152
-system=system
-tags=system.cpu.l2cache.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.toL2Bus.master[0]
-mem_side=system.membus.slave[1]
-
-[system.cpu.l2cache.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=2097152
-
-[system.cpu.toL2Bus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=false
-power_model=Null
-response_latency=1
-snoop_filter=system.cpu.toL2Bus.snoop_filter
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
-
-[system.cpu.toL2Bus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=0
-max_capacity=8388608
-system=system
-
-[system.cpu.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
-cwd=build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-timing
-drivers=
-egid=100
-env=
-errout=cerr
-euid=100
-eventq_index=0
-executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/eon
-gid=100
-input=cin
-kvmInSE=false
-max_stack_size=67108864
-output=cout
-pid=100
-ppid=99
-simpoint=0
-system=system
-uid=100
-useArchPT=false
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.membus]
-type=CoherentXBar
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=true
-power_model=Null
-response_latency=2
-snoop_filter=Null
-snoop_response_latency=4
-system=system
-use_default_range=false
-width=16
-master=system.physmem.port
-slave=system.system_port system.cpu.l2cache.mem_side
-
-[system.physmem]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-eventq_index=0
-in_addr_map=true
-latency=30000
-latency_var=0
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-range=0:134217727
-port=system.membus.master[0]
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simerr b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simerr
deleted file mode 100755
index 870cfd899..000000000
--- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simerr
+++ /dev/null
@@ -1,52 +0,0 @@
-warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-warn: Prefetch instructions in Alpha do not do anything
-warn: Prefetch instructions in Alpha do not do anything
-warn: Prefetch instructions in Alpha do not do anything
-getting pixel output filename pixels_out.cook
-opening control file chair.control.cook
-opening camera file chair.camera
-opening surfaces file chair.surfaces
-reading data
-processing 8parts
-Grid measure is 6 by 3.0001 by 6
-cell dimension is 0.863065
-Creating grid for list of length 21
-Grid size = 7 by 4 by 7
-Total occupancy = 236
-reading control stream
-reading camera stream
-Writing to chair.cook.ppm
-calculating 15 by 15 image with 196 samples
-col 0. . .
-col 1. . .
-col 2. . .
-col 3. . .
-col 4. . .
-col 5. . .
-col 6. . .
-col 7. . .
-col 8. . .
-col 9. . .
-col 10. . .
-col 11. . .
-col 12. . .
-col 13. . .
-col 14. . .
-Writing to chair.cook.ppm
-0 8 14
-1 8 14
-2 8 14
-3 8 14
-4 8 14
-5 8 14
-6 8 14
-7 8 14
-8 8 14
-9 8 14
-10 8 14
-11 8 14
-12 8 14
-13 8 14
-14 8 14
-warn: ignoring syscall sigprocmask(1, ...)
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout
deleted file mode 100755
index 1c6cb75e4..000000000
--- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout
+++ /dev/null
@@ -1,17 +0,0 @@
-Redirecting stdout to build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-timing/simout
-Redirecting stderr to build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-timing/simerr
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Jul 19 2016 12:23:51
-gem5 started Jul 21 2016 14:09:28
-gem5 executing on e108600-lin, pid 4302
-command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/30.eon/alpha/tru64/simple-timing
-
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-info: Increasing stack size by one page.
-Eon, Version 1.1
-info: Increasing stack size by one page.
-OO-style eon Time= 0.566667
-Exiting @ tick 567385356500 because target called exit()
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt
deleted file mode 100644
index 6d86d3450..000000000
--- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt
+++ /dev/null
@@ -1,555 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.567393 # Number of seconds simulated
-sim_ticks 567392530500 # Number of ticks simulated
-final_tick 567392530500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1833225 # Simulator instruction rate (inst/s)
-host_op_rate 1833225 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2609105944 # Simulator tick rate (ticks/s)
-host_mem_usage 258692 # Number of bytes of host memory used
-host_seconds 217.47 # Real time elapsed on the host
-sim_insts 398664609 # Number of instructions simulated
-sim_ops 398664609 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 567392530500 # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst 205120 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 254016 # Number of bytes read from this memory
-system.physmem.bytes_read::total 459136 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 205120 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 205120 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 3205 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 3969 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 7174 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 361513 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 447690 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 809203 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 361513 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 361513 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 361513 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 447690 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 809203 # Total bandwidth to/from this memory (bytes/s)
-system.pwrStateResidencyTicks::UNDEFINED 567392530500 # Cumulative time (in ticks) in various power states
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.dtb.fetch_hits 0 # ITB hits
-system.cpu.dtb.fetch_misses 0 # ITB misses
-system.cpu.dtb.fetch_acv 0 # ITB acv
-system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 94754490 # DTB read hits
-system.cpu.dtb.read_misses 21 # DTB read misses
-system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 94754511 # DTB read accesses
-system.cpu.dtb.write_hits 73520730 # DTB write hits
-system.cpu.dtb.write_misses 35 # DTB write misses
-system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 73520765 # DTB write accesses
-system.cpu.dtb.data_hits 168275220 # DTB hits
-system.cpu.dtb.data_misses 56 # DTB misses
-system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 168275276 # DTB accesses
-system.cpu.itb.fetch_hits 398664666 # ITB hits
-system.cpu.itb.fetch_misses 173 # ITB misses
-system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 398664839 # ITB accesses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.read_acv 0 # DTB read access violations
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.itb.write_acv 0 # DTB write access violations
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.data_hits 0 # DTB hits
-system.cpu.itb.data_misses 0 # DTB misses
-system.cpu.itb.data_acv 0 # DTB access violations
-system.cpu.itb.data_accesses 0 # DTB accesses
-system.cpu.workload.num_syscalls 215 # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON 567392530500 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 1134785061 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 398664609 # Number of instructions committed
-system.cpu.committedOps 398664609 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 316365921 # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses 155295119 # Number of float alu accesses
-system.cpu.num_func_calls 16015498 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 25997790 # number of instructions that are conditional controls
-system.cpu.num_int_insts 316365921 # number of integer instructions
-system.cpu.num_fp_insts 155295119 # number of float instructions
-system.cpu.num_int_register_reads 372938779 # number of times the integer registers were read
-system.cpu.num_int_register_writes 159335870 # number of times the integer registers were written
-system.cpu.num_fp_register_reads 151776196 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 100196481 # number of times the floating registers were written
-system.cpu.num_mem_refs 168275276 # number of memory refs
-system.cpu.num_load_insts 94754511 # Number of load instructions
-system.cpu.num_store_insts 73520765 # Number of store instructions
-system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 1134785061 # Number of busy cycles
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.Branches 44587535 # Number of branches fetched
-system.cpu.op_class::No_OpClass 23123356 5.80% 5.80% # Class of executed instruction
-system.cpu.op_class::IntAlu 141652567 35.53% 41.33% # Class of executed instruction
-system.cpu.op_class::IntMult 2124322 0.53% 41.86% # Class of executed instruction
-system.cpu.op_class::IntDiv 0 0.00% 41.86% # Class of executed instruction
-system.cpu.op_class::FloatAdd 35620060 8.93% 50.80% # Class of executed instruction
-system.cpu.op_class::FloatCmp 7072549 1.77% 52.57% # Class of executed instruction
-system.cpu.op_class::FloatCvt 2735231 0.69% 53.26% # Class of executed instruction
-system.cpu.op_class::FloatMult 16498021 4.14% 57.40% # Class of executed instruction
-system.cpu.op_class::FloatMultAcc 0 0.00% 57.40% # Class of executed instruction
-system.cpu.op_class::FloatDiv 1563283 0.39% 57.79% # Class of executed instruction
-system.cpu.op_class::FloatMisc 0 0.00% 57.79% # Class of executed instruction
-system.cpu.op_class::FloatSqrt 0 0.00% 57.79% # Class of executed instruction
-system.cpu.op_class::SimdAdd 0 0.00% 57.79% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc 0 0.00% 57.79% # Class of executed instruction
-system.cpu.op_class::SimdAlu 0 0.00% 57.79% # Class of executed instruction
-system.cpu.op_class::SimdCmp 0 0.00% 57.79% # Class of executed instruction
-system.cpu.op_class::SimdCvt 0 0.00% 57.79% # Class of executed instruction
-system.cpu.op_class::SimdMisc 0 0.00% 57.79% # Class of executed instruction
-system.cpu.op_class::SimdMult 0 0.00% 57.79% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc 0 0.00% 57.79% # Class of executed instruction
-system.cpu.op_class::SimdShift 0 0.00% 57.79% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc 0 0.00% 57.79% # Class of executed instruction
-system.cpu.op_class::SimdSqrt 0 0.00% 57.79% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd 0 0.00% 57.79% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu 0 0.00% 57.79% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp 0 0.00% 57.79% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt 0 0.00% 57.79% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv 0 0.00% 57.79% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc 0 0.00% 57.79% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult 0 0.00% 57.79% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc 0 0.00% 57.79% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt 0 0.00% 57.79% # Class of executed instruction
-system.cpu.op_class::MemRead 46072316 11.56% 69.35% # Class of executed instruction
-system.cpu.op_class::MemWrite 30396985 7.62% 76.97% # Class of executed instruction
-system.cpu.op_class::FloatMemRead 48682195 12.21% 89.18% # Class of executed instruction
-system.cpu.op_class::FloatMemWrite 43123780 10.82% 100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 398664665 # Class of executed instruction
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 567392530500 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements 764 # number of replacements
-system.cpu.dcache.tags.tagsinuse 3288.789389 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 168271068 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 4152 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 40527.713873 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 3288.789389 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.802927 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.802927 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024 3388 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 39 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3 210 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4 3112 # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024 0.827148 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 336554592 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 336554592 # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 567392530500 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data 94753540 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 94753540 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 73517528 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 73517528 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 168271068 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 168271068 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 168271068 # number of overall hits
-system.cpu.dcache.overall_hits::total 168271068 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 950 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 950 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 3202 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 3202 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 4152 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 4152 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 4152 # number of overall misses
-system.cpu.dcache.overall_misses::total 4152 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 53715500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 53715500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 198735000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 198735000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 252450500 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 252450500 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 252450500 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 252450500 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 94754490 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 94754490 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 73520730 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 73520730 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 168275220 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 168275220 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 168275220 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 168275220 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000010 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.000010 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000044 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.000044 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56542.631579 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 56542.631579 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62065.896315 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 62065.896315 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 60802.143545 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 60802.143545 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 60802.143545 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 60802.143545 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.writebacks::writebacks 649 # number of writebacks
-system.cpu.dcache.writebacks::total 649 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 950 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 950 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3202 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 3202 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 4152 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 52765500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 52765500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 195533000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 195533000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 248298500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 248298500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 248298500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 248298500 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000044 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 55542.631579 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 55542.631579 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61065.896315 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61065.896315 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 59802.143545 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 59802.143545 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 59802.143545 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 59802.143545 # average overall mshr miss latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 567392530500 # Cumulative time (in ticks) in various power states
-system.cpu.icache.tags.replacements 1769 # number of replacements
-system.cpu.icache.tags.tagsinuse 1795.076643 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 398660993 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 3673 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 108538.250204 # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 1795.076643 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.876502 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.876502 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024 1904 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1 138 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2 91 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3 251 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4 1375 # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024 0.929688 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 797333005 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 797333005 # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 567392530500 # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst 398660993 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 398660993 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 398660993 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 398660993 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 398660993 # number of overall hits
-system.cpu.icache.overall_hits::total 398660993 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 3673 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 3673 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 3673 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 3673 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 3673 # number of overall misses
-system.cpu.icache.overall_misses::total 3673 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 208020000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 208020000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 208020000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 208020000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 208020000 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 208020000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 398664666 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 398664666 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 398664666 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 398664666 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 398664666 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 398664666 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000009 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.000009 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.000009 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.000009 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.000009 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.000009 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56634.903349 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 56634.903349 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 56634.903349 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 56634.903349 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 56634.903349 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 56634.903349 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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-system.cpu.icache.writebacks::writebacks 1769 # number of writebacks
-system.cpu.icache.writebacks::total 1769 # number of writebacks
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3673 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 3673 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 3673 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 3673 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 3673 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 3673 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 204347000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 204347000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 204347000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 204347000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 204347000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 204347000 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.000009 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.000009 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 55634.903349 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 55634.903349 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 55634.903349 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 55634.903349 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 55634.903349 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 55634.903349 # average overall mshr miss latency
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 567392530500 # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.tags.replacements 0 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 6481.659208 # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs 3184 # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs 7174 # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs 0.443825 # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 2770.348214 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 3711.310994 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst 0.084544 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data 0.113260 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total 0.197805 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024 7174 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1 116 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2 75 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3 392 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4 6535 # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024 0.218933 # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses 90038 # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses 90038 # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 567392530500 # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.WritebackDirty_hits::writebacks 649 # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total 649 # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks 1769 # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total 1769 # number of WritebackClean hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data 60 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total 60 # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 468 # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total 468 # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data 123 # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total 123 # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst 468 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 183 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 651 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst 468 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 183 # number of overall hits
-system.cpu.l2cache.overall_hits::total 651 # number of overall hits
-system.cpu.l2cache.ReadExReq_misses::cpu.data 3142 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 3142 # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3205 # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total 3205 # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data 827 # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total 827 # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst 3205 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 3969 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 7174 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst 3205 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 3969 # number of overall misses
-system.cpu.l2cache.overall_misses::total 7174 # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 190095000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 190095000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 193914000 # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total 193914000 # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 50040500 # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total 50040500 # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 193914000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 240135500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 434049500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 193914000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 240135500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 434049500 # number of overall miss cycles
-system.cpu.l2cache.WritebackDirty_accesses::writebacks 649 # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total 649 # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks 1769 # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total 1769 # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 3202 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 3202 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 3673 # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total 3673 # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 950 # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total 950 # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst 3673 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 4152 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 7825 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 3673 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 4152 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 7825 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.981262 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 0.981262 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.872584 # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.872584 # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.870526 # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.870526 # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.872584 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.955925 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.916805 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.872584 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.955925 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.916805 # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60501.273074 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60501.273074 # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60503.588144 # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60503.588144 # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60508.464329 # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60508.464329 # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60503.588144 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60502.771479 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 60503.136326 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60503.588144 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60502.771479 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 60503.136326 # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3142 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 3142 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3205 # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3205 # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 827 # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total 827 # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 3205 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 3969 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 7174 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 3205 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 3969 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 7174 # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 158675000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 158675000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 161864000 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 161864000 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 41770500 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 41770500 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 161864000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 200445500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 362309500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 161864000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 200445500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 362309500 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.981262 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.981262 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.872584 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.870526 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.870526 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.916805 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.916805 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50501.273074 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50501.273074 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50503.588144 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50503.588144 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50508.464329 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50508.464329 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50503.588144 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50502.771479 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50503.136326 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50503.588144 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50502.771479 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50503.136326 # average overall mshr miss latency
-system.cpu.toL2Bus.snoop_filter.tot_requests 10358 # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests 2533 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 567392530500 # Cumulative time (in ticks) in various power states
-system.cpu.toL2Bus.trans_dist::ReadResp 4623 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty 649 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean 1769 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict 115 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 3202 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 3202 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq 3673 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq 950 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9115 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9068 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 18183 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 348288 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 307264 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 655552 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 0 # Total snoops (count)
-system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples 7825 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 7825 100.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 7825 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 7597000 # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 5509500 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 6228000 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.snoop_filter.tot_requests 7174 # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 567392530500 # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadResp 4032 # Transaction distribution
-system.membus.trans_dist::ReadExReq 3142 # Transaction distribution
-system.membus.trans_dist::ReadExResp 3142 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 4032 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14348 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 14348 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 459136 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 459136 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples 7174 # Request fanout histogram
-system.membus.snoop_fanout::mean 0 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 7174 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 7174 # Request fanout histogram
-system.membus.reqLayer0.occupancy 7196500 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer1.occupancy 35870000 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
-
----------- End Simulation Statistics ----------