diff options
Diffstat (limited to 'tests/long/se/30.eon')
| -rw-r--r-- | tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt | 598 | ||||
| -rw-r--r-- | tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt | 1256 | ||||
| -rw-r--r-- | tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt | 1216 |
3 files changed, 1772 insertions, 1298 deletions
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt index c1850cccb..1c69e7033 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.141181 # Number of seconds simulated -sim_ticks 141180939500 # Number of ticks simulated -final_tick 141180939500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.141149 # Number of seconds simulated +sim_ticks 141148809500 # Number of ticks simulated +final_tick 141148809500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 139974 # Simulator instruction rate (inst/s) -host_op_rate 139974 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 49569488 # Simulator tick rate (ticks/s) -host_mem_usage 218836 # Number of bytes of host memory used -host_seconds 2848.14 # Real time elapsed on the host +host_inst_rate 76319 # Simulator instruction rate (inst/s) +host_op_rate 76319 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 27020959 # Simulator tick rate (ticks/s) +host_mem_usage 222760 # Number of bytes of host memory used +host_seconds 5223.68 # Real time elapsed on the host sim_insts 398664595 # Number of instructions simulated sim_ops 398664595 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 214592 # Number of bytes read from this memory @@ -19,14 +19,172 @@ system.physmem.bytes_inst_read::total 214592 # Nu system.physmem.num_reads::cpu.inst 3353 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 3969 # Number of read requests responded to by this memory system.physmem.num_reads::total 7322 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1519979 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1799223 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3319202 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1519979 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1519979 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1519979 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1799223 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3319202 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1520325 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1799633 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3319957 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1520325 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1520325 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1520325 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1799633 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3319957 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7322 # Total number of read requests seen +system.physmem.writeReqs 0 # Total number of write requests seen +system.physmem.cpureqs 7322 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 468608 # Total number of bytes read from memory +system.physmem.bytesWritten 0 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 468608 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 465 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 464 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 518 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 520 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 382 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 397 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 457 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 443 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 405 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 457 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 588 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 397 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 529 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 418 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 395 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 487 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis +system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 141148757500 # Total gap between requests +system.physmem.readPktSize::0 0 # Categorize read packet sizes +system.physmem.readPktSize::1 0 # Categorize read packet sizes +system.physmem.readPktSize::2 0 # Categorize read packet sizes +system.physmem.readPktSize::3 0 # Categorize read packet sizes +system.physmem.readPktSize::4 0 # Categorize read packet sizes +system.physmem.readPktSize::5 0 # Categorize read packet sizes +system.physmem.readPktSize::6 7322 # Categorize read packet sizes +system.physmem.readPktSize::7 0 # Categorize read packet sizes +system.physmem.readPktSize::8 0 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # categorize write packet sizes +system.physmem.writePktSize::1 0 # categorize write packet sizes +system.physmem.writePktSize::2 0 # categorize write packet sizes +system.physmem.writePktSize::3 0 # categorize write packet sizes +system.physmem.writePktSize::4 0 # categorize write packet sizes +system.physmem.writePktSize::5 0 # categorize write packet sizes +system.physmem.writePktSize::6 0 # categorize write packet sizes +system.physmem.writePktSize::7 0 # categorize write packet sizes +system.physmem.writePktSize::8 0 # categorize write packet sizes +system.physmem.neitherpktsize::0 0 # categorize neither packet sizes +system.physmem.neitherpktsize::1 0 # categorize neither packet sizes +system.physmem.neitherpktsize::2 0 # categorize neither packet sizes +system.physmem.neitherpktsize::3 0 # categorize neither packet sizes +system.physmem.neitherpktsize::4 0 # categorize neither packet sizes +system.physmem.neitherpktsize::5 0 # categorize neither packet sizes +system.physmem.neitherpktsize::6 0 # categorize neither packet sizes +system.physmem.neitherpktsize::7 0 # categorize neither packet sizes +system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.rdQLenPdf::0 5336 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1506 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 331 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 124 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 25 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.totQLat 28738807 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 171664807 # Sum of mem lat for all requests +system.physmem.totBusLat 29288000 # Total cycles spent in databus access +system.physmem.totBankLat 113638000 # Total cycles spent in bank access +system.physmem.avgQLat 3924.99 # Average queueing delay per request +system.physmem.avgBankLat 15520.08 # Average bank access latency per request +system.physmem.avgBusLat 4000.00 # Average bus latency per request +system.physmem.avgMemAccLat 23445.07 # Average memory access latency +system.physmem.avgRdBW 3.32 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 3.32 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.02 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.00 # Average read queue length over time +system.physmem.avgWrQLen 0.00 # Average write queue length over time +system.physmem.readRowHits 6437 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate 87.91 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 19277350.11 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -35,18 +193,18 @@ system.cpu.dtb.read_hits 94755019 # DT system.cpu.dtb.read_misses 21 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations system.cpu.dtb.read_accesses 94755040 # DTB read accesses -system.cpu.dtb.write_hits 73522102 # DTB write hits +system.cpu.dtb.write_hits 73522092 # DTB write hits system.cpu.dtb.write_misses 35 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 73522137 # DTB write accesses -system.cpu.dtb.data_hits 168277121 # DTB hits +system.cpu.dtb.write_accesses 73522127 # DTB write accesses +system.cpu.dtb.data_hits 168277111 # DTB hits system.cpu.dtb.data_misses 56 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 168277177 # DTB accesses -system.cpu.itb.fetch_hits 49111833 # ITB hits +system.cpu.dtb.data_accesses 168277167 # DTB accesses +system.cpu.itb.fetch_hits 49111843 # ITB hits system.cpu.itb.fetch_misses 88782 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 49200615 # ITB accesses +system.cpu.itb.fetch_accesses 49200625 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -60,26 +218,26 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 282361880 # number of cpu cycles simulated +system.cpu.numCycles 282297620 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 53870354 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 30921657 # Number of conditional branches predicted +system.cpu.branch_predictor.lookups 53870359 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 30921660 # Number of conditional branches predicted system.cpu.branch_predictor.condIncorrect 16037209 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 33426941 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 15653987 # Number of BTB hits +system.cpu.branch_predictor.BTBLookups 33426943 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 15653988 # Number of BTB hits system.cpu.branch_predictor.usedRAS 8007516 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 18 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 46.830450 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 29683846 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 24186508 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 280818440 # Number of Reads from Int. Register File +system.cpu.branch_predictor.BTBHitPct 46.830451 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 29683847 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 24186512 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 280818433 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 159335859 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 440154299 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 440154292 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 119907695 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 100196481 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 220104176 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 100457653 # Number of Registers Read Through Forwarding Logic +system.cpu.regfile_manager.regForwards 100457659 # Number of Registers Read Through Forwarding Logic system.cpu.agen_unit.agens 168700458 # Number of Address Generations system.cpu.execution_unit.predictedTakenIncorrect 14475221 # Number of Branches Incorrectly Predicted As Taken. system.cpu.execution_unit.predictedNotTakenIncorrect 1561329 # Number of Branches Incorrectly Predicted As Not Taken). @@ -90,12 +248,12 @@ system.cpu.execution_unit.executions 205750873 # Nu system.cpu.mult_div_unit.multiplies 2124330 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 281927927 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 281928004 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 8028 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 13487383 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 268874497 # Number of cycles cpu stages are processed. -system.cpu.activity 95.223370 # Percentage of cycles cpu is active +system.cpu.timesIdled 8014 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 13423125 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 268874495 # Number of cycles cpu stages are processed. +system.cpu.activity 95.245045 # Percentage of cycles cpu is active system.cpu.comLoads 94754489 # Number of Load instructions committed system.cpu.comStores 73520729 # Number of Store instructions committed system.cpu.comBranches 44587532 # Number of Branches instructions committed @@ -107,78 +265,78 @@ system.cpu.committedInsts 398664595 # Nu system.cpu.committedOps 398664595 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 398664595 # Number of Instructions committed (Total) -system.cpu.cpi 0.708269 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.708108 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.708269 # CPI: Total CPI of All Threads -system.cpu.ipc 1.411892 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.708108 # CPI: Total CPI of All Threads +system.cpu.ipc 1.412214 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.411892 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 78547913 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 203813967 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 72.181828 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 108875170 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 173486710 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 61.441265 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 104652466 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 177709414 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 62.936758 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 183580459 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 98781421 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 34.983979 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 92669372 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 189692508 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 67.180636 # Percentage of cycles stage was utilized (processing insts). +system.cpu.ipc_total 1.412214 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 78483642 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 203813978 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 72.198263 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 108810922 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 173486698 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 61.455246 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 104588213 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 177709407 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 62.951082 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 183516209 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 98781411 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 34.991939 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 92605054 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 189692566 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 67.195949 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 1974 # number of replacements -system.cpu.icache.tagsinuse 1829.872355 # Cycle average of tags in use -system.cpu.icache.total_refs 49107443 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1830.000422 # Cycle average of tags in use +system.cpu.icache.total_refs 49107453 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 3901 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 12588.424250 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 12588.426814 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1829.872355 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.893492 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.893492 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 49107443 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 49107443 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 49107443 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 49107443 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 49107443 # number of overall hits -system.cpu.icache.overall_hits::total 49107443 # number of overall hits +system.cpu.icache.occ_blocks::cpu.inst 1830.000422 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.893555 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.893555 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 49107453 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 49107453 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 49107453 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 49107453 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 49107453 # number of overall hits +system.cpu.icache.overall_hits::total 49107453 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 4389 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 4389 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 4389 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 4389 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 4389 # number of overall misses system.cpu.icache.overall_misses::total 4389 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 215239500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 215239500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 215239500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 215239500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 215239500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 215239500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 49111832 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 49111832 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 49111832 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 49111832 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 49111832 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 49111832 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 191814500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 191814500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 191814500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 191814500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 191814500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 191814500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 49111842 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 49111842 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 49111842 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 49111842 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 49111842 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 49111842 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000089 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000089 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000089 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000089 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000089 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000089 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49040.669856 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 49040.669856 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 49040.669856 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 49040.669856 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 49040.669856 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 49040.669856 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43703.463203 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 43703.463203 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 43703.463203 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 43703.463203 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 43703.463203 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 43703.463203 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 90 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 66 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 90 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 66 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_hits::cpu.inst 488 # number of ReadReq MSHR hits @@ -193,58 +351,58 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 3901 system.cpu.icache.demand_mshr_misses::total 3901 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 3901 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 3901 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 190519000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 190519000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 190519000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 190519000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 190519000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 190519000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 169767000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 169767000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 169767000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 169767000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 169767000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 169767000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000079 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000079 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000079 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48838.502948 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48838.502948 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48838.502948 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 48838.502948 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48838.502948 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 48838.502948 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 43518.841323 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 43518.841323 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 43518.841323 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 43518.841323 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 43518.841323 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 43518.841323 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 764 # number of replacements -system.cpu.dcache.tagsinuse 3284.744401 # Cycle average of tags in use -system.cpu.dcache.total_refs 168261808 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 3285.037423 # Cycle average of tags in use +system.cpu.dcache.total_refs 168261838 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 40525.483622 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 40525.490848 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3284.744401 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.801940 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.801940 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 94753261 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 94753261 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73508547 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73508547 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 168261808 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168261808 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168261808 # number of overall hits -system.cpu.dcache.overall_hits::total 168261808 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1228 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1228 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 12182 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 12182 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 13410 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 13410 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 13410 # number of overall misses -system.cpu.dcache.overall_misses::total 13410 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 65498000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 65498000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 641953000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 641953000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 707451000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 707451000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 707451000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 707451000 # number of overall miss cycles +system.cpu.dcache.occ_blocks::cpu.data 3285.037423 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.802011 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.802011 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 94753259 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 94753259 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 73508579 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73508579 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 168261838 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168261838 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168261838 # number of overall hits +system.cpu.dcache.overall_hits::total 168261838 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1230 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1230 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 12150 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 12150 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 13380 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 13380 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 13380 # number of overall misses +system.cpu.dcache.overall_misses::total 13380 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 62962000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 62962000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 525724500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 525724500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 588686500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 588686500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 588686500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 588686500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 94754489 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 94754489 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) @@ -255,38 +413,38 @@ system.cpu.dcache.overall_accesses::cpu.data 168275218 system.cpu.dcache.overall_accesses::total 168275218 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000013 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000013 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000166 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000166 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000165 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000165 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000080 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000080 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000080 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000080 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53337.133550 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 53337.133550 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52696.847808 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 52696.847808 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 52755.480984 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 52755.480984 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 52755.480984 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 52755.480984 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51188.617886 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 51188.617886 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43269.506173 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 43269.506173 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 43997.496263 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 43997.496263 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 43997.496263 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 43997.496263 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 171928 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 132949 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 1907 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 1897 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 90.156266 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 70.083817 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 649 # number of writebacks system.cpu.dcache.writebacks::total 649 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 278 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 278 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 8980 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 8980 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 9258 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 9258 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 9258 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 9258 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 280 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 280 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 8948 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 8948 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 9228 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 9228 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 9228 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 9228 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 950 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 950 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3202 # number of WriteReq MSHR misses @@ -295,14 +453,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4152 system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 48495500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 48495500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 175965000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 175965000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 224460500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 224460500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 224460500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 224460500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 47641000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 47641000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 148441000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 148441000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 196082000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 196082000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 196082000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 196082000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses @@ -311,28 +469,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51047.894737 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51047.894737 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54954.715803 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54954.715803 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 54060.814066 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 54060.814066 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54060.814066 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 54060.814066 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 50148.421053 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 50148.421053 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46358.838226 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46358.838226 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 47225.915222 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 47225.915222 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 47225.915222 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 47225.915222 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 3900.293758 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 3900.679461 # Cycle average of tags in use system.cpu.l2cache.total_refs 754 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 4711 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.160051 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 370.502388 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2902.254610 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 627.536760 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.011307 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.088570 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.019151 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.119028 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 370.560631 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2902.521753 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 627.597077 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.011309 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.088578 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.019153 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.119039 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 548 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 123 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 671 # number of ReadReq hits @@ -357,17 +515,17 @@ system.cpu.l2cache.demand_misses::total 7322 # nu system.cpu.l2cache.overall_misses::cpu.inst 3353 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 3969 # number of overall misses system.cpu.l2cache.overall_misses::total 7322 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 181079500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 46077000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 227156500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 172190500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 172190500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 181079500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 218267500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 399347000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 181079500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 218267500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 399347000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 160328500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 45215500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 205544000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 144675500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 144675500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 160328500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 189891000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 350219500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 160328500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 189891000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 350219500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 3901 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 947 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 4848 # number of ReadReq accesses(hits+misses) @@ -392,17 +550,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.909226 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.859523 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.955925 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.909226 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 54005.219207 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55918.689320 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 54382.690927 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 54750.556439 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 54750.556439 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 54005.219207 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54993.071303 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 54540.699262 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 54005.219207 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54993.071303 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 54540.699262 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47816.433045 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54873.179612 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 49208.522863 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 46001.748808 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 46001.748808 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47816.433045 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 47843.537415 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 47831.125376 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47816.433045 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 47843.537415 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 47831.125376 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -422,17 +580,17 @@ system.cpu.l2cache.demand_mshr_misses::total 7322 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3353 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 3969 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7322 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 140250000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 36053500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 176303500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 133849000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 133849000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 140250000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 169902500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 310152500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 140250000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 169902500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 310152500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 117992891 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 34864220 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 152857111 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 105232120 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 105232120 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 117992891 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 140096340 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 258089231 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 117992891 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 140096340 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 258089231 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.859523 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.870116 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.861592 # mshr miss rate for ReadReq accesses @@ -444,17 +602,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.909226 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.859523 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.909226 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41828.213540 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43754.247573 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42208.163754 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42559.300477 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42559.300477 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41828.213540 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42807.382212 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42358.986616 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41828.213540 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42807.382212 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42358.986616 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35190.244855 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42310.946602 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36594.951161 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33460.133545 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33460.133545 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35190.244855 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35297.641723 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 35248.460940 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35190.244855 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35297.641723 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 35248.460940 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt index f5e3faa91..bdc3bba7f 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -1,52 +1,210 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.080354 # Number of seconds simulated -sim_ticks 80354154000 # Number of ticks simulated -final_tick 80354154000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.080450 # Number of seconds simulated +sim_ticks 80450416000 # Number of ticks simulated +final_tick 80450416000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 221188 # Simulator instruction rate (inst/s) -host_op_rate 221188 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 47323038 # Simulator tick rate (ticks/s) -host_mem_usage 219864 # Number of bytes of host memory used -host_seconds 1697.99 # Real time elapsed on the host +host_inst_rate 142052 # Simulator instruction rate (inst/s) +host_op_rate 142052 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 30428395 # Simulator tick rate (ticks/s) +host_mem_usage 223780 # Number of bytes of host memory used +host_seconds 2643.93 # Real time elapsed on the host sim_insts 375574808 # Number of instructions simulated sim_ops 375574808 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 222976 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 255424 # Number of bytes read from this memory -system.physmem.bytes_read::total 478400 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 222976 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 222976 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3484 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3991 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7475 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2774916 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3178728 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 5953644 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2774916 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2774916 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2774916 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3178728 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 5953644 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 222592 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 255232 # Number of bytes read from this memory +system.physmem.bytes_read::total 477824 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 222592 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 222592 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3478 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3988 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7466 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2766822 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3172538 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 5939360 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2766822 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2766822 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2766822 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3172538 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 5939360 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7466 # Total number of read requests seen +system.physmem.writeReqs 0 # Total number of write requests seen +system.physmem.cpureqs 7466 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 477824 # Total number of bytes read from memory +system.physmem.bytesWritten 0 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 477824 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 484 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 483 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 533 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 529 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 384 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 401 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 463 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 447 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 405 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 456 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 591 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 408 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 548 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 429 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 401 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 504 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis +system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 80450362000 # Total gap between requests +system.physmem.readPktSize::0 0 # Categorize read packet sizes +system.physmem.readPktSize::1 0 # Categorize read packet sizes +system.physmem.readPktSize::2 0 # Categorize read packet sizes +system.physmem.readPktSize::3 0 # Categorize read packet sizes +system.physmem.readPktSize::4 0 # Categorize read packet sizes +system.physmem.readPktSize::5 0 # Categorize read packet sizes +system.physmem.readPktSize::6 7466 # Categorize read packet sizes +system.physmem.readPktSize::7 0 # Categorize read packet sizes +system.physmem.readPktSize::8 0 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # categorize write packet sizes +system.physmem.writePktSize::1 0 # categorize write packet sizes +system.physmem.writePktSize::2 0 # categorize write packet sizes +system.physmem.writePktSize::3 0 # categorize write packet sizes +system.physmem.writePktSize::4 0 # categorize write packet sizes +system.physmem.writePktSize::5 0 # categorize write packet sizes +system.physmem.writePktSize::6 0 # categorize write packet sizes +system.physmem.writePktSize::7 0 # categorize write packet sizes +system.physmem.writePktSize::8 0 # categorize write packet sizes +system.physmem.neitherpktsize::0 0 # categorize neither packet sizes +system.physmem.neitherpktsize::1 0 # categorize neither packet sizes +system.physmem.neitherpktsize::2 0 # categorize neither packet sizes +system.physmem.neitherpktsize::3 0 # categorize neither packet sizes +system.physmem.neitherpktsize::4 0 # categorize neither packet sizes +system.physmem.neitherpktsize::5 0 # categorize neither packet sizes +system.physmem.neitherpktsize::6 0 # categorize neither packet sizes +system.physmem.neitherpktsize::7 0 # categorize neither packet sizes +system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.rdQLenPdf::0 3927 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2012 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 826 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 326 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 202 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 113 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 42 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.totQLat 54925938 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 190713938 # Sum of mem lat for all requests +system.physmem.totBusLat 29864000 # Total cycles spent in databus access +system.physmem.totBankLat 105924000 # Total cycles spent in bank access +system.physmem.avgQLat 7356.81 # Average queueing delay per request +system.physmem.avgBankLat 14187.52 # Average bank access latency per request +system.physmem.avgBusLat 4000.00 # Average bus latency per request +system.physmem.avgMemAccLat 25544.33 # Average memory access latency +system.physmem.avgRdBW 5.94 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 5.94 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.04 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.00 # Average read queue length over time +system.physmem.avgWrQLen 0.00 # Average write queue length over time +system.physmem.readRowHits 6527 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate 87.42 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 10775564.16 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 103401614 # DTB read hits -system.cpu.dtb.read_misses 88552 # DTB read misses -system.cpu.dtb.read_acv 48603 # DTB read access violations -system.cpu.dtb.read_accesses 103490166 # DTB read accesses -system.cpu.dtb.write_hits 79056152 # DTB write hits -system.cpu.dtb.write_misses 1601 # DTB write misses +system.cpu.dtb.read_hits 103443494 # DTB read hits +system.cpu.dtb.read_misses 89204 # DTB read misses +system.cpu.dtb.read_acv 48604 # DTB read access violations +system.cpu.dtb.read_accesses 103532698 # DTB read accesses +system.cpu.dtb.write_hits 79020707 # DTB write hits +system.cpu.dtb.write_misses 1585 # DTB write misses system.cpu.dtb.write_acv 2 # DTB write access violations -system.cpu.dtb.write_accesses 79057753 # DTB write accesses -system.cpu.dtb.data_hits 182457766 # DTB hits -system.cpu.dtb.data_misses 90153 # DTB misses -system.cpu.dtb.data_acv 48605 # DTB access violations -system.cpu.dtb.data_accesses 182547919 # DTB accesses -system.cpu.itb.fetch_hits 52578444 # ITB hits +system.cpu.dtb.write_accesses 79022292 # DTB write accesses +system.cpu.dtb.data_hits 182464201 # DTB hits +system.cpu.dtb.data_misses 90789 # DTB misses +system.cpu.dtb.data_acv 48606 # DTB access violations +system.cpu.dtb.data_accesses 182554990 # DTB accesses +system.cpu.itb.fetch_hits 52635617 # ITB hits system.cpu.itb.fetch_misses 446 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 52578890 # ITB accesses +system.cpu.itb.fetch_accesses 52636063 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -60,245 +218,245 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 160708310 # number of cpu cycles simulated +system.cpu.numCycles 160900834 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 52055858 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 30270064 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1609565 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 28583053 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 24291253 # Number of BTB hits +system.cpu.BPredUnit.lookups 52082511 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 30304197 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1627462 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 28687866 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 24364965 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 9363483 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 1125 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 53630506 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 462761975 # Number of instructions fetch has processed -system.cpu.fetch.Branches 52055858 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 33654736 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 81569260 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 7805922 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 19227823 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 182 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 8640 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 52578444 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 632985 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 160593743 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.881569 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.314206 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 9358559 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 1149 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 53712913 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 462927523 # Number of instructions fetch has processed +system.cpu.fetch.Branches 52082511 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 33723524 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 81628321 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 7863564 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 19256748 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 186 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 8496 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 52635617 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 625198 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 160803654 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.878837 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.313069 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 79024483 49.21% 49.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4373999 2.72% 51.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 7277585 4.53% 56.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 5624285 3.50% 59.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 12451588 7.75% 67.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 8090347 5.04% 72.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5701462 3.55% 76.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1906860 1.19% 77.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 36143134 22.51% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 79175333 49.24% 49.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4378645 2.72% 51.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 7276914 4.53% 56.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 5654242 3.52% 60.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 12481747 7.76% 67.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 8090070 5.03% 72.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5699527 3.54% 76.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1919584 1.19% 77.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 36127592 22.47% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 160593743 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.323915 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.879515 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 59159628 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 14701180 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 76777373 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3802489 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 6153073 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 9767212 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 4329 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 457201252 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 12277 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 6153073 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 62463630 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4784250 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 400809 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 77384574 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 9407407 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 451419869 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 14 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 20713 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 7782416 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 295098377 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 593658097 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 314398187 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 279259910 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 160803654 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.323693 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.877098 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 59260573 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 14714376 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 76844391 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3791608 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 6192706 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 9758398 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 4357 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 457340975 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 12460 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 6192706 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 62581380 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4767420 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 396481 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 77424943 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 9440724 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 451604153 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 25 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 23405 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 7795110 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 295281147 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 593898440 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 314599798 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 279298642 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259532329 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 35566048 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 38393 # count of serializing insts renamed +system.cpu.rename.UndoneMaps 35748818 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 38358 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 348 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 27305396 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 107006158 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 81864884 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 8914753 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 6402170 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 416586090 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 336 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 407940469 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1092011 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 40751586 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 19838559 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 121 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 160593743 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.540202 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.007855 # Number of insts issued each cycle +system.cpu.rename.skidInsts 27322373 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 107078098 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 81809760 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 8914792 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 6385731 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 416755970 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 334 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 407971342 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1213804 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 40920126 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 20099668 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 119 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 160803654 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.537078 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.007577 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 32107491 19.99% 19.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 26532573 16.52% 36.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 26024058 16.20% 52.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 24782303 15.43% 68.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 21577160 13.44% 81.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15465247 9.63% 91.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8675795 5.40% 96.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 4109702 2.56% 99.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1319414 0.82% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 32260500 20.06% 20.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 26539337 16.50% 36.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 26078054 16.22% 52.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 24787830 15.41% 68.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 21571430 13.41% 81.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15523746 9.65% 91.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8624317 5.36% 96.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 4085465 2.54% 99.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1332975 0.83% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 160593743 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 160803654 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 35836 0.30% 0.30% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 36186 0.30% 0.30% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 0.30% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.30% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 73145 0.62% 0.92% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 5467 0.05% 0.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 3221 0.03% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 1851348 15.57% 16.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 1774625 14.92% 31.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 31.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 31.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 31.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 31.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 31.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 31.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 31.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 31.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 31.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 31.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 31.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 31.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 31.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 31.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 31.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 31.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 31.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 31.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 31.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 31.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 31.48% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 5106562 42.94% 74.43% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3040891 25.57% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 74788 0.63% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 4408 0.04% 0.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 3062 0.03% 1.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 1840642 15.50% 16.50% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 1784659 15.03% 31.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 31.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 31.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 31.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 31.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 31.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 31.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 31.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 31.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 31.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 31.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 31.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 31.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 31.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 31.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 31.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 31.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 31.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 31.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 31.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 31.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 31.53% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 5098486 42.94% 74.47% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3030945 25.53% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 158120657 38.76% 38.77% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2126534 0.52% 39.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 39.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 33463281 8.20% 47.49% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 7848056 1.92% 49.42% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2840409 0.70% 50.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 16567576 4.06% 54.17% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 1592675 0.39% 54.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.57% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 105294166 25.81% 80.38% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 80053534 19.62% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 158101841 38.75% 38.76% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2126541 0.52% 39.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 39.28% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 33488456 8.21% 47.49% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 7847707 1.92% 49.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2841085 0.70% 50.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 16565313 4.06% 54.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 1591977 0.39% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 105357579 25.82% 80.39% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 80017262 19.61% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 407940469 # Type of FU issued -system.cpu.iq.rate 2.538391 # Inst issue rate -system.cpu.iq.fu_busy_cnt 11891095 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.029149 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 648130283 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 270005016 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 237809508 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 341327504 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 187383841 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 162964934 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 245490516 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 174307467 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 14797790 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 407971342 # Type of FU issued +system.cpu.iq.rate 2.535545 # Inst issue rate +system.cpu.iq.fu_busy_cnt 11873176 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.029103 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 648496700 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 270371889 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 237775030 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 341336618 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 187355366 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 162947679 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 245502336 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 174308601 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 14799025 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 12251671 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 123751 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 50882 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 8344155 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 12323611 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 124858 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 50857 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 8289031 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 260839 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 3 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 260769 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 122 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 6153073 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2493888 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 367103 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 441513906 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 235069 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 107006158 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 81864884 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 336 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 120 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 76 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 50882 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1249323 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 568752 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1818075 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 403380721 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 103538845 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 4559748 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 6192706 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2493954 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 366810 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 441694516 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 229015 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 107078098 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 81809760 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 334 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 117 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 78 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 50857 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1275804 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 567133 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1842937 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 403387908 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 103581364 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 4583434 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 24927480 # number of nop insts executed -system.cpu.iew.exec_refs 182596628 # number of memory reference insts executed -system.cpu.iew.exec_branches 47226669 # Number of branches executed -system.cpu.iew.exec_stores 79057783 # Number of stores executed -system.cpu.iew.exec_rate 2.510018 # Inst execution rate -system.cpu.iew.wb_sent 401610425 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 400774442 # cumulative count of insts written-back -system.cpu.iew.wb_producers 195308199 # num instructions producing a value -system.cpu.iew.wb_consumers 273451305 # num instructions consuming a value +system.cpu.iew.exec_nop 24938212 # number of nop insts executed +system.cpu.iew.exec_refs 182603691 # number of memory reference insts executed +system.cpu.iew.exec_branches 47210628 # Number of branches executed +system.cpu.iew.exec_stores 79022327 # Number of stores executed +system.cpu.iew.exec_rate 2.507059 # Inst execution rate +system.cpu.iew.wb_sent 401574040 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 400722709 # cumulative count of insts written-back +system.cpu.iew.wb_producers 195201608 # num instructions producing a value +system.cpu.iew.wb_consumers 273256469 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.493800 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.714234 # average fanout of values written-back +system.cpu.iew.wb_rate 2.490495 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.714353 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 42890401 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 43076400 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1605306 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 154440670 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.581345 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.965853 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1623178 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 154610948 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.578502 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.964409 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 58870445 38.12% 38.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 23396206 15.15% 53.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13280012 8.60% 61.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11680215 7.56% 69.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 8466998 5.48% 74.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 5501467 3.56% 78.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 5150112 3.33% 81.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3370011 2.18% 83.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 24725204 16.01% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 58949463 38.13% 38.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 23452675 15.17% 53.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13321237 8.62% 61.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11705960 7.57% 69.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 8475693 5.48% 74.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 5493357 3.55% 78.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 5136307 3.32% 81.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3345893 2.16% 84.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 24730363 16.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 154440670 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 154610948 # Number of insts commited each cycle system.cpu.commit.committedInsts 398664583 # Number of instructions committed system.cpu.commit.committedOps 398664583 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -309,70 +467,70 @@ system.cpu.commit.branches 44587533 # Nu system.cpu.commit.fp_insts 155295106 # Number of committed floating point instructions. system.cpu.commit.int_insts 316365839 # Number of committed integer instructions. system.cpu.commit.function_calls 8007752 # Number of function calls committed. -system.cpu.commit.bw_lim_events 24725204 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 24730363 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 571267473 # The number of ROB reads -system.cpu.rob.rob_writes 889277309 # The number of ROB writes -system.cpu.timesIdled 3039 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 114567 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 571618591 # The number of ROB reads +system.cpu.rob.rob_writes 889688372 # The number of ROB writes +system.cpu.timesIdled 2869 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 97180 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 375574808 # Number of Instructions Simulated system.cpu.committedOps 375574808 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 375574808 # Number of Instructions Simulated -system.cpu.cpi 0.427900 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.427900 # CPI: Total CPI of All Threads -system.cpu.ipc 2.336997 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.336997 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 402957504 # number of integer regfile reads -system.cpu.int_regfile_writes 172619998 # number of integer regfile writes -system.cpu.fp_regfile_reads 158343155 # number of floating regfile reads -system.cpu.fp_regfile_writes 105226626 # number of floating regfile writes +system.cpu.cpi 0.428412 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.428412 # CPI: Total CPI of All Threads +system.cpu.ipc 2.334201 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.334201 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 402943078 # number of integer regfile reads +system.cpu.int_regfile_writes 172629700 # number of integer regfile writes +system.cpu.fp_regfile_reads 158343488 # number of floating regfile reads +system.cpu.fp_regfile_writes 105222580 # number of floating regfile writes system.cpu.misc_regfile_reads 350572 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 2218 # number of replacements -system.cpu.icache.tagsinuse 1836.523631 # Cycle average of tags in use -system.cpu.icache.total_refs 52573018 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 4149 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 12671.250422 # Average number of references to valid blocks. +system.cpu.icache.replacements 2200 # number of replacements +system.cpu.icache.tagsinuse 1838.464064 # Cycle average of tags in use +system.cpu.icache.total_refs 52630329 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 4132 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 12737.252904 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1836.523631 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.896740 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.896740 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 52573018 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 52573018 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 52573018 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 52573018 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 52573018 # number of overall hits -system.cpu.icache.overall_hits::total 52573018 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5426 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5426 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5426 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5426 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5426 # number of overall misses -system.cpu.icache.overall_misses::total 5426 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 168571000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 168571000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 168571000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 168571000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 168571000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 168571000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 52578444 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 52578444 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 52578444 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 52578444 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 52578444 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 52578444 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000103 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000103 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000103 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000103 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000103 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000103 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 31067.268706 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 31067.268706 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 31067.268706 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 31067.268706 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 31067.268706 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 31067.268706 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1838.464064 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.897688 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.897688 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 52630329 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 52630329 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 52630329 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 52630329 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 52630329 # number of overall hits +system.cpu.icache.overall_hits::total 52630329 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5288 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5288 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5288 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5288 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5288 # number of overall misses +system.cpu.icache.overall_misses::total 5288 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 146095500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 146095500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 146095500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 146095500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 146095500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 146095500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 52635617 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 52635617 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 52635617 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 52635617 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 52635617 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 52635617 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000100 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000100 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000100 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000100 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000100 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000100 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27627.742057 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 27627.742057 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 27627.742057 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 27627.742057 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 27627.742057 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 27627.742057 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -381,284 +539,284 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1277 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1277 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1277 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1277 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1277 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1277 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4149 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 4149 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 4149 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 4149 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 4149 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 4149 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 129086500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 129086500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 129086500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 129086500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 129086500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 129086500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1156 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1156 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1156 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1156 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1156 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1156 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4132 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 4132 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 4132 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 4132 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 4132 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 4132 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 115307000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 115307000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 115307000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 115307000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 115307000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 115307000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000079 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000079 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000079 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 31112.677754 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 31112.677754 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 31112.677754 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 31112.677754 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 31112.677754 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 31112.677754 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27905.856728 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27905.856728 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27905.856728 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 27905.856728 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27905.856728 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 27905.856728 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 788 # number of replacements -system.cpu.dcache.tagsinuse 3297.853996 # Cycle average of tags in use -system.cpu.dcache.total_refs 161841661 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 4190 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 38625.694749 # Average number of references to valid blocks. +system.cpu.dcache.replacements 781 # number of replacements +system.cpu.dcache.tagsinuse 3295.904807 # Cycle average of tags in use +system.cpu.dcache.total_refs 161883653 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 4181 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 38718.883760 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3297.853996 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.805140 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.805140 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 88341162 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 88341162 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73500481 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73500481 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 18 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 18 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 161841643 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 161841643 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 161841643 # number of overall hits -system.cpu.dcache.overall_hits::total 161841643 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1802 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1802 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 20248 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 20248 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 22050 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 22050 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 22050 # number of overall misses -system.cpu.dcache.overall_misses::total 22050 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 62316500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 62316500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 625415500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 625415500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 687732000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 687732000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 687732000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 687732000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 88342964 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 88342964 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::cpu.data 3295.904807 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.804664 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.804664 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 88381720 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 88381720 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 73501913 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73501913 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 20 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 20 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 161883633 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 161883633 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 161883633 # number of overall hits +system.cpu.dcache.overall_hits::total 161883633 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1838 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1838 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 18816 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 18816 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 20654 # 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number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 88383558 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 73520729 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 18 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 18 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 161863693 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 161863693 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 161863693 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 161863693 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000020 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000020 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000275 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000275 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000136 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000136 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000136 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000136 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34581.853496 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 34581.853496 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30887.766693 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 30887.766693 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31189.659864 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31189.659864 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31189.659864 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31189.659864 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 15 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 20 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 20 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 161904287 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 161904287 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 161904287 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 161904287 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000021 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000021 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000256 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000256 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000128 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000128 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000128 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000128 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34800.870511 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 34800.870511 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26759.194303 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 26759.194303 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 27474.823279 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 27474.823279 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 27474.823279 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 27474.823279 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 613 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 15 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 153.250000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 667 # number of writebacks -system.cpu.dcache.writebacks::total 667 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 813 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 813 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 17047 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 17047 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 17860 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 17860 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 17860 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 17860 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 989 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 989 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3201 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 3201 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4190 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4190 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4190 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4190 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 35672500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 35672500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 129053000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 129053000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 164725500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 164725500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 164725500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 164725500 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 659 # number of writebacks +system.cpu.dcache.writebacks::total 659 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 852 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 852 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 15621 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 15621 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 16473 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 16473 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 16473 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 16473 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 986 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 986 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3195 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 3195 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4181 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4181 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4181 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4181 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 35567000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 35567000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 111777000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 111777000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 147344000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 147344000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 147344000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 147344000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000011 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000044 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000043 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000026 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000026 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000026 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000026 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 36069.261881 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 36069.261881 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40316.463605 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40316.463605 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 39313.961814 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 39313.961814 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 39313.961814 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 39313.961814 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 36072.008114 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 36072.008114 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34984.976526 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34984.976526 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35241.329825 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 35241.329825 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35241.329825 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 35241.329825 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 4035.335685 # Cycle average of tags in use -system.cpu.l2cache.total_refs 887 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 4877 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.181874 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 4031.024226 # Cycle average of tags in use +system.cpu.l2cache.total_refs 872 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 4868 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.179129 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 371.767101 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 3005.985586 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 657.582998 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.011345 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.091735 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.020068 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.123149 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 665 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 130 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 795 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 667 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 667 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 69 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 69 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 665 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 199 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 864 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 665 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 199 # number of overall hits -system.cpu.l2cache.overall_hits::total 864 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3484 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 859 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 4343 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 3132 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 3132 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3484 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 3991 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 7475 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3484 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 3991 # number of overall misses -system.cpu.l2cache.overall_misses::total 7475 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 124255000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 34500500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 158755500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 125685500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 125685500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 124255000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 160186000 # 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average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 31770.557792 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 35810.305918 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 33928.408786 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 578 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 7 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 144.500000 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # 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number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 147757500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 260732500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.839720 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.868554 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.845271 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.978444 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.978444 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.839720 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.952506 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.896390 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.839720 # 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average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32426.808266 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37022.676021 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34880.602007 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3478 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 857 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 4335 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3131 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 3131 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3478 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 3988 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 7466 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3478 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 3988 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 7466 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 98162814 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 31479970 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 129642784 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 98128686 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 98128686 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 98162814 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 129608656 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 227771470 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 98162814 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 129608656 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 227771470 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.841723 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.869168 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.847011 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.979969 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.979969 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.841723 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.953839 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.898111 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.841723 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.953839 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.898111 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 28223.925819 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 36732.753792 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 29906.063206 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31341.004791 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31341.004791 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 28223.925819 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 32499.662989 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 30507.831503 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 28223.925819 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 32499.662989 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 30507.831503 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index 908860e43..843436b83 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -1,32 +1,190 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.070882 # Number of seconds simulated -sim_ticks 70882487500 # Number of ticks simulated -final_tick 70882487500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.071023 # Number of seconds simulated +sim_ticks 71023388000 # Number of ticks simulated +final_tick 71023388000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 146290 # Simulator instruction rate (inst/s) -host_op_rate 187023 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 37976354 # Simulator tick rate (ticks/s) -host_mem_usage 236976 # Number of bytes of host memory used -host_seconds 1866.49 # Real time elapsed on the host +host_inst_rate 129198 # Simulator instruction rate (inst/s) +host_op_rate 165172 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 33606101 # Simulator tick rate (ticks/s) +host_mem_usage 240544 # Number of bytes of host memory used +host_seconds 2113.41 # Real time elapsed on the host sim_insts 273048441 # Number of instructions simulated sim_ops 349076165 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 194880 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 272768 # Number of bytes read from this memory -system.physmem.bytes_read::total 467648 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 272832 # Number of bytes read from this memory +system.physmem.bytes_read::total 467712 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 194880 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 194880 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu.inst 3045 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 4262 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7307 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2749339 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3848172 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6597511 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2749339 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2749339 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2749339 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3848172 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6597511 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::cpu.data 4263 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7308 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2743885 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3841439 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6585324 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2743885 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2743885 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2743885 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3841439 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6585324 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7308 # Total number of read requests seen +system.physmem.writeReqs 0 # Total number of write requests seen +system.physmem.cpureqs 7308 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 467712 # Total number of bytes read from memory +system.physmem.bytesWritten 0 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 467712 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 345 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 467 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 513 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 578 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 475 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 461 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 441 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 510 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 480 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 494 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 484 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 551 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 363 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 415 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 369 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 362 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis +system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 71023232000 # Total gap between requests +system.physmem.readPktSize::0 0 # Categorize read packet sizes +system.physmem.readPktSize::1 0 # Categorize read packet sizes +system.physmem.readPktSize::2 0 # Categorize read packet sizes +system.physmem.readPktSize::3 0 # Categorize read packet sizes +system.physmem.readPktSize::4 0 # Categorize read packet sizes +system.physmem.readPktSize::5 0 # Categorize read packet sizes +system.physmem.readPktSize::6 7308 # Categorize read packet sizes +system.physmem.readPktSize::7 0 # Categorize read packet sizes +system.physmem.readPktSize::8 0 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # categorize write packet sizes +system.physmem.writePktSize::1 0 # categorize write packet sizes +system.physmem.writePktSize::2 0 # categorize write packet sizes +system.physmem.writePktSize::3 0 # categorize write packet sizes +system.physmem.writePktSize::4 0 # categorize write packet sizes +system.physmem.writePktSize::5 0 # categorize write packet sizes +system.physmem.writePktSize::6 0 # categorize write packet sizes +system.physmem.writePktSize::7 0 # categorize write packet sizes +system.physmem.writePktSize::8 0 # categorize write packet sizes +system.physmem.neitherpktsize::0 0 # categorize neither packet sizes +system.physmem.neitherpktsize::1 0 # categorize neither packet sizes +system.physmem.neitherpktsize::2 0 # categorize neither packet sizes +system.physmem.neitherpktsize::3 0 # categorize neither packet sizes +system.physmem.neitherpktsize::4 0 # categorize neither packet sizes +system.physmem.neitherpktsize::5 0 # categorize neither packet sizes +system.physmem.neitherpktsize::6 0 # categorize neither packet sizes +system.physmem.neitherpktsize::7 0 # categorize neither packet sizes +system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.rdQLenPdf::0 4207 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2152 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 666 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 201 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 75 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.totQLat 41389289 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 172709289 # Sum of mem lat for all requests +system.physmem.totBusLat 29232000 # Total cycles spent in databus access +system.physmem.totBankLat 102088000 # Total cycles spent in bank access +system.physmem.avgQLat 5663.56 # Average queueing delay per request +system.physmem.avgBankLat 13969.35 # Average bank access latency per request +system.physmem.avgBusLat 4000.00 # Average bus latency per request +system.physmem.avgMemAccLat 23632.91 # Average memory access latency +system.physmem.avgRdBW 6.59 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 6.59 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.04 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.00 # Average read queue length over time +system.physmem.avgWrQLen 0.00 # Average write queue length over time +system.physmem.readRowHits 6370 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate 87.16 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 9718559.39 # Average gap between requests system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -70,107 +228,107 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 141764976 # number of cpu cycles simulated +system.cpu.numCycles 142046777 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 43022632 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 21746290 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 2100537 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 27784307 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 17845610 # Number of BTB hits +system.cpu.BPredUnit.lookups 43162042 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 21862143 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 2121703 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 28877793 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 17918646 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 6965581 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 7462 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 40878725 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 328721134 # Number of instructions fetch has processed -system.cpu.fetch.Branches 43022632 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 24811191 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 73667201 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 8391169 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 20823021 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 27 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 3522 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 39401519 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 692730 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 141652682 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.982295 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.454701 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 6972885 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 7671 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 40968439 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 329355833 # Number of instructions fetch has processed +system.cpu.fetch.Branches 43162042 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 24891531 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 73809901 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 8464308 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 20842753 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 28 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 2971 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 39491995 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 707720 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 141956225 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.979912 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.453592 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 68666188 48.48% 48.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 7372946 5.20% 53.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 5824782 4.11% 57.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 6228810 4.40% 62.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4953654 3.50% 65.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4319066 3.05% 68.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3319868 2.34% 71.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 4326916 3.05% 74.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 36640452 25.87% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 68825893 48.48% 48.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 7402388 5.21% 53.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 5830184 4.11% 57.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 6288593 4.43% 62.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4967322 3.50% 65.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4323548 3.05% 68.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3311772 2.33% 71.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4321361 3.04% 74.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 36685164 25.84% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 141652682 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.303479 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.318775 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 47724056 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 16047440 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 69280897 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 2389978 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 6210311 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 7496443 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 70615 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 414536105 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 220570 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 6210311 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 53491207 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1558118 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 338571 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 65828585 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 14225890 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 403967880 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 63 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1665803 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 10197275 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 723 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 443295910 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2386846444 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1300310044 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1086536400 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 141956225 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.303858 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.318643 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 47854672 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 16043866 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 69433090 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 2362421 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 6262176 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 7513619 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 70716 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 415062954 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 220817 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 6262176 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 53639950 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1545689 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 333184 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 65936980 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 14238246 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 404539854 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 67 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1667551 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 10176735 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 553 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 443995291 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2389355526 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1302857658 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1086497868 # Number of floating rename lookups system.cpu.rename.CommittedMaps 384584946 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 58710964 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 14469 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 14467 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 35655672 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 105463248 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 93220202 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 4594940 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5698907 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 391915159 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 25548 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 378021086 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1395950 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 41892562 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 109796784 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1071 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 141652682 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.668648 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.042717 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 59410345 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 14542 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 14541 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 35671511 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 105577606 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 93228051 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 4593885 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5660351 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 392311117 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 25611 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 378254160 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1403521 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 42287591 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 111052876 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1134 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 141956225 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.664583 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.042822 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 28697410 20.26% 20.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 20492119 14.47% 34.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 20907256 14.76% 49.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 18207035 12.85% 62.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 24094157 17.01% 79.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15966233 11.27% 90.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 9051361 6.39% 97.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3319497 2.34% 99.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 917614 0.65% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 28896984 20.36% 20.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 20515288 14.45% 34.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 20937445 14.75% 49.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 18231025 12.84% 62.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 24110473 16.98% 79.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15997056 11.27% 90.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 9050570 6.38% 97.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3298757 2.32% 99.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 918627 0.65% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 141652682 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 141956225 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 8869 0.05% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 4699 0.03% 0.08% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9062 0.05% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 4694 0.03% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.08% # attempts to use FU when none available @@ -189,127 +347,127 @@ system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.08% # at system.cpu.iq.fu_full::SimdShift 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 45720 0.25% 0.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 45808 0.25% 0.33% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 7848 0.04% 0.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 429 0.00% 0.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 7711 0.04% 0.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 383 0.00% 0.38% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatDiv 3 0.00% 0.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 193652 1.08% 1.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 4980 0.03% 1.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 240582 1.34% 2.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.82% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9467921 52.63% 55.44% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 8015707 44.56% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 193806 1.08% 1.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 5491 0.03% 1.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 241038 1.34% 2.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.83% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9458380 52.63% 55.45% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 8006771 44.55% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 128195849 33.91% 33.91% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2174611 0.58% 34.49% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.49% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.49% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.49% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.49% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.49% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.49% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 34.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 6839706 1.81% 36.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 8692181 2.30% 38.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 3465000 0.92% 39.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1622054 0.43% 39.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 21343322 5.65% 45.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 7172329 1.90% 47.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 7135364 1.89% 49.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 49.42% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 102447083 27.10% 76.52% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 88758301 23.48% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 128369790 33.94% 33.94% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2174598 0.57% 34.51% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 34.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 6843583 1.81% 36.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 8689764 2.30% 38.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 3465929 0.92% 39.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1622822 0.43% 39.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 21343412 5.64% 45.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 7172666 1.90% 47.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 7136167 1.89% 49.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 175288 0.05% 49.44% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 102562726 27.11% 76.55% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 88697415 23.45% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 378021086 # Type of FU issued -system.cpu.iq.rate 2.666534 # Inst issue rate -system.cpu.iq.fu_busy_cnt 17990410 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.047591 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 665853263 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 301144367 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 252283124 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 251227951 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 132702727 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 118872712 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 266490153 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 129521343 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 10844694 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 378254160 # Type of FU issued +system.cpu.iq.rate 2.662884 # Inst issue rate +system.cpu.iq.fu_busy_cnt 17973147 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.047516 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 666559792 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 301879538 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 252435570 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 251281421 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 132758695 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 118859507 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 266684443 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 129542864 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 10845590 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 10812156 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 121101 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14360 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 10842267 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 10926514 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 120350 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14368 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 10850116 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 29815 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 119 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 27154 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 78 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 6210311 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 59816 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 7651 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 391949728 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1062817 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 105463248 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 93220202 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 14378 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 211 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 349 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14360 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1675475 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 499111 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 2174586 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 373364048 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 101084784 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 4657038 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 6262176 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 55211 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 11686 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 392346402 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1078418 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 105577606 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 93228051 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 14439 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 194 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 331 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14368 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1702737 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 499287 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 2202024 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 373561232 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 101191974 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 4692928 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9021 # number of nop insts executed -system.cpu.iew.exec_refs 188503459 # number of memory reference insts executed -system.cpu.iew.exec_branches 38700482 # Number of branches executed -system.cpu.iew.exec_stores 87418675 # Number of stores executed -system.cpu.iew.exec_rate 2.633683 # Inst execution rate -system.cpu.iew.wb_sent 371949572 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 371155836 # cumulative count of insts written-back -system.cpu.iew.wb_producers 184798274 # num instructions producing a value -system.cpu.iew.wb_consumers 367725403 # num instructions consuming a value +system.cpu.iew.exec_nop 9674 # number of nop insts executed +system.cpu.iew.exec_refs 188550520 # number of memory reference insts executed +system.cpu.iew.exec_branches 38725245 # Number of branches executed +system.cpu.iew.exec_stores 87358546 # Number of stores executed +system.cpu.iew.exec_rate 2.629847 # Inst execution rate +system.cpu.iew.wb_sent 372099364 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 371295077 # cumulative count of insts written-back +system.cpu.iew.wb_producers 184920977 # num instructions producing a value +system.cpu.iew.wb_consumers 367888043 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.618107 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.502544 # average fanout of values written-back +system.cpu.iew.wb_rate 2.613893 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.502656 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 42873018 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 43269770 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 24477 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 2030662 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 135442372 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.577309 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.655328 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 2051746 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 135694050 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.572528 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.654395 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 38119190 28.14% 28.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 29150867 21.52% 49.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13483643 9.96% 59.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11130935 8.22% 67.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 13797972 10.19% 78.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7276796 5.37% 83.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 3948237 2.92% 86.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3977327 2.94% 89.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 14557405 10.75% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 38297743 28.22% 28.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 29217550 21.53% 49.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13522381 9.97% 59.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11119570 8.19% 67.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 13774007 10.15% 78.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7289874 5.37% 83.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 3949510 2.91% 86.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3974023 2.93% 89.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 14549392 10.72% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 135442372 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 135694050 # Number of insts commited each cycle system.cpu.commit.committedInsts 273049053 # Number of instructions committed system.cpu.commit.committedOps 349076777 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -320,70 +478,70 @@ system.cpu.commit.branches 36549055 # Nu system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions. system.cpu.commit.int_insts 279593983 # Number of committed integer instructions. system.cpu.commit.function_calls 6225112 # Number of function calls committed. -system.cpu.commit.bw_lim_events 14557405 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 14549392 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 512832239 # The number of ROB reads -system.cpu.rob.rob_writes 790114412 # The number of ROB writes -system.cpu.timesIdled 3064 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 112294 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 513488682 # The number of ROB reads +system.cpu.rob.rob_writes 790959694 # The number of ROB writes +system.cpu.timesIdled 2717 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 90552 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 273048441 # Number of Instructions Simulated system.cpu.committedOps 349076165 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 273048441 # Number of Instructions Simulated -system.cpu.cpi 0.519194 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.519194 # CPI: Total CPI of All Threads -system.cpu.ipc 1.926064 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.926064 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1783379175 # number of integer regfile reads -system.cpu.int_regfile_writes 236079321 # number of integer regfile writes -system.cpu.fp_regfile_reads 189868959 # number of floating regfile reads -system.cpu.fp_regfile_writes 133650660 # number of floating regfile writes -system.cpu.misc_regfile_reads 990849298 # number of misc regfile reads +system.cpu.cpi 0.520226 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.520226 # CPI: Total CPI of All Threads +system.cpu.ipc 1.922243 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.922243 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1784209945 # number of integer regfile reads +system.cpu.int_regfile_writes 236299492 # number of integer regfile writes +system.cpu.fp_regfile_reads 189823111 # number of floating regfile reads +system.cpu.fp_regfile_writes 133661428 # number of floating regfile writes +system.cpu.misc_regfile_reads 991633784 # number of misc regfile reads system.cpu.misc_regfile_writes 34426469 # number of misc regfile writes -system.cpu.icache.replacements 13928 # number of replacements -system.cpu.icache.tagsinuse 1856.985526 # Cycle average of tags in use -system.cpu.icache.total_refs 39384906 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 15824 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 2488.934909 # Average number of references to valid blocks. +system.cpu.icache.replacements 13962 # number of replacements +system.cpu.icache.tagsinuse 1856.548325 # Cycle average of tags in use +system.cpu.icache.total_refs 39475406 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 15856 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 2489.619450 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1856.985526 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.906731 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.906731 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 39384906 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 39384906 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 39384906 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 39384906 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 39384906 # number of overall hits -system.cpu.icache.overall_hits::total 39384906 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 16613 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 16613 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 16613 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 16613 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 16613 # number of overall misses -system.cpu.icache.overall_misses::total 16613 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 188398500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 188398500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 188398500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 188398500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 188398500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 188398500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 39401519 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 39401519 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 39401519 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 39401519 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 39401519 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 39401519 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000422 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000422 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000422 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000422 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000422 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000422 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 11340.426172 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 11340.426172 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 11340.426172 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 11340.426172 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 11340.426172 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 11340.426172 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1856.548325 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.906518 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.906518 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 39475406 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 39475406 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 39475406 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 39475406 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 39475406 # number of overall hits +system.cpu.icache.overall_hits::total 39475406 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 16589 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 16589 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 16589 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 16589 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 16589 # number of overall misses +system.cpu.icache.overall_misses::total 16589 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 174124000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 174124000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 174124000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 174124000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 174124000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 174124000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 39491995 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 39491995 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 39491995 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 39491995 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 39491995 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 39491995 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000420 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000420 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000420 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000420 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000420 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000420 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10496.353005 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 10496.353005 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 10496.353005 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 10496.353005 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 10496.353005 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 10496.353005 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -392,146 +550,146 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 789 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 789 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 789 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 789 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 789 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 789 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15824 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 15824 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 15824 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 15824 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 15824 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 15824 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 136475000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 136475000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 136475000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 136475000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 136475000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 136475000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000402 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000402 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000402 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000402 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000402 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000402 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8624.557634 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 8624.557634 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8624.557634 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 8624.557634 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8624.557634 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 8624.557634 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 733 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 733 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 733 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 733 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 733 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 733 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15856 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 15856 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 15856 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 15856 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 15856 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 15856 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 125938500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 125938500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 125938500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 125938500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 125938500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 125938500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000401 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000401 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000401 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000401 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000401 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000401 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7942.640010 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7942.640010 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7942.640010 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 7942.640010 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7942.640010 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 7942.640010 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1417 # number of replacements -system.cpu.dcache.tagsinuse 3115.188705 # Cycle average of tags in use -system.cpu.dcache.total_refs 172067508 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 4618 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 37260.179298 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1428 # number of replacements +system.cpu.dcache.tagsinuse 3114.448538 # Cycle average of tags in use +system.cpu.dcache.total_refs 172176390 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 4628 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 37203.195765 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3115.188705 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.760544 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.760544 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 90009194 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 90009194 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 82031517 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 82031517 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 13545 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 13545 # number of LoadLockedReq hits +system.cpu.dcache.occ_blocks::cpu.data 3114.448538 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.760363 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.760363 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 90117753 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 90117753 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 82031823 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 82031823 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 13562 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 13562 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 13252 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 13252 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 172040711 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 172040711 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 172040711 # number of overall hits -system.cpu.dcache.overall_hits::total 172040711 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 3936 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 3936 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 21143 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 21143 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 172149576 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 172149576 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 172149576 # number of overall hits +system.cpu.dcache.overall_hits::total 172149576 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 3920 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 3920 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 20837 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 20837 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 25079 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 25079 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 25079 # number of overall misses -system.cpu.dcache.overall_misses::total 25079 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 123444000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 123444000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 700240500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 700240500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 74000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 74000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 823684500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 823684500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 823684500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 823684500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 90013130 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 90013130 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 24757 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 24757 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 24757 # number of overall misses +system.cpu.dcache.overall_misses::total 24757 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 107051000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 107051000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 536036000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 536036000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 83000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 83000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 643087000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 643087000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 643087000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 643087000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 90121673 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 90121673 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052660 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052660 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13547 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 13547 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13564 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 13564 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 13252 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 13252 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 172065790 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 172065790 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 172065790 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 172065790 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000044 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000044 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000258 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000258 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000148 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000148 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000146 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000146 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000146 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000146 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31362.804878 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 31362.804878 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33119.259329 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33119.259329 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 37000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 37000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 32843.594242 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 32843.594242 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 32843.594242 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 32843.594242 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 172174333 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 172174333 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 172174333 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 172174333 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000043 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000043 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000254 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000254 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000147 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000147 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000144 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000144 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000144 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000144 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27308.928571 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 27308.928571 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25725.200365 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 25725.200365 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 41500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 41500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 25975.966393 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 25975.966393 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 25975.966393 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 25975.966393 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 626 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 365 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 16 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 12 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 39.125000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 30.416667 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1041 # number of writebacks -system.cpu.dcache.writebacks::total 1041 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2130 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2130 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18331 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 18331 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 1045 # number of writebacks +system.cpu.dcache.writebacks::total 1045 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2105 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2105 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18024 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 18024 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 20461 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 20461 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 20461 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 20461 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1806 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1806 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2812 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2812 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4618 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4618 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4618 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4618 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 58649500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 58649500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 107455500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 107455500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 166105000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 166105000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 166105000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 166105000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_hits::cpu.data 20129 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 20129 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 20129 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 20129 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1815 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1815 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2813 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2813 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4628 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4628 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4628 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4628 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 50564500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 50564500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84395500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 84395500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 134960000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 134960000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 134960000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 134960000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000020 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000020 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000034 # mshr miss rate for WriteReq accesses @@ -540,98 +698,98 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32474.806202 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 32474.806202 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38213.193457 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38213.193457 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35969.034214 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 35969.034214 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35969.034214 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 35969.034214 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27859.228650 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27859.228650 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30001.955208 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30001.955208 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29161.624892 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 29161.624892 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29161.624892 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 29161.624892 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 3978.553859 # Cycle average of tags in use -system.cpu.l2cache.total_refs 13166 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 5424 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.427360 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 3987.642168 # Cycle average of tags in use +system.cpu.l2cache.total_refs 13211 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 5425 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 2.435207 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 368.225876 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2798.824975 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 811.503008 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.011237 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.085413 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.024765 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.121416 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 12759 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 297 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 13056 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1041 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1041 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 17 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 17 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 12759 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 314 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 13073 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 12759 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 314 # number of overall hits -system.cpu.l2cache.overall_hits::total 13073 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3064 # number of ReadReq misses +system.cpu.l2cache.occ_blocks::writebacks 370.156310 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2800.588114 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 816.897744 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.011296 # 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average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 30819.551935 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -640,59 +798,59 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 19 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 42 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 61 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 19 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 42 # 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average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 34246.959943 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 34246.959943 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32086.371100 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34315.227593 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33386.410292 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32086.371100 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34315.227593 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33386.410292 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_misses::cpu.data 4263 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 7308 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 85814425 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 42422648 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 128237073 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 72139117 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 72139117 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 85814425 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 114561765 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 200376190 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 85814425 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 114561765 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 200376190 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.192041 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.809813 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.255461 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992893 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992893 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.192041 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.921132 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.356766 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.192041 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.921132 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.356766 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 28182.077176 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 28878.589517 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 28408.744572 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 25819.297423 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 25819.297423 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 28182.077176 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 26873.508093 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 27418.745211 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 28182.077176 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 26873.508093 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 27418.745211 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |