diff options
Diffstat (limited to 'tests/long/se/30.eon')
18 files changed, 1494 insertions, 1504 deletions
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini index 673c743ff..fd38a6ce1 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini @@ -191,7 +191,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -cwd=build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/inorder-timing +cwd=build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/inorder-timing egid=100 env= errout=cerr diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout index 051061431..8d1e02107 100755 --- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout @@ -1,14 +1,14 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 11:50:11 -gem5 started Jun 4 2012 13:42:58 +gem5 compiled Jun 28 2012 22:05:18 +gem5 started Jun 28 2012 22:10:46 gem5 executing on zizzer -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/inorder-timing +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Eon, Version 1.1 info: Increasing stack size by one page. OO-style eon Time= 0.133333 -Exiting @ tick 141175129500 because target called exit() +Exiting @ tick 141174877500 because target called exit() diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt index 06e2fa444..63af08cbf 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,32 +1,32 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.141175 # Number of seconds simulated -sim_ticks 141175129500 # Number of ticks simulated -final_tick 141175129500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 141174877500 # Number of ticks simulated +final_tick 141174877500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 110841 # Simulator instruction rate (inst/s) -host_op_rate 110841 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 39251086 # Simulator tick rate (ticks/s) -host_mem_usage 221340 # Number of bytes of host memory used -host_seconds 3596.72 # Real time elapsed on the host +host_inst_rate 165783 # Simulator instruction rate (inst/s) +host_op_rate 165783 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 58706881 # Simulator tick rate (ticks/s) +host_mem_usage 225068 # Number of bytes of host memory used +host_seconds 2404.74 # Real time elapsed on the host sim_insts 398664595 # Number of instructions simulated sim_ops 398664595 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 214592 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 254400 # Number of bytes read from this memory -system.physmem.bytes_read::total 468992 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 254016 # Number of bytes read from this memory +system.physmem.bytes_read::total 468608 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 214592 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 214592 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu.inst 3353 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3975 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7328 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1520041 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1802017 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3322058 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1520041 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1520041 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1520041 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1802017 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3322058 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::cpu.data 3969 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7322 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1520044 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1799300 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3319344 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1520044 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1520044 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1520044 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1799300 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3319344 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -60,7 +60,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 282350260 # number of cpu cycles simulated +system.cpu.numCycles 282349756 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.lookups 53870351 # Number of BP lookups @@ -93,9 +93,9 @@ system.cpu.contextSwitches 1 # Nu system.cpu.threadCycles 281921224 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.timesIdled 6799 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 13475974 # Number of cycles cpu's stages were not processed +system.cpu.idleCycles 13475470 # Number of cycles cpu's stages were not processed system.cpu.runCycles 268874286 # Number of cycles cpu stages are processed. -system.cpu.activity 95.227214 # Percentage of cycles cpu is active +system.cpu.activity 95.227384 # Percentage of cycles cpu is active system.cpu.comLoads 94754489 # Number of Load instructions committed system.cpu.comStores 73520729 # Number of Store instructions committed system.cpu.comBranches 44587532 # Number of Branches instructions committed @@ -107,34 +107,34 @@ system.cpu.committedInsts 398664595 # Nu system.cpu.committedOps 398664595 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 398664595 # Number of Instructions committed (Total) -system.cpu.cpi 0.708240 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.708239 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.708240 # CPI: Total CPI of All Threads -system.cpu.ipc 1.411951 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.708239 # CPI: Total CPI of All Threads +system.cpu.ipc 1.411953 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.411951 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 78536322 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 1.411953 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 78535818 # Number of cycles 0 instructions are processed. system.cpu.stage0.runCycles 203813938 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 72.184788 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 108863639 # Number of cycles 0 instructions are processed. +system.cpu.stage0.utilization 72.184917 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 108863135 # Number of cycles 0 instructions are processed. system.cpu.stage1.runCycles 173486621 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 61.443762 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 104640873 # Number of cycles 0 instructions are processed. +system.cpu.stage1.utilization 61.443871 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 104640369 # Number of cycles 0 instructions are processed. system.cpu.stage2.runCycles 177709387 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 62.939339 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 183568799 # Number of cycles 0 instructions are processed. +system.cpu.stage2.utilization 62.939451 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 183568295 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 98781461 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 34.985433 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 92657665 # Number of cycles 0 instructions are processed. +system.cpu.stage3.utilization 34.985495 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 92657161 # Number of cycles 0 instructions are processed. system.cpu.stage4.runCycles 189692595 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 67.183432 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.utilization 67.183552 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 1974 # number of replacements -system.cpu.icache.tagsinuse 1829.918694 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1829.918683 # Cycle average of tags in use system.cpu.icache.total_refs 49107469 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 3901 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 12588.430915 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1829.918694 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 1829.918683 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.893515 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.893515 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 49107469 # number of ReadReq hits @@ -213,12 +213,12 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47480.645988 system.cpu.icache.overall_avg_mshr_miss_latency::total 47480.645988 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 764 # number of replacements -system.cpu.dcache.tagsinuse 3284.843893 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 3284.843876 # Cycle average of tags in use system.cpu.dcache.total_refs 168261959 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 40525.519990 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3284.843893 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 3284.843876 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.801964 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.801964 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 94753265 # number of ReadReq hits @@ -237,14 +237,14 @@ system.cpu.dcache.demand_misses::cpu.data 13259 # n system.cpu.dcache.demand_misses::total 13259 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 13259 # number of overall misses system.cpu.dcache.overall_misses::total 13259 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 63819000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 63819000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 63567000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 63567000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 626556000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 626556000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 690375000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 690375000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 690375000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 690375000 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 690123000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 690123000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 690123000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 690123000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 94754489 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 94754489 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) @@ -261,14 +261,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000079 system.cpu.dcache.demand_miss_rate::total 0.000079 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000079 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000079 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 52139.705882 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 52139.705882 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51933.823529 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 51933.823529 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52061.154965 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 52061.154965 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 52068.406365 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 52068.406365 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 52068.406365 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 52068.406365 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 52049.400407 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 52049.400407 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 52049.400407 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 52049.400407 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 82410500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -295,14 +295,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4152 system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 46180000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 46180000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 45925000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 45925000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 169537000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 169537000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 215717000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 215717000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 215717000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 215717000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 215462000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 215462000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 215462000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 215462000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses @@ -311,63 +311,63 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48610.526316 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48610.526316 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48342.105263 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48342.105263 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52947.220487 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52947.220487 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51954.961464 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 51954.961464 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51954.961464 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 51954.961464 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51893.545279 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 51893.545279 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51893.545279 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 51893.545279 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 13 # number of replacements -system.cpu.l2cache.tagsinuse 3896.685167 # Cycle average of tags in use -system.cpu.l2cache.total_refs 736 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 4717 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.156031 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.tagsinuse 3900.421280 # Cycle average of tags in use +system.cpu.l2cache.total_refs 754 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 4711 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.160051 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 370.518693 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2902.345937 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 623.820537 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 370.518684 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2902.345910 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 627.556686 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.011307 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.088573 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.019037 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.118917 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.019152 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.119031 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 548 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 117 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 665 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 123 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 671 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 649 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 649 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 60 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 60 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.inst 548 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 177 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 725 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 183 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 731 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 548 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 177 # number of overall hits -system.cpu.l2cache.overall_hits::total 725 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 183 # number of overall hits +system.cpu.l2cache.overall_hits::total 731 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 3353 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 830 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 4183 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 824 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 4177 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 3145 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 3145 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 3353 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 3975 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 7328 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 3969 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 7322 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 3353 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 3975 # number of overall misses -system.cpu.l2cache.overall_misses::total 7328 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 3969 # number of overall misses +system.cpu.l2cache.overall_misses::total 7322 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 175438000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 43622500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 219060500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 43307500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 218745500 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 164970500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 164970500 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 175438000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 208593000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 384031000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 208278000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 383716000 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 175438000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 208593000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 384031000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 208278000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 383716000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 3901 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 947 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 4848 # number of ReadReq accesses(hits+misses) @@ -382,27 +382,27 @@ system.cpu.l2cache.overall_accesses::cpu.inst 3901 system.cpu.l2cache.overall_accesses::cpu.data 4152 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 8053 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.859523 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.876452 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.862830 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.870116 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.861592 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.981279 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.981279 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.859523 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.957370 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.909971 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.955925 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.909226 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.859523 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.957370 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.909971 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.955925 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.909226 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52322.696093 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52557.228916 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52369.232608 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52557.645631 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52369.044769 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52454.848967 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52454.848967 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52322.696093 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52476.226415 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52405.977074 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52476.190476 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52405.900027 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52322.696093 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52476.226415 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52405.977074 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52476.190476 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52405.900027 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -412,49 +412,49 @@ system.cpu.l2cache.avg_blocked_cycles::no_targets nan system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3353 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 830 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 4183 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 824 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 4177 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3145 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 3145 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 3353 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 3975 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 7328 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 3969 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 7322 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 3353 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 3975 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 7328 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 3969 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 7322 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 134591000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 33517500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 168108500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 33277500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 167868500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 126757500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 126757500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 134591000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 160275000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 294866000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 160035000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 294626000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 134591000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 160275000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 294866000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 160035000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 294626000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.859523 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.876452 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.862830 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.870116 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.861592 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.981279 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.981279 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.859523 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.957370 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.909971 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.909226 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.859523 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.957370 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.909971 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.909226 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40140.471220 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40382.530120 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40188.501076 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40385.315534 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40188.771846 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40304.451510 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40304.451510 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40140.471220 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40320.754717 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40238.264192 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40321.239607 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40238.459437 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40140.471220 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40320.754717 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40238.264192 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40321.239607 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40238.459437 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini index 7162e6c66..11313b921 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini @@ -489,7 +489,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -cwd=build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing +cwd=build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/o3-timing egid=100 env= errout=cerr diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout index 0c5d1935a..0f3bb3f65 100755 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout @@ -1,14 +1,14 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 11:50:11 -gem5 started Jun 4 2012 13:46:44 +gem5 compiled Jun 28 2012 22:05:18 +gem5 started Jun 28 2012 22:10:52 gem5 executing on zizzer -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Eon, Version 1.1 info: Increasing stack size by one page. OO-style eon Time= 0.066667 -Exiting @ tick 80257421500 because target called exit() +Exiting @ tick 80278875500 because target called exit() diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt index 55fb5b70f..c7cbab894 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -1,52 +1,52 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.080257 # Number of seconds simulated -sim_ticks 80257421500 # Number of ticks simulated -final_tick 80257421500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.080279 # Number of seconds simulated +sim_ticks 80278875500 # Number of ticks simulated +final_tick 80278875500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 183656 # Simulator instruction rate (inst/s) -host_op_rate 183656 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 39245952 # Simulator tick rate (ticks/s) -host_mem_usage 222148 # Number of bytes of host memory used -host_seconds 2044.99 # Real time elapsed on the host +host_inst_rate 279986 # Simulator instruction rate (inst/s) +host_op_rate 279986 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 59846889 # Simulator tick rate (ticks/s) +host_mem_usage 226092 # Number of bytes of host memory used +host_seconds 1341.40 # Real time elapsed on the host sim_insts 375574808 # Number of instructions simulated sim_ops 375574808 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 222720 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 255808 # Number of bytes read from this memory -system.physmem.bytes_read::total 478528 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 222720 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 222720 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3480 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3997 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7477 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2775070 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3187344 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 5962414 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2775070 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2775070 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2775070 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3187344 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 5962414 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 222592 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 255296 # Number of bytes read from this memory +system.physmem.bytes_read::total 477888 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 222592 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 222592 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3478 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3989 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7467 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2772734 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3180114 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 5952849 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2772734 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2772734 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2772734 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3180114 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 5952849 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 103368572 # DTB read hits -system.cpu.dtb.read_misses 88956 # DTB read misses +system.cpu.dtb.read_hits 103395556 # DTB read hits +system.cpu.dtb.read_misses 88623 # DTB read misses system.cpu.dtb.read_acv 48603 # DTB read access violations -system.cpu.dtb.read_accesses 103457528 # DTB read accesses -system.cpu.dtb.write_hits 78975243 # DTB write hits -system.cpu.dtb.write_misses 1664 # DTB write misses -system.cpu.dtb.write_acv 3 # DTB write access violations -system.cpu.dtb.write_accesses 78976907 # DTB write accesses -system.cpu.dtb.data_hits 182343815 # DTB hits -system.cpu.dtb.data_misses 90620 # DTB misses -system.cpu.dtb.data_acv 48606 # DTB access violations -system.cpu.dtb.data_accesses 182434435 # DTB accesses -system.cpu.itb.fetch_hits 52487109 # ITB hits -system.cpu.itb.fetch_misses 461 # ITB misses +system.cpu.dtb.read_accesses 103484179 # DTB read accesses +system.cpu.dtb.write_hits 78997481 # DTB write hits +system.cpu.dtb.write_misses 1612 # DTB write misses +system.cpu.dtb.write_acv 4 # DTB write access violations +system.cpu.dtb.write_accesses 78999093 # DTB write accesses +system.cpu.dtb.data_hits 182393037 # DTB hits +system.cpu.dtb.data_misses 90235 # DTB misses +system.cpu.dtb.data_acv 48607 # DTB access violations +system.cpu.dtb.data_accesses 182483272 # DTB accesses +system.cpu.itb.fetch_hits 52516361 # ITB hits +system.cpu.itb.fetch_misses 462 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 52487570 # ITB accesses +system.cpu.itb.fetch_accesses 52516823 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -60,112 +60,112 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 160514845 # number of cpu cycles simulated +system.cpu.numCycles 160557753 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 52017212 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 30261257 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1593315 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 28494887 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 24272738 # Number of BTB hits +system.cpu.BPredUnit.lookups 52050833 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 30287644 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1599078 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 29208422 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 24276895 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 9355488 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 4145 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 53524792 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 462212886 # Number of instructions fetch has processed -system.cpu.fetch.Branches 52017212 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 33628226 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 81457148 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 7754706 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 19283001 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 185 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 7777 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 52487109 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 628108 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 160395311 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.881711 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.314748 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 9365187 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 1064 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 53558689 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 462299559 # Number of instructions fetch has processed +system.cpu.fetch.Branches 52050833 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 33642082 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 81488062 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 7763373 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 19255908 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 182 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 8203 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 52516361 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 627395 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 160436815 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.881505 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.314292 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 78938163 49.21% 49.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4375676 2.73% 51.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 7263628 4.53% 56.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 5613511 3.50% 59.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 12408314 7.74% 67.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 8080182 5.04% 72.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5692573 3.55% 76.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1906295 1.19% 77.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 36116969 22.52% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 78948753 49.21% 49.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4374209 2.73% 51.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 7277181 4.54% 56.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 5613096 3.50% 59.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 12419261 7.74% 67.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 8092340 5.04% 72.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5700245 3.55% 76.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1902354 1.19% 77.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 36109376 22.51% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 160395311 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.324065 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.879565 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 59060129 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 14738019 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 76660368 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3818816 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 6117979 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 9735972 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 4512 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 456714619 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 12671 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 6117979 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 62341788 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4786215 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 392111 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 77312738 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 9444480 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 451064099 # Number of instructions processed by rename +system.cpu.fetch.rateDist::total 160436815 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.324188 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.879335 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 59087459 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 14718957 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 76680946 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3827925 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 6121528 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 9736129 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 4314 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 456834278 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 12214 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 6121528 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 62371527 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4787903 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 394179 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 77332259 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 9429419 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 451139499 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 10 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 26210 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 7820126 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 294805500 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 593185508 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 313931497 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 279254011 # Number of floating rename lookups +system.cpu.rename.IQFullEvents 22898 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 7804449 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 294872724 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 593300368 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 314087845 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 279212523 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259532329 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 35273171 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 38670 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 424 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 27284397 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 106956708 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 81779793 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 8927292 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 6395845 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 416292628 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 359 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 407676624 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1078526 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 40464590 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 19834312 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 144 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 160395311 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.541699 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.006909 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 35340395 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 38267 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 351 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 27285549 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 106973750 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 81779740 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 8912420 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 6388901 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 416336746 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 335 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 407746724 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1079648 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 40502587 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 19766308 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 120 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 160436815 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.541479 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.007779 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 31984575 19.94% 19.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 26488225 16.51% 36.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 26058764 16.25% 52.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 24758572 15.44% 68.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 21531957 13.42% 81.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15472386 9.65% 91.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8703569 5.43% 96.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 4094121 2.55% 99.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1303142 0.81% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 32040952 19.97% 19.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 26498917 16.52% 36.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 25974021 16.19% 52.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 24801870 15.46% 68.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 21558468 13.44% 81.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15451278 9.63% 91.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8686999 5.41% 96.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 4112581 2.56% 99.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1311729 0.82% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 160395311 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 160436815 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 35479 0.30% 0.30% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 35223 0.30% 0.30% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 0.30% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.30% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 74583 0.63% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 5020 0.04% 0.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 3238 0.03% 1.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 1852472 15.62% 16.62% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 1780365 15.01% 31.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 74176 0.62% 0.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 4373 0.04% 0.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 3034 0.03% 0.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 1856115 15.64% 16.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 1782113 15.01% 31.63% # attempts to use FU when none available system.cpu.iq.fu_full::FloatSqrt 0 0.00% 31.63% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAdd 0 0.00% 31.63% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 31.63% # attempts to use FU when none available @@ -187,19 +187,19 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 31.63% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 31.63% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 31.63% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 31.63% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 5090382 42.92% 74.55% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3018331 25.45% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 5098643 42.95% 74.58% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3017744 25.42% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 157965890 38.75% 38.76% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2126519 0.52% 39.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 158007223 38.75% 38.76% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2126531 0.52% 39.28% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 39.28% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 33457651 8.21% 47.48% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 7841942 1.92% 49.41% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2840834 0.70% 50.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 16563363 4.06% 54.17% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 1591033 0.39% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 33463416 8.21% 47.49% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 7846184 1.92% 49.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2836368 0.70% 50.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 16562414 4.06% 54.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 1592681 0.39% 54.56% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.56% # Type of FU issued @@ -221,86 +221,86 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.56% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 105252822 25.82% 80.38% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 80002989 19.62% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 105279650 25.82% 80.38% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 79998676 19.62% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 407676624 # Type of FU issued -system.cpu.iq.rate 2.539806 # Inst issue rate -system.cpu.iq.fu_busy_cnt 11859870 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.029091 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 647408174 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 269506276 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 237627844 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 341278781 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 187302066 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 162920489 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 245219921 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 174282992 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 14797631 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 407746724 # Type of FU issued +system.cpu.iq.rate 2.539564 # Inst issue rate +system.cpu.iq.fu_busy_cnt 11871421 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.029115 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 647615644 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 269617595 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 237690414 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 341265688 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 187272317 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 162935841 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 245304560 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 174280004 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 14820631 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 12202221 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 124163 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 50788 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 8259064 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 12219263 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 125114 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 50286 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 8259011 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 260903 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 260829 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 6117979 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2500869 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 370633 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 441236152 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 174981 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 106956708 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 81779793 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 359 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 125 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 18 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 50788 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1245732 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 559417 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1805149 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 403162552 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 103506235 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 4514072 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 6121528 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2498871 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 366274 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 441262786 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 203691 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 106973750 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 81779740 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 335 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 126 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 17 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 50286 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1245920 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 565907 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1811827 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 403241961 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 103532839 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 4504763 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 24943165 # number of nop insts executed -system.cpu.iew.exec_refs 182483180 # number of memory reference insts executed -system.cpu.iew.exec_branches 47188511 # Number of branches executed -system.cpu.iew.exec_stores 78976945 # Number of stores executed -system.cpu.iew.exec_rate 2.511684 # Inst execution rate -system.cpu.iew.wb_sent 401387937 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 400548333 # cumulative count of insts written-back -system.cpu.iew.wb_producers 195210305 # num instructions producing a value -system.cpu.iew.wb_consumers 273275997 # num instructions consuming a value +system.cpu.iew.exec_nop 24925705 # number of nop insts executed +system.cpu.iew.exec_refs 182531964 # number of memory reference insts executed +system.cpu.iew.exec_branches 47208062 # Number of branches executed +system.cpu.iew.exec_stores 78999125 # Number of stores executed +system.cpu.iew.exec_rate 2.511507 # Inst execution rate +system.cpu.iew.wb_sent 401471936 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 400626255 # cumulative count of insts written-back +system.cpu.iew.wb_producers 195236823 # num instructions producing a value +system.cpu.iew.wb_consumers 273330928 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.495397 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.714334 # average fanout of values written-back +system.cpu.iew.wb_rate 2.495216 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.714287 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 398664583 # The number of committed instructions system.cpu.commit.commitCommittedOps 398664583 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 42606114 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 42637745 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1588886 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 154277332 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.584078 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.967872 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1594835 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 154315287 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.583442 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.967476 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 58795294 38.11% 38.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 23338616 15.13% 53.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13263185 8.60% 61.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11678899 7.57% 69.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 8438473 5.47% 74.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 5481478 3.55% 78.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 5137622 3.33% 81.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3374234 2.19% 83.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 24769531 16.06% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 58825621 38.12% 38.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 23339762 15.12% 53.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13270606 8.60% 61.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11657566 7.55% 69.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 8455456 5.48% 74.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 5496217 3.56% 78.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 5141868 3.33% 81.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3368734 2.18% 83.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 24759457 16.04% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 154277332 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 154315287 # Number of insts commited each cycle system.cpu.commit.committedInsts 398664583 # Number of instructions committed system.cpu.commit.committedOps 398664583 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -311,70 +311,70 @@ system.cpu.commit.branches 44587533 # Nu system.cpu.commit.fp_insts 155295106 # Number of committed floating point instructions. system.cpu.commit.int_insts 316365839 # Number of committed integer instructions. system.cpu.commit.function_calls 8007752 # Number of function calls committed. -system.cpu.commit.bw_lim_events 24769531 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 24759457 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 570775521 # The number of ROB reads -system.cpu.rob.rob_writes 888672842 # The number of ROB writes -system.cpu.timesIdled 2679 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 119534 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 570855181 # The number of ROB reads +system.cpu.rob.rob_writes 888739971 # The number of ROB writes +system.cpu.timesIdled 2694 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 120938 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 375574808 # Number of Instructions Simulated system.cpu.committedOps 375574808 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 375574808 # Number of Instructions Simulated -system.cpu.cpi 0.427384 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.427384 # CPI: Total CPI of All Threads -system.cpu.ipc 2.339814 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.339814 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 402674037 # number of integer regfile reads -system.cpu.int_regfile_writes 172514061 # number of integer regfile writes -system.cpu.fp_regfile_reads 158318736 # number of floating regfile reads -system.cpu.fp_regfile_writes 105208261 # number of floating regfile writes +system.cpu.cpi 0.427499 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.427499 # CPI: Total CPI of All Threads +system.cpu.ipc 2.339188 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.339188 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 402766119 # number of integer regfile reads +system.cpu.int_regfile_writes 172550874 # number of integer regfile writes +system.cpu.fp_regfile_reads 158333530 # number of floating regfile reads +system.cpu.fp_regfile_writes 105213831 # number of floating regfile writes system.cpu.misc_regfile_reads 350572 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 2234 # number of replacements -system.cpu.icache.tagsinuse 1837.389415 # Cycle average of tags in use -system.cpu.icache.total_refs 52481453 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 4164 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 12603.615034 # Average number of references to valid blocks. +system.cpu.icache.replacements 2221 # number of replacements +system.cpu.icache.tagsinuse 1836.833971 # Cycle average of tags in use +system.cpu.icache.total_refs 52510942 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 4151 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 12650.190797 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1837.389415 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.897163 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.897163 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 52481453 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 52481453 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 52481453 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 52481453 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 52481453 # number of overall hits -system.cpu.icache.overall_hits::total 52481453 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5656 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5656 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5656 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5656 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5656 # number of overall misses -system.cpu.icache.overall_misses::total 5656 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 175405000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 175405000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 175405000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 175405000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 175405000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 175405000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 52487109 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 52487109 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 52487109 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 52487109 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 52487109 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 52487109 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000108 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000108 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000108 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000108 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000108 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000108 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 31012.199434 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 31012.199434 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 31012.199434 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 31012.199434 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 31012.199434 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 31012.199434 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1836.833971 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.896892 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.896892 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 52510942 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 52510942 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 52510942 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 52510942 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 52510942 # number of overall hits +system.cpu.icache.overall_hits::total 52510942 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5419 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5419 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5419 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5419 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5419 # number of overall misses +system.cpu.icache.overall_misses::total 5419 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 170335500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 170335500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 170335500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 170335500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 170335500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 170335500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 52516361 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 52516361 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 52516361 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 52516361 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 52516361 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 52516361 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000103 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000103 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000103 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000103 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000103 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000103 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 31433.013471 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 31433.013471 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 31433.013471 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 31433.013471 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 31433.013471 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 31433.013471 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -383,82 +383,82 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1492 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1492 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1492 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1492 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1492 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1492 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4164 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 4164 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 4164 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 4164 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 4164 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 4164 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 125153000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 125153000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 125153000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 125153000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 125153000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 125153000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1268 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1268 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1268 # 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number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 125070500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 125070500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 125070500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000079 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000079 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000079 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 30055.955812 # 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average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 30130.209588 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 804 # number of replacements -system.cpu.dcache.tagsinuse 3297.800145 # Cycle average of tags in use -system.cpu.dcache.total_refs 161809566 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 4205 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 38480.277289 # Average number of references to valid blocks. +system.cpu.dcache.replacements 783 # number of replacements +system.cpu.dcache.tagsinuse 3297.903545 # Cycle average of tags in use +system.cpu.dcache.total_refs 161813696 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 4184 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 38674.401530 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3297.800145 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.805127 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.805127 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 88308332 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 88308332 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73501218 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73501218 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 16 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 16 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 161809550 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 161809550 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 161809550 # 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number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 623249000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 623249000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 623249000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 623249000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 88310021 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 88310021 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::cpu.data 3297.903545 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.805152 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.805152 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 88312425 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 88312425 # 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number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 88314078 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 73520729 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 16 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 161830750 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 161830750 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 161830750 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 161830750 # number of overall (read+write) accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 18 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 18 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 161834807 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 161834807 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 161834807 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 161834807 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000019 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000019 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000265 # miss rate for WriteReq accesses @@ -467,148 +467,148 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000131 system.cpu.dcache.demand_miss_rate::total 0.000131 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000131 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000131 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33167.850799 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 33167.850799 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29072.241300 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 29072.241300 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 29398.537736 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 29398.537736 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 29398.537736 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 29398.537736 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 2500 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33398.971567 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 33398.971567 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29267.816800 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 29267.816800 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 29591.012353 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 29591.012353 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 29591.012353 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 29591.012353 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2500 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 682 # number of writebacks -system.cpu.dcache.writebacks::total 682 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 686 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 686 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16309 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16309 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 16995 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 16995 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 16995 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 16995 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1003 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1003 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3202 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 3202 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4205 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4205 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4205 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4205 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 31754500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 31754500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 113124000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 113124000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 144878500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 144878500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 144878500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 144878500 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 661 # number of writebacks +system.cpu.dcache.writebacks::total 661 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 664 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 664 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16281 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16281 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 16945 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 16945 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 16945 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 16945 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 989 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 989 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3195 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 3195 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4184 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4184 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4184 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4184 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 31319000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 31319000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 113198500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 113198500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 144517500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 144517500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 144517500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 144517500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000011 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000044 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000043 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000026 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000026 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000026 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000026 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31659.521436 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31659.521436 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35329.169269 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35329.169269 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34453.864447 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 34453.864447 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34453.864447 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 34453.864447 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31667.340748 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31667.340748 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35429.890454 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35429.890454 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34540.511472 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 34540.511472 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34540.511472 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 34540.511472 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 11 # number of replacements -system.cpu.l2cache.tagsinuse 4039.301940 # Cycle average of tags in use -system.cpu.l2cache.total_refs 903 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 4887 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.184776 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.tagsinuse 4030.550390 # Cycle average of tags in use +system.cpu.l2cache.total_refs 892 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 4871 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.183125 # 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number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 26958500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 135278500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 98537000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 98537000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 108320000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 125495500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 233815500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 108320000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 125495500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 233815500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.837870 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.867543 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.843580 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.979969 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.979969 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.837870 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.953394 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.895861 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.837870 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.953394 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.895861 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31144.335825 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31420.163170 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31198.916052 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31471.414883 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31471.414883 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31144.335825 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31460.391075 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31313.177983 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31144.335825 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31460.391075 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31313.177983 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini index b05b7d5ce..b7b2de2d4 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini @@ -158,7 +158,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -cwd=build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-timing +cwd=build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout index 39e268f04..535f9cae3 100755 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout @@ -1,14 +1,14 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 11:50:11 -gem5 started Jun 4 2012 13:47:31 +gem5 compiled Jun 28 2012 22:05:18 +gem5 started Jun 28 2012 22:12:10 gem5 executing on zizzer -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-timing +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Eon, Version 1.1 info: Increasing stack size by one page. OO-style eon Time= 0.566667 -Exiting @ tick 567343170000 because target called exit() +Exiting @ tick 567342918000 because target called exit() diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt index f16fecb77..049129481 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt @@ -1,32 +1,32 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.567343 # Number of seconds simulated -sim_ticks 567343170000 # Number of ticks simulated -final_tick 567343170000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 567342918000 # Number of ticks simulated +final_tick 567342918000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1377504 # Simulator instruction rate (inst/s) -host_op_rate 1377504 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1960338494 # Simulator tick rate (ticks/s) -host_mem_usage 220796 # Number of bytes of host memory used -host_seconds 289.41 # Real time elapsed on the host +host_inst_rate 2055836 # Simulator instruction rate (inst/s) +host_op_rate 2055836 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2925676505 # Simulator tick rate (ticks/s) +host_mem_usage 224040 # Number of bytes of host memory used +host_seconds 193.92 # Real time elapsed on the host sim_insts 398664609 # Number of instructions simulated sim_ops 398664609 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 205120 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 254400 # Number of bytes read from this memory -system.physmem.bytes_read::total 459520 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 254016 # Number of bytes read from this memory +system.physmem.bytes_read::total 459136 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 205120 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 205120 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu.inst 3205 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3975 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7180 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3969 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7174 # Number of read requests responded to by this memory system.physmem.bw_read::cpu.inst 361545 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 448406 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 809951 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 447729 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 809274 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 361545 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 361545 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_total::cpu.inst 361545 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 448406 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 809951 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 447729 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 809274 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -60,7 +60,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 1134686340 # number of cpu cycles simulated +system.cpu.numCycles 1134685836 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 398664609 # Number of instructions committed @@ -79,16 +79,16 @@ system.cpu.num_mem_refs 168275276 # nu system.cpu.num_load_insts 94754511 # Number of load instructions system.cpu.num_store_insts 73520765 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 1134686340 # Number of busy cycles +system.cpu.num_busy_cycles 1134685836 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 1769 # number of replacements -system.cpu.icache.tagsinuse 1795.131074 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1795.131072 # Cycle average of tags in use system.cpu.icache.total_refs 398660993 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 3673 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 108538.250204 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1795.131074 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 1795.131072 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.876529 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.876529 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 398660993 # number of ReadReq hits @@ -161,12 +161,12 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47648.516199 system.cpu.icache.overall_avg_mshr_miss_latency::total 47648.516199 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 764 # number of replacements -system.cpu.dcache.tagsinuse 3288.912598 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 3288.912595 # Cycle average of tags in use system.cpu.dcache.total_refs 168271068 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 40527.713873 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3288.912598 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 3288.912595 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.802957 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.802957 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 94753540 # number of ReadReq hits @@ -185,14 +185,14 @@ system.cpu.dcache.demand_misses::cpu.data 4152 # n system.cpu.dcache.demand_misses::total 4152 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 4152 # number of overall misses system.cpu.dcache.overall_misses::total 4152 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 48286000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 48286000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 48034000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 48034000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 176792000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 176792000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 225078000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 225078000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 225078000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 225078000 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 224826000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 224826000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 224826000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 224826000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 94754490 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 94754490 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520730 # number of WriteReq accesses(hits+misses) @@ -209,14 +209,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50827.368421 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 50827.368421 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50562.105263 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 50562.105263 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55212.991880 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 55212.991880 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 54209.537572 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 54209.537572 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 54209.537572 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 54209.537572 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 54148.843931 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 54148.843931 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 54148.843931 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 54148.843931 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -235,14 +235,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4152 system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 45436000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 45436000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 45184000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 45184000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 167186000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 167186000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 212622000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 212622000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 212622000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 212622000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 212370000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 212370000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 212370000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 212370000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses @@ -251,63 +251,63 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47827.368421 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47827.368421 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47562.105263 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47562.105263 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52212.991880 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52212.991880 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51209.537572 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 51209.537572 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51209.537572 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 51209.537572 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51148.843931 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 51148.843931 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51148.843931 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 51148.843931 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 13 # number of replacements -system.cpu.l2cache.tagsinuse 3768.712262 # Cycle average of tags in use -system.cpu.l2cache.total_refs 656 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 4572 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.143482 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.tagsinuse 3772.462815 # Cycle average of tags in use +system.cpu.l2cache.total_refs 674 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 4566 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.147613 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 371.536808 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2770.454482 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 626.720973 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 371.536806 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2770.454477 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 630.471532 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.011338 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.084548 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.019126 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.115012 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.019240 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.115126 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 468 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 117 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 585 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 123 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 591 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 649 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 649 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 60 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 60 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.inst 468 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 177 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 645 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 183 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 651 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 468 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 177 # number of overall hits -system.cpu.l2cache.overall_hits::total 645 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 183 # number of overall hits +system.cpu.l2cache.overall_hits::total 651 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 3205 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 833 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 4038 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 827 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 4032 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 3142 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 3142 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 3205 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 3975 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 7180 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 3969 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 7174 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 3205 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 3975 # number of overall misses -system.cpu.l2cache.overall_misses::total 7180 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 3969 # number of overall misses +system.cpu.l2cache.overall_misses::total 7174 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 166660000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 43316000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 209976000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 43004000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 209664000 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 163384000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 163384000 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 166660000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 206700000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 373360000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 206388000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 373048000 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 166660000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 206700000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 373360000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 206388000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 373048000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 3673 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 950 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 4623 # number of ReadReq accesses(hits+misses) @@ -322,16 +322,16 @@ system.cpu.l2cache.overall_accesses::cpu.inst 3673 system.cpu.l2cache.overall_accesses::cpu.data 4152 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 7825 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.872584 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.876842 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.873459 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.870526 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.872161 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.981262 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.981262 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.872584 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.957370 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.917572 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.955925 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.916805 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.872584 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.957370 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.917572 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.955925 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.916805 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency @@ -352,38 +352,38 @@ system.cpu.l2cache.avg_blocked_cycles::no_targets nan system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3205 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 833 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 4038 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 827 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 4032 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3142 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 3142 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 3205 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 3975 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 7180 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 3969 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 7174 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 3205 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 3975 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 7180 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 3969 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 7174 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 128200000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 33320000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 161520000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 33080000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 161280000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 125680000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 125680000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 128200000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 159000000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 287200000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 158760000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 286960000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 128200000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 159000000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 287200000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 158760000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 286960000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.876842 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.873459 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.870526 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.872161 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.981262 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.981262 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.957370 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.917572 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.916805 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.957370 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.917572 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.916805 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini index b166901dc..27728d570 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini @@ -507,7 +507,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -cwd=build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing +cwd=build/ARM/tests/fast/long/se/30.eon/arm/linux/o3-timing egid=100 env= errout=cerr diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout index fd4ba336e..e6faeb5f0 100755 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:14:06 -gem5 started Jun 4 2012 17:54:41 +gem5 compiled Jun 28 2012 22:10:14 +gem5 started Jun 29 2012 00:48:53 gem5 executing on zizzer -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/30.eon/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -13,4 +13,4 @@ info: Increasing stack size by one page. info: Increasing stack size by one page. info: Increasing stack size by one page. OO-style eon Time= 0.070000 -Exiting @ tick 71774859500 because target called exit() +Exiting @ tick 71244143500 because target called exit() diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index 154ddb0a7..e982040ed 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -1,32 +1,32 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.071775 # Number of seconds simulated -sim_ticks 71774859500 # Number of ticks simulated -final_tick 71774859500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.071244 # Number of seconds simulated +sim_ticks 71244143500 # Number of ticks simulated +final_tick 71244143500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 120484 # Simulator instruction rate (inst/s) -host_op_rate 154032 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 31671128 # Simulator tick rate (ticks/s) -host_mem_usage 240520 # Number of bytes of host memory used -host_seconds 2266.26 # Real time elapsed on the host -sim_insts 273048474 # Number of instructions simulated -sim_ops 349076199 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 199168 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 273728 # Number of bytes read from this memory -system.physmem.bytes_read::total 472896 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 199168 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 199168 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3112 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 4277 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7389 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2774899 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3813703 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6588602 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2774899 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2774899 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2774899 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3813703 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6588602 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 187993 # Simulator instruction rate (inst/s) +host_op_rate 240337 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 49051248 # Simulator tick rate (ticks/s) +host_mem_usage 243200 # Number of bytes of host memory used +host_seconds 1452.44 # Real time elapsed on the host +sim_insts 273048446 # Number of instructions simulated +sim_ops 349076170 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 195520 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 273792 # Number of bytes read from this memory +system.physmem.bytes_read::total 469312 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 195520 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 195520 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3055 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 4278 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7333 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2744366 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3843011 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6587377 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2744366 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2744366 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2744366 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3843011 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6587377 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -70,107 +70,107 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 143549720 # number of cpu cycles simulated +system.cpu.numCycles 142488288 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 37175542 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 22262323 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 2214096 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 22505770 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 18082192 # Number of BTB hits +system.cpu.BPredUnit.lookups 36834655 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 22011992 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 2128141 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 21111775 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 17921807 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 7072101 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 52600 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 41561697 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 332366381 # Number of instructions fetch has processed -system.cpu.fetch.Branches 37175542 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 25154293 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 74569841 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 8920940 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 20643175 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 124 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 4492 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 39951299 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 710527 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 143433675 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.978110 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.454958 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 7049660 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 9673 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 41170537 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 330092344 # Number of instructions fetch has processed +system.cpu.fetch.Branches 36834655 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 24971467 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 74065448 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 8653461 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 20659218 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 37 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 3712 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 39589827 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 662584 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 142371733 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.982100 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.456260 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 69560380 48.50% 48.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 7529870 5.25% 53.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 5927266 4.13% 57.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 6353418 4.43% 62.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 5053258 3.52% 65.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4245115 2.96% 68.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3249040 2.27% 71.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 4338891 3.03% 74.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 37176437 25.92% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 68999572 48.46% 48.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 7443838 5.23% 53.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 5890912 4.14% 57.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 6290109 4.42% 62.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 5018667 3.53% 65.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4222472 2.97% 68.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3222890 2.26% 71.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4319860 3.03% 74.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 36963413 25.96% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 143433675 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.258973 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.315340 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 48398038 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 15922899 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 70106313 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 2422163 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 6584262 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 7647961 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 70686 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 419107715 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 208401 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 6584262 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 54237445 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1551128 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 362766 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 66624532 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 14073542 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 408263314 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 21 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1648402 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 10108765 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 752 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 447190592 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2407780645 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1318183800 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1089596845 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 384584999 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 62605593 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 23936 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 23899 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 35817763 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 106133186 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 93562284 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 4587440 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5646194 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 394242574 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 33887 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 379407553 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1341475 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 44167400 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 116755410 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 9405 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 143433675 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.645178 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.047092 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 142371733 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.258510 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.316628 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 47920905 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 15947714 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 69670851 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 2428941 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 6403322 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 7589257 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 69989 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 416841547 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 209997 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 6403322 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 53735690 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1551358 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 361067 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 66219864 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 14100432 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 406248964 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 31 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1649610 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 10115480 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 773 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 445265070 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2397426033 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1310073571 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1087352462 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 384584954 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 60680116 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 19505 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 19502 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 35831958 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 105842469 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 93258241 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 4666139 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5699487 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 393022623 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 30465 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 378573033 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1364119 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 42964941 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 113697743 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 5987 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 142371733 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.659046 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.045030 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 29947758 20.88% 20.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 20633542 14.39% 35.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 21077069 14.69% 49.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 18246072 12.72% 62.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 24216587 16.88% 79.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 16050569 11.19% 90.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 9012327 6.28% 97.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3309506 2.31% 99.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 940245 0.66% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 29238426 20.54% 20.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 20559915 14.44% 34.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 20888687 14.67% 49.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 18235605 12.81% 62.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 24142271 16.96% 79.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 16046767 11.27% 90.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 9027765 6.34% 97.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3298956 2.32% 99.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 933341 0.66% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 143433675 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 142371733 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9527 0.05% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 4696 0.03% 0.08% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9050 0.05% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 4700 0.03% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.08% # attempts to use FU when none available @@ -189,203 +189,203 @@ system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.08% # at system.cpu.iq.fu_full::SimdShift 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 47773 0.27% 0.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 7824 0.04% 0.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 381 0.00% 0.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 48305 0.27% 0.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 7771 0.04% 0.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 390 0.00% 0.39% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatDiv 3 0.00% 0.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 194196 1.08% 1.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 4065 0.02% 1.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 241389 1.34% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9461548 52.57% 55.40% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 8027461 44.60% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 194430 1.08% 1.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 4896 0.03% 1.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 241266 1.34% 2.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.85% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9438470 52.59% 55.43% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 7998776 44.57% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 129140993 34.04% 34.04% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2178888 0.57% 34.61% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.61% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.61% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.61% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.61% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.61% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.61% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.61% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.61% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.61% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.61% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 3 0.00% 34.61% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.61% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.61% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.61% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.61% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.61% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.61% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.61% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 6841737 1.80% 36.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 8706483 2.29% 38.71% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 3462240 0.91% 39.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1609824 0.42% 40.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 21270001 5.61% 45.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 7182346 1.89% 47.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 7142588 1.88% 49.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 175287 0.05% 49.47% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 102963295 27.14% 76.61% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 88733868 23.39% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 128705433 34.00% 34.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2178586 0.58% 34.57% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 5 0.00% 34.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 6839771 1.81% 36.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 8697995 2.30% 38.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 3451888 0.91% 39.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1605167 0.42% 40.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 21254253 5.61% 45.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 7183697 1.90% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 7136969 1.89% 49.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 49.46% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 102677998 27.12% 76.58% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 88665985 23.42% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 379407553 # Type of FU issued -system.cpu.iq.rate 2.643039 # Inst issue rate -system.cpu.iq.fu_busy_cnt 17998863 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.047439 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 670841771 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 305961612 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 253223434 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 250747348 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 132496015 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 118776381 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 268120952 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 129285464 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 10792483 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 378573033 # Type of FU issued +system.cpu.iq.rate 2.656871 # Inst issue rate +system.cpu.iq.fu_busy_cnt 17948057 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.047410 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 668230837 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 303627249 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 252741444 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 250599138 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 132404625 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 118730959 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 267327381 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 129193709 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 10789214 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 11482088 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 116027 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 13932 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 11184344 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 11191376 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 112013 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 13979 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 10880305 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 9709 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 181 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 7857 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 112 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 6584262 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 34186 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1479 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 394326849 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1347232 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 106133186 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 93562284 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 22722 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 192 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 169 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 13932 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1780753 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 562062 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 2342815 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 374477920 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 101438803 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 4929633 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 6403322 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 34047 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1473 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 393102382 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1223414 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 105842469 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 93258241 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 19294 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 195 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 174 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 13979 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1692038 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 558009 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 2250047 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 373788733 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 101161202 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 4784300 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 50388 # number of nop insts executed -system.cpu.iew.exec_refs 188856020 # number of memory reference insts executed -system.cpu.iew.exec_branches 32491949 # Number of branches executed -system.cpu.iew.exec_stores 87417217 # Number of stores executed -system.cpu.iew.exec_rate 2.608698 # Inst execution rate -system.cpu.iew.wb_sent 372876985 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 371999815 # cumulative count of insts written-back -system.cpu.iew.wb_producers 185166823 # num instructions producing a value -system.cpu.iew.wb_consumers 368327153 # num instructions consuming a value +system.cpu.iew.exec_nop 49294 # number of nop insts executed +system.cpu.iew.exec_refs 188542226 # number of memory reference insts executed +system.cpu.iew.exec_branches 32415827 # Number of branches executed +system.cpu.iew.exec_stores 87381024 # Number of stores executed +system.cpu.iew.exec_rate 2.623294 # Inst execution rate +system.cpu.iew.wb_sent 372275263 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 371472403 # cumulative count of insts written-back +system.cpu.iew.wb_producers 184833323 # num instructions producing a value +system.cpu.iew.wb_consumers 367854017 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.591435 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.502724 # average fanout of values written-back +system.cpu.iew.wb_rate 2.607038 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.502464 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 273049086 # The number of committed instructions -system.cpu.commit.commitCommittedOps 349076811 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 45250302 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 24482 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 2186131 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 136849414 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.550810 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.650371 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 273049058 # The number of committed instructions +system.cpu.commit.commitCommittedOps 349076782 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 44025608 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 24478 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 2100754 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 135968412 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.567337 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.653672 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 39364225 28.76% 28.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 29162916 21.31% 50.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13605145 9.94% 60.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11228015 8.20% 68.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 13810148 10.09% 78.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7236976 5.29% 83.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 4020101 2.94% 86.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3901622 2.85% 89.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 14520266 10.61% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 38641813 28.42% 28.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 29058445 21.37% 49.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13534255 9.95% 59.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11222379 8.25% 68.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 13789944 10.14% 78.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7224545 5.31% 83.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 4032637 2.97% 86.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3910785 2.88% 89.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 14553609 10.70% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 136849414 # Number of insts commited each cycle -system.cpu.commit.committedInsts 273049086 # Number of instructions committed -system.cpu.commit.committedOps 349076811 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 135968412 # Number of insts commited each cycle +system.cpu.commit.committedInsts 273049058 # Number of instructions committed +system.cpu.commit.committedOps 349076782 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 177029038 # Number of memory references committed -system.cpu.commit.loads 94651098 # Number of loads committed +system.cpu.commit.refs 177029029 # Number of memory references committed +system.cpu.commit.loads 94651093 # Number of loads committed system.cpu.commit.membars 11033 # Number of memory barriers committed -system.cpu.commit.branches 30523993 # Number of branches committed +system.cpu.commit.branches 30523988 # Number of branches committed system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions. -system.cpu.commit.int_insts 279594011 # Number of committed integer instructions. +system.cpu.commit.int_insts 279593987 # Number of committed integer instructions. system.cpu.commit.function_calls 6225112 # Number of function calls committed. -system.cpu.commit.bw_lim_events 14520266 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 14553609 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 516653738 # The number of ROB reads -system.cpu.rob.rob_writes 795243409 # The number of ROB writes -system.cpu.timesIdled 2720 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 116045 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 273048474 # Number of Instructions Simulated -system.cpu.committedOps 349076199 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 273048474 # Number of Instructions Simulated -system.cpu.cpi 0.525730 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.525730 # CPI: Total CPI of All Threads -system.cpu.ipc 1.902118 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.902118 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1788157543 # number of integer regfile reads -system.cpu.int_regfile_writes 236964047 # number of integer regfile writes -system.cpu.fp_regfile_reads 189767378 # number of floating regfile reads -system.cpu.fp_regfile_writes 133494852 # number of floating regfile writes -system.cpu.misc_regfile_reads 995239791 # number of misc regfile reads -system.cpu.misc_regfile_writes 34426479 # number of misc regfile writes -system.cpu.icache.replacements 14190 # number of replacements -system.cpu.icache.tagsinuse 1864.933817 # Cycle average of tags in use -system.cpu.icache.total_refs 39934285 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 16092 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 2481.623478 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 514514670 # The number of ROB reads +system.cpu.rob.rob_writes 792612920 # The number of ROB writes +system.cpu.timesIdled 2826 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 116555 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 273048446 # Number of Instructions Simulated +system.cpu.committedOps 349076170 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 273048446 # Number of Instructions Simulated +system.cpu.cpi 0.521843 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.521843 # CPI: Total CPI of All Threads +system.cpu.ipc 1.916287 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.916287 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1784947411 # number of integer regfile reads +system.cpu.int_regfile_writes 236351279 # number of integer regfile writes +system.cpu.fp_regfile_reads 189697788 # number of floating regfile reads +system.cpu.fp_regfile_writes 133433924 # number of floating regfile writes +system.cpu.misc_regfile_reads 991980863 # number of misc regfile reads +system.cpu.misc_regfile_writes 34426471 # number of misc regfile writes +system.cpu.icache.replacements 14091 # number of replacements +system.cpu.icache.tagsinuse 1855.139503 # Cycle average of tags in use +system.cpu.icache.total_refs 39573076 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 15985 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 2475.638161 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1864.933817 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.910612 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.910612 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 39934285 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 39934285 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 39934285 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 39934285 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 39934285 # number of overall hits -system.cpu.icache.overall_hits::total 39934285 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 17014 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 17014 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 17014 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 17014 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 17014 # number of overall misses -system.cpu.icache.overall_misses::total 17014 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 211050500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 211050500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 211050500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 211050500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 211050500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 211050500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 39951299 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 39951299 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 39951299 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 39951299 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 39951299 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 39951299 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000426 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000426 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000426 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000426 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000426 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000426 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 12404.519807 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 12404.519807 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 12404.519807 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 12404.519807 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 12404.519807 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 12404.519807 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1855.139503 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.905830 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.905830 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 39573076 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 39573076 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 39573076 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 39573076 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 39573076 # number of overall hits +system.cpu.icache.overall_hits::total 39573076 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 16751 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 16751 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 16751 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 16751 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 16751 # number of overall misses +system.cpu.icache.overall_misses::total 16751 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 205369500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 205369500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 205369500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 205369500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 205369500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 205369500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 39589827 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 39589827 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 39589827 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 39589827 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 39589827 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 39589827 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000423 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000423 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000423 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000423 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000423 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000423 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 12260.133723 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 12260.133723 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 12260.133723 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 12260.133723 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 12260.133723 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 12260.133723 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -394,252 +394,250 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 900 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 900 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 900 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 900 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 900 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 900 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16114 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 16114 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 16114 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 16114 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 16114 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 16114 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 139714000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 139714000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 139714000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 139714000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 139714000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 139714000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000403 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000403 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000403 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000403 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000403 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000403 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8670.348765 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 8670.348765 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8670.348765 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 8670.348765 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8670.348765 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 8670.348765 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 765 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 765 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 765 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 765 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 765 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 765 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15986 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 15986 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 15986 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 15986 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 15986 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 15986 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 137471000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 137471000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 137471000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 137471000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 137471000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 137471000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000404 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000404 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000404 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000404 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000404 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000404 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8599.462029 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 8599.462029 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8599.462029 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 8599.462029 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8599.462029 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 8599.462029 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1427 # number of replacements -system.cpu.dcache.tagsinuse 3127.647604 # Cycle average of tags in use -system.cpu.dcache.total_refs 172501472 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 4641 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 37169.030812 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1422 # number of replacements +system.cpu.dcache.tagsinuse 3120.754345 # Cycle average of tags in use +system.cpu.dcache.total_refs 172231049 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 4634 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 37166.821105 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3127.647604 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.763586 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.763586 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 90441052 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 90441052 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 82033132 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 82033132 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 14008 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 14008 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 13257 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 13257 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 172474184 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 172474184 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 172474184 # number of overall hits -system.cpu.dcache.overall_hits::total 172474184 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 3598 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 3598 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 19528 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 19528 # number of WriteReq misses +system.cpu.dcache.occ_blocks::cpu.data 3120.754345 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.761903 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.761903 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 90171406 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 90171406 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 82032842 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 82032842 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 13547 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 13547 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 13253 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 13253 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 172204248 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 172204248 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 172204248 # number of overall hits +system.cpu.dcache.overall_hits::total 172204248 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 3698 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 3698 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 19818 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 19818 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 23126 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 23126 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 23126 # number of overall misses -system.cpu.dcache.overall_misses::total 23126 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 115634000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 115634000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 650274000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 650274000 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 23516 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 23516 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 23516 # number of overall misses +system.cpu.dcache.overall_misses::total 23516 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 118442000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 118442000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 655611500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 655611500 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 76000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 76000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 765908000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 765908000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 765908000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 765908000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 90444650 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 90444650 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 774053500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 774053500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 774053500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 774053500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 90175104 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 90175104 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052660 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052660 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 14010 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 14010 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 13257 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 13257 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 172497310 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 172497310 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 172497310 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 172497310 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000040 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000040 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000238 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000238 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000143 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000143 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000134 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000134 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000134 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000134 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32138.410228 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 32138.410228 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33299.569848 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33299.569848 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13549 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 13549 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 13253 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 13253 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 172227764 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 172227764 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 172227764 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 172227764 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000041 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000041 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000242 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000242 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000148 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000148 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000137 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000137 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000137 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000137 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32028.664143 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 32028.664143 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33081.617721 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33081.617721 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38000 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 38000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 33118.913777 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 33118.913777 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 33118.913777 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 33118.913777 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 32916.035890 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 32916.035890 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 32916.035890 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 32916.035890 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 315000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 307000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 13 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 24230.769231 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 27909.090909 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1038 # number of writebacks -system.cpu.dcache.writebacks::total 1038 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1792 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1792 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16671 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16671 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 1041 # number of writebacks +system.cpu.dcache.writebacks::total 1041 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1882 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1882 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16999 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16999 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 18463 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 18463 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 18463 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 18463 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1806 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1806 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2857 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2857 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4663 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4663 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4663 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4663 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 54896500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 54896500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 101557000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 101557000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 156453500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 156453500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 156453500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 156453500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_hits::cpu.data 18881 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 18881 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 18881 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 18881 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1816 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1816 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2819 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2819 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4635 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4635 # 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number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 45668000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 142411500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 682000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 682000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 88208000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 88208000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 96743500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 133876000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 230619500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 96743500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 133876000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 230619500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.193388 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.807756 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.255350 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994006 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994006 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.193388 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.921569 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.356388 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.193388 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.921569 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.356388 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31087.242931 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31322.359396 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31162.253829 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31290.528556 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31290.528556 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31087.242931 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31301.379472 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31211.192313 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31087.242931 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31301.379472 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31211.192313 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 14 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 37 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 51 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 14 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 37 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 51 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 14 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 37 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 51 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3055 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1476 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 4531 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2802 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 2802 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3055 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 4278 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 7333 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3055 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 4278 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 7333 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 94947500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 46180500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 141128000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 87716500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 87716500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 94947500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 133897000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 228844500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 94947500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 133897000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 228844500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.191117 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.813671 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.254565 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.993617 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.993617 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.191117 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.923177 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.355643 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.191117 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.923177 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.355643 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31079.378069 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31287.601626 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31147.208122 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31304.960742 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31304.960742 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31079.378069 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31298.971482 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31207.486704 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31079.378069 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31298.971482 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31207.486704 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini index 796e4e4fa..8af4db376 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini @@ -95,7 +95,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -cwd=build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic +cwd=build/ARM/tests/fast/long/se/30.eon/arm/linux/simple-atomic egid=100 env= errout=cerr diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout index 80d4c141d..0dc5c6cdd 100755 --- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:14:06 -gem5 started Jun 4 2012 18:01:26 +gem5 compiled Jun 28 2012 22:10:14 +gem5 started Jun 29 2012 00:54:17 gem5 executing on zizzer -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/30.eon/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/30.eon/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -13,4 +13,4 @@ info: Increasing stack size by one page. info: Increasing stack size by one page. info: Increasing stack size by one page. OO-style eon Time= 0.210000 -Exiting @ tick 212344048000 because target called exit() +Exiting @ tick 212344043000 because target called exit() diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt index 1239fc01a..4a3f2e632 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt @@ -1,38 +1,38 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.212344 # Number of seconds simulated -sim_ticks 212344048000 # Number of ticks simulated -final_tick 212344048000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 212344043000 # Number of ticks simulated +final_tick 212344043000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1586428 # Simulator instruction rate (inst/s) -host_op_rate 2028172 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1233780581 # Simulator tick rate (ticks/s) -host_mem_usage 229108 # Number of bytes of host memory used -host_seconds 172.11 # Real time elapsed on the host -sim_insts 273037671 # Number of instructions simulated -sim_ops 349065408 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 1394641440 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 480709269 # Number of bytes read from this memory -system.physmem.bytes_read::total 1875350709 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1394641440 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1394641440 # Number of instructions bytes read from this memory +host_inst_rate 2237295 # Simulator instruction rate (inst/s) +host_op_rate 2860273 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1739965936 # Simulator tick rate (ticks/s) +host_mem_usage 232696 # Number of bytes of host memory used +host_seconds 122.04 # Real time elapsed on the host +sim_insts 273037663 # Number of instructions simulated +sim_ops 349065399 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 1394641404 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 480709268 # Number of bytes read from this memory +system.physmem.bytes_read::total 1875350672 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1394641404 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1394641404 # Number of instructions bytes read from this memory system.physmem.bytes_written::cpu.data 400047783 # Number of bytes written to this memory system.physmem.bytes_written::total 400047783 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 348660360 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 94582506 # Number of read requests responded to by this memory -system.physmem.num_reads::total 443242866 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 348660351 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 94582505 # Number of read requests responded to by this memory +system.physmem.num_reads::total 443242856 # Number of read requests responded to by this memory system.physmem.num_writes::cpu.data 82063572 # Number of write requests responded to by this memory system.physmem.num_writes::total 82063572 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 6567838624 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2263822667 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 8831661291 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 6567838624 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 6567838624 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1883960425 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1883960425 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 6567838624 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4147783092 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 10715621716 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 6567838609 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2263822715 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 8831661324 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 6567838609 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 6567838609 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1883960470 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1883960470 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 6567838609 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4147783185 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 10715621794 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -76,26 +76,26 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 424688097 # number of cpu cycles simulated +system.cpu.numCycles 424688087 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 273037671 # Number of instructions committed -system.cpu.committedOps 349065408 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 279584926 # Number of integer alu accesses +system.cpu.committedInsts 273037663 # Number of instructions committed +system.cpu.committedOps 349065399 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 279584918 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses -system.cpu.num_func_calls 12433363 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 18087062 # number of instructions that are conditional controls -system.cpu.num_int_insts 279584926 # number of integer instructions +system.cpu.num_func_calls 12448615 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 18087061 # number of instructions that are conditional controls +system.cpu.num_int_insts 279584918 # number of integer instructions system.cpu.num_fp_insts 114216705 # number of float instructions -system.cpu.num_int_register_reads 1887652191 # number of times the integer registers were read -system.cpu.num_int_register_writes 251197918 # number of times the integer registers were written +system.cpu.num_int_register_reads 1887652153 # number of times the integer registers were read +system.cpu.num_int_register_writes 251197905 # number of times the integer registers were written system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written -system.cpu.num_mem_refs 177024357 # number of memory refs -system.cpu.num_load_insts 94648758 # Number of load instructions +system.cpu.num_mem_refs 177024356 # number of memory refs +system.cpu.num_load_insts 94648757 # Number of load instructions system.cpu.num_store_insts 82375599 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 424688097 # Number of busy cycles +system.cpu.num_busy_cycles 424688087 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini index f88d3c19b..68ac46334 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini @@ -176,7 +176,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -cwd=build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing +cwd=build/ARM/tests/fast/long/se/30.eon/arm/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout b/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout index 02e894db6..ddb90c634 100755 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:14:06 -gem5 started Jun 4 2012 18:04:29 +gem5 compiled Jun 28 2012 22:10:14 +gem5 started Jun 29 2012 00:56:30 gem5 executing on zizzer -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/30.eon/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/30.eon/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -13,4 +13,4 @@ info: Increasing stack size by one page. info: Increasing stack size by one page. info: Increasing stack size by one page. OO-style eon Time= 0.520000 -Exiting @ tick 525854475000 because target called exit() +Exiting @ tick 525854423000 because target called exit() diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt index ce6e736cb..bbdf06ba7 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt @@ -1,32 +1,32 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.525854 # Number of seconds simulated -sim_ticks 525854475000 # Number of ticks simulated -final_tick 525854475000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 525854423000 # Number of ticks simulated +final_tick 525854423000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 697015 # Simulator instruction rate (inst/s) -host_op_rate 891108 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1343878935 # Simulator tick rate (ticks/s) -host_mem_usage 238268 # Number of bytes of host memory used -host_seconds 391.30 # Real time elapsed on the host -sim_insts 272739291 # Number of instructions simulated -sim_ops 348687131 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 167040 # Number of bytes read from this memory +host_inst_rate 1009014 # Simulator instruction rate (inst/s) +host_op_rate 1289987 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1945426950 # Simulator tick rate (ticks/s) +host_mem_usage 241152 # Number of bytes of host memory used +host_seconds 270.30 # Real time elapsed on the host +sim_insts 272739283 # Number of instructions simulated +sim_ops 348687122 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 166976 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 270272 # Number of bytes read from this memory -system.physmem.bytes_read::total 437312 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 167040 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 167040 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 2610 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 437248 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 166976 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 166976 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 2609 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 4223 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6833 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 317654 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 6832 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 317533 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 513967 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 831622 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 317654 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 317654 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 317654 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 831500 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 317533 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 317533 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 317533 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 513967 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 831622 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 831500 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -70,73 +70,73 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 1051708950 # number of cpu cycles simulated +system.cpu.numCycles 1051708846 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 272739291 # Number of instructions committed -system.cpu.committedOps 348687131 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 279584925 # Number of integer alu accesses +system.cpu.committedInsts 272739283 # Number of instructions committed +system.cpu.committedOps 348687122 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 279584917 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses -system.cpu.num_func_calls 12433363 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 18087061 # number of instructions that are conditional controls -system.cpu.num_int_insts 279584925 # number of integer instructions +system.cpu.num_func_calls 12448615 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 18087060 # number of instructions that are conditional controls +system.cpu.num_int_insts 279584917 # number of integer instructions system.cpu.num_fp_insts 114216705 # number of float instructions -system.cpu.num_int_register_reads 2212913209 # number of times the integer registers were read -system.cpu.num_int_register_writes 251197915 # number of times the integer registers were written +system.cpu.num_int_register_reads 2212913168 # number of times the integer registers were read +system.cpu.num_int_register_writes 251197902 # number of times the integer registers were written system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written -system.cpu.num_mem_refs 177024357 # number of memory refs -system.cpu.num_load_insts 94648758 # Number of load instructions +system.cpu.num_mem_refs 177024356 # number of memory refs +system.cpu.num_load_insts 94648757 # Number of load instructions system.cpu.num_store_insts 82375599 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 1051708950 # Number of busy cycles +system.cpu.num_busy_cycles 1051708846 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 13796 # number of replacements -system.cpu.icache.tagsinuse 1765.984158 # Cycle average of tags in use -system.cpu.icache.total_refs 348644756 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1765.984191 # Cycle average of tags in use +system.cpu.icache.total_refs 348644747 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 15603 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 22344.725758 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 22344.725181 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1765.984158 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 1765.984191 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.862297 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.862297 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 348644756 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 348644756 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 348644756 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 348644756 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 348644756 # number of overall hits -system.cpu.icache.overall_hits::total 348644756 # number of overall hits +system.cpu.icache.ReadReq_hits::cpu.inst 348644747 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 348644747 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 348644747 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 348644747 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 348644747 # number of overall hits +system.cpu.icache.overall_hits::total 348644747 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 15603 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 15603 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 15603 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 15603 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 15603 # number of overall misses system.cpu.icache.overall_misses::total 15603 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 328062000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 328062000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 328062000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 328062000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 328062000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 328062000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 348660359 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 348660359 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 348660359 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 348660359 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 348660359 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 348660359 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 328020000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 328020000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 328020000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 328020000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 328020000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 328020000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 348660350 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 348660350 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 348660350 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 348660350 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 348660350 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 348660350 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000045 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000045 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000045 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000045 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000045 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21025.572005 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 21025.572005 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 21025.572005 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 21025.572005 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 21025.572005 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 21025.572005 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21022.880215 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 21022.880215 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 21022.880215 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 21022.880215 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 21022.880215 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 21022.880215 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -151,46 +151,46 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 15603 system.cpu.icache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 15603 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 15603 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281253000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 281253000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281253000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 281253000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281253000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 281253000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281211000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 281211000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281211000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 281211000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281211000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 281211000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000045 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18025.572005 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18025.572005 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18025.572005 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 18025.572005 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18025.572005 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 18025.572005 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18022.880215 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18022.880215 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18022.880215 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 18022.880215 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18022.880215 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 18022.880215 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 1332 # number of replacements -system.cpu.dcache.tagsinuse 3078.396238 # Cycle average of tags in use -system.cpu.dcache.total_refs 176641600 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 3078.396294 # Cycle average of tags in use +system.cpu.dcache.total_refs 176641599 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 4478 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 39446.538633 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 39446.538410 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3078.396238 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 3078.396294 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.751562 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.751562 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 94570005 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 94570005 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 94570004 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 94570004 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 82049805 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 82049805 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 176619810 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 176619810 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 176619810 # number of overall hits -system.cpu.dcache.overall_hits::total 176619810 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 176619809 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 176619809 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 176619809 # number of overall hits +system.cpu.dcache.overall_hits::total 176619809 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 1606 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 1606 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 2872 # number of WriteReq misses @@ -207,18 +207,18 @@ system.cpu.dcache.demand_miss_latency::cpu.data 240058000 system.cpu.dcache.demand_miss_latency::total 240058000 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 240058000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 240058000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 94571611 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 94571611 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 94571610 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 94571610 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 176624288 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 176624288 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 176624288 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 176624288 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 176624287 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 176624287 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 176624287 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 176624287 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000017 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000017 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000035 # miss rate for WriteReq accesses @@ -278,54 +278,54 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 50608.307280 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50608.307280 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 50608.307280 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 48 # number of replacements -system.cpu.l2cache.tagsinuse 3475.672922 # Cycle average of tags in use -system.cpu.l2cache.total_refs 13308 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 4883 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.725374 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.tagsinuse 3487.701804 # Cycle average of tags in use +system.cpu.l2cache.total_refs 13310 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 4882 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 2.726342 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 341.613272 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2402.300580 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 731.759070 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 341.613277 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2408.384377 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 737.704150 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.010425 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.073312 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.022332 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.106069 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 12993 # number of ReadReq hits +system.cpu.l2cache.occ_percent::cpu.inst 0.073498 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.022513 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.106436 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 12994 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 239 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 13232 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 13233 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 998 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 998 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 16 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 12993 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 12994 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 255 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 13248 # 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