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-rw-r--r--tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini2
-rwxr-xr-xtests/long/se/30.eon/ref/arm/linux/o3-timing/simout6
-rw-r--r--tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt12
3 files changed, 10 insertions, 10 deletions
diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini
index d73a74668..7f3ecc8dc 100644
--- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini
@@ -594,7 +594,7 @@ id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
-id_aa64pfr0_el1=17
+id_aa64pfr0_el1=34
id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout
index 7e2bba88d..c5508bf05 100755
--- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing/sim
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jul 21 2016 14:37:41
-gem5 started Jul 21 2016 15:06:52
-gem5 executing on e108600-lin, pid 24264
+gem5 compiled Aug 1 2016 17:10:05
+gem5 started Aug 1 2016 17:10:34
+gem5 executing on e108600-lin, pid 12223
command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/30.eon/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
index cc1788f11..01e70293e 100644
--- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.111754 # Nu
sim_ticks 111753553500 # Number of ticks simulated
final_tick 111753553500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 162111 # Simulator instruction rate (inst/s)
-host_op_rate 194632 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 66351635 # Simulator tick rate (ticks/s)
-host_mem_usage 287668 # Number of bytes of host memory used
-host_seconds 1684.26 # Real time elapsed on the host
+host_inst_rate 142273 # Simulator instruction rate (inst/s)
+host_op_rate 170814 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 58231903 # Simulator tick rate (ticks/s)
+host_mem_usage 288696 # Number of bytes of host memory used
+host_seconds 1919.11 # Real time elapsed on the host
sim_insts 273037220 # Number of instructions simulated
sim_ops 327811602 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@@ -681,7 +681,7 @@ system.cpu.fp_regfile_reads 186641875 # nu
system.cpu.fp_regfile_writes 131668024 # number of floating regfile writes
system.cpu.cc_regfile_reads 1279432977 # number of cc regfile reads
system.cpu.cc_regfile_writes 80060950 # number of cc regfile writes
-system.cpu.misc_regfile_reads 1056766060 # number of misc regfile reads
+system.cpu.misc_regfile_reads 1056766062 # number of misc regfile reads
system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 1542955 # number of replacements