diff options
Diffstat (limited to 'tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt')
| -rw-r--r-- | tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt | 829 |
1 files changed, 0 insertions, 829 deletions
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt deleted file mode 100644 index 42592acc9..000000000 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt +++ /dev/null @@ -1,829 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.521167 # Number of seconds simulated -sim_ticks 521167228000 # Number of ticks simulated -final_tick 521167228000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 492017 # Simulator instruction rate (inst/s) -host_op_rate 492017 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 276083455 # Simulator tick rate (ticks/s) -host_mem_usage 263220 # Number of bytes of host memory used -host_seconds 1887.72 # Real time elapsed on the host -sim_insts 928789150 # Number of instructions simulated -sim_ops 928789150 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 521167228000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 185984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 18520896 # Number of bytes read from this memory -system.physmem.bytes_read::total 18706880 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 185984 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 185984 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4267712 # Number of bytes written to this memory -system.physmem.bytes_written::total 4267712 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2906 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 289389 # Number of read requests responded to by this memory -system.physmem.num_reads::total 292295 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory -system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 356861 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 35537338 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 35894199 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 356861 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 356861 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 8188757 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 8188757 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 8188757 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 356861 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 35537338 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 44082956 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 292295 # Number of read requests accepted -system.physmem.writeReqs 66683 # Number of write requests accepted -system.physmem.readBursts 292295 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 66683 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 18686976 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 19904 # Total number of bytes read from write queue -system.physmem.bytesWritten 4265856 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 18706880 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 4267712 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 311 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 18028 # Per bank write bursts -system.physmem.perBankRdBursts::1 18369 # Per bank write bursts -system.physmem.perBankRdBursts::2 18396 # Per bank write bursts -system.physmem.perBankRdBursts::3 18341 # Per bank write bursts -system.physmem.perBankRdBursts::4 18255 # Per bank write bursts -system.physmem.perBankRdBursts::5 18258 # Per bank write bursts -system.physmem.perBankRdBursts::6 18325 # Per bank write bursts -system.physmem.perBankRdBursts::7 18297 # Per bank write bursts -system.physmem.perBankRdBursts::8 18227 # Per bank write bursts -system.physmem.perBankRdBursts::9 18235 # Per bank write bursts -system.physmem.perBankRdBursts::10 18232 # Per bank write bursts -system.physmem.perBankRdBursts::11 18375 # Per bank write bursts -system.physmem.perBankRdBursts::12 18268 # Per bank write bursts -system.physmem.perBankRdBursts::13 18134 # Per bank write bursts -system.physmem.perBankRdBursts::14 18057 # Per bank write bursts -system.physmem.perBankRdBursts::15 18187 # Per bank write bursts -system.physmem.perBankWrBursts::0 4123 # Per bank write bursts -system.physmem.perBankWrBursts::1 4164 # Per bank write bursts -system.physmem.perBankWrBursts::2 4221 # Per bank write bursts -system.physmem.perBankWrBursts::3 4157 # Per bank write bursts -system.physmem.perBankWrBursts::4 4141 # Per bank write bursts -system.physmem.perBankWrBursts::5 4097 # Per bank write bursts -system.physmem.perBankWrBursts::6 4260 # Per bank write bursts -system.physmem.perBankWrBursts::7 4224 # Per bank write bursts -system.physmem.perBankWrBursts::8 4233 # Per bank write bursts -system.physmem.perBankWrBursts::9 4192 # Per bank write bursts -system.physmem.perBankWrBursts::10 4150 # Per bank write bursts -system.physmem.perBankWrBursts::11 4241 # Per bank write bursts -system.physmem.perBankWrBursts::12 4098 # Per bank write bursts -system.physmem.perBankWrBursts::13 4100 # Per bank write bursts -system.physmem.perBankWrBursts::14 4096 # Per bank write bursts -system.physmem.perBankWrBursts::15 4157 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 521167139500 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 292295 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 66683 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 291434 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 537 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 13 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 895 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 896 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4047 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4054 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4055 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4056 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4055 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4055 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4055 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4055 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4055 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4055 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4056 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4056 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4059 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4056 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4054 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4054 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 95989 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 239.106731 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 159.105135 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 271.560992 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 28950 30.16% 30.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 41784 43.53% 73.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 11694 12.18% 85.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2599 2.71% 88.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 913 0.95% 89.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 756 0.79% 90.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 331 0.34% 90.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 447 0.47% 91.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8515 8.87% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 95989 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4054 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 68.753823 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 34.637200 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 730.740597 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 4046 99.80% 99.80% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.83% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::7168-8191 1 0.02% 99.85% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14336-15359 5 0.12% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::30720-31743 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4054 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4054 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.441539 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.421503 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.829633 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3159 77.92% 77.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 895 22.08% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4054 # Writes before turning the bus around for reads -system.physmem.totQLat 15194551500 # Total ticks spent queuing -system.physmem.totMemAccLat 20669251500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1459920000 # Total ticks spent in databus transfers -system.physmem.avgQLat 52038.99 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 70788.99 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 35.86 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 8.19 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 35.89 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 8.19 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.34 # Data bus utilization in percentage -system.physmem.busUtilRead 0.28 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.40 # Average write queue length when enqueuing -system.physmem.readRowHits 210474 # Number of row buffer hits during reads -system.physmem.writeRowHits 52167 # Number of row buffer hits during writes -system.physmem.readRowHitRate 72.08 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.23 # Row buffer hit rate for writes -system.physmem.avgGap 1451808.02 # Average gap between requests -system.physmem.pageHitRate 73.23 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 341770380 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 181632495 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1044360660 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 174280140 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 28691395200.000008 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 8105258640 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1605839040 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 57337999170 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 51043667520 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 64046185080 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 212592411075 # Total energy per rank (pJ) -system.physmem_0.averagePower 407.915916 # Core power per rank (mW) -system.physmem_0.totalIdleTime 499165974500 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 3167480750 # Time in different power states -system.physmem_0.memoryStateTime::REF 12206580000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 240498579500 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 132926079750 # Time in different power states -system.physmem_0.memoryStateTime::ACT 6626927000 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 125741581000 # Time in different power states -system.physmem_1.actEnergy 343648200 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 182645760 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1040405100 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 173653740 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 28803874320.000008 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 8196268830 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1616284320 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 57528037740 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 51141308640 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 63870409695 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 212914803135 # Total energy per rank (pJ) -system.physmem_1.averagePower 408.534516 # Core power per rank (mW) -system.physmem_1.totalIdleTime 498942805750 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 3183963500 # Time in different power states -system.physmem_1.memoryStateTime::REF 12254448000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 239604631750 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 133180372750 # Time in different power states -system.physmem_1.memoryStateTime::ACT 6785962500 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 126157849500 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 521167228000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 123851675 # Number of BP lookups -system.cpu.branchPred.condPredicted 79872959 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 686742 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 102066154 # Number of BTB lookups -system.cpu.branchPred.BTBHits 68190152 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 66.809759 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 18697401 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 11223 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 14052181 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 14048615 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 3566 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 11656 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 237539296 # DTB read hits -system.cpu.dtb.read_misses 195211 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 237734507 # DTB read accesses -system.cpu.dtb.write_hits 98305023 # DTB write hits -system.cpu.dtb.write_misses 7170 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 98312193 # DTB write accesses -system.cpu.dtb.data_hits 335844319 # DTB hits -system.cpu.dtb.data_misses 202381 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 336046700 # DTB accesses -system.cpu.itb.fetch_hits 286584578 # ITB hits -system.cpu.itb.fetch_misses 119 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 286584697 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 37 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 521167228000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 1042334456 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 928789150 # Number of instructions committed -system.cpu.committedOps 928789150 # Number of ops (including micro ops) committed -system.cpu.discardedOps 319598 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.122251 # CPI: cycles per instruction -system.cpu.ipc 0.891066 # IPC: instructions per cycle -system.cpu.op_class_0::No_OpClass 86206875 9.28% 9.28% # Class of committed instruction -system.cpu.op_class_0::IntAlu 486529511 52.38% 61.66% # Class of committed instruction -system.cpu.op_class_0::IntMult 7040 0.00% 61.67% # Class of committed instruction -system.cpu.op_class_0::IntDiv 0 0.00% 61.67% # Class of committed instruction -system.cpu.op_class_0::FloatAdd 13018262 1.40% 63.07% # Class of committed instruction -system.cpu.op_class_0::FloatCmp 3826477 0.41% 63.48% # Class of committed instruction -system.cpu.op_class_0::FloatCvt 3187663 0.34% 63.82% # Class of committed instruction -system.cpu.op_class_0::FloatMult 4 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::FloatMultAcc 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::FloatDiv 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::FloatMisc 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::FloatSqrt 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdAdd 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdAddAcc 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdAlu 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdCmp 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdCvt 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdMisc 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdMult 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdMultAcc 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdShift 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdShiftAcc 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdSqrt 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAdd 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAlu 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCmp 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCvt 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdFloatDiv 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMisc 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMult 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::MemRead 228135214 24.56% 88.39% # Class of committed instruction -system.cpu.op_class_0::MemWrite 94471145 10.17% 98.56% # Class of committed instruction -system.cpu.op_class_0::FloatMemRead 9570033 1.03% 99.59% # Class of committed instruction -system.cpu.op_class_0::FloatMemWrite 3836926 0.41% 100.00% # Class of committed instruction -system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::total 928789150 # Class of committed instruction -system.cpu.tickCycles 962817000 # Number of cycles that the object actually ticked -system.cpu.idleCycles 79517456 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 521167228000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 776559 # number of replacements -system.cpu.dcache.tags.tagsinuse 4092.209717 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 320318705 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 780655 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 410.320442 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 968708500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4092.209717 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999075 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999075 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 209 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 957 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1349 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1527 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 643115675 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 643115675 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 521167228000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 222154657 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 222154657 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 98164048 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 98164048 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 320318705 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 320318705 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 320318705 # number of overall hits -system.cpu.dcache.overall_hits::total 320318705 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 711653 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 711653 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 137152 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 137152 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 848805 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 848805 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 848805 # number of overall misses -system.cpu.dcache.overall_misses::total 848805 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 36922839000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 36922839000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10957317000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10957317000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 47880156000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 47880156000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 47880156000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 47880156000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 222866310 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 222866310 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 321167510 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 321167510 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 321167510 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 321167510 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003193 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.003193 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001395 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001395 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.002643 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002643 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.002643 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002643 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51883.205720 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 51883.205720 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 79891.777007 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 79891.777007 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 56408.899571 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 56408.899571 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 56408.899571 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 56408.899571 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 88440 # number of writebacks -system.cpu.dcache.writebacks::total 88440 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 9 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 9 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68141 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 68141 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 68150 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 68150 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 68150 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 68150 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711644 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 711644 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69011 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 69011 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 780655 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 780655 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 780655 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 780655 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36210490500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 36210490500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5501688000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5501688000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 41712178500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 41712178500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 41712178500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 41712178500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003193 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003193 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000702 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000702 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002431 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002431 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002431 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002431 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 50882.871913 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 50882.871913 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79721.899407 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79721.899407 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53432.282506 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 53432.282506 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53432.282506 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 53432.282506 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 521167228000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 10581 # number of replacements -system.cpu.icache.tags.tagsinuse 1690.101724 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 286572250 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 12327 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 23247.525756 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1690.101724 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.825245 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.825245 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1746 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 105 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1576 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.852539 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 573181483 # Number of tag accesses -system.cpu.icache.tags.data_accesses 573181483 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 521167228000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 286572250 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 286572250 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 286572250 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 286572250 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 286572250 # number of overall hits -system.cpu.icache.overall_hits::total 286572250 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 12328 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 12328 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 12328 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 12328 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 12328 # number of overall misses -system.cpu.icache.overall_misses::total 12328 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 376885500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 376885500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 376885500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 376885500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 376885500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 376885500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 286584578 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 286584578 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 286584578 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 286584578 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 286584578 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 286584578 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000043 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000043 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000043 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000043 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000043 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000043 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 30571.503894 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 30571.503894 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 30571.503894 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 30571.503894 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 30571.503894 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 30571.503894 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 10581 # number of writebacks -system.cpu.icache.writebacks::total 10581 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12328 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 12328 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 12328 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 12328 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 12328 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 12328 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 364558500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 364558500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 364558500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 364558500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 364558500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 364558500 # 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average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 29571.585010 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 29571.585010 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 521167228000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 259984 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32658.667775 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1287369 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 292752 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.397473 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 3857784000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 51.730334 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 79.865838 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 32527.071603 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.001579 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002437 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.992647 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.996663 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 151 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 294 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2875 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29149 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 12933736 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 12933736 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 521167228000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 88440 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 88440 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 10581 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 10581 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 2366 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 2366 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 9421 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 9421 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 488900 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 488900 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 9421 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 491266 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 500687 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 9421 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 491266 # number of overall hits -system.cpu.l2cache.overall_hits::total 500687 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 66645 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 66645 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2907 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 2907 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222744 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 222744 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2907 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 289389 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 292296 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2907 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 289389 # number of overall misses -system.cpu.l2cache.overall_misses::total 292296 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5373301500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5373301500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 247147500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 247147500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 30009565500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 30009565500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 247147500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 35382867000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 35630014500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 247147500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 35382867000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 35630014500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 88440 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 88440 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 10581 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 10581 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 69011 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 69011 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 12328 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 12328 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 711644 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 711644 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 12328 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 780655 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 792983 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 12328 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 780655 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 792983 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.965716 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.965716 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.235805 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.235805 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312999 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312999 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.235805 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.370700 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.368603 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.235805 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.370700 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.368603 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80625.725861 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80625.725861 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 85018.059856 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 85018.059856 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 134726.706443 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 134726.706443 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 85018.059856 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 122267.491162 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 121897.030750 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 85018.059856 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 122267.491162 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 121897.030750 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 66683 # number of writebacks -system.cpu.l2cache.writebacks::total 66683 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 1 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66645 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 66645 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2907 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2907 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222744 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222744 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2907 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 289389 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 292296 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2907 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 289389 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 292296 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4706851500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4706851500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 218087500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 218087500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 27782125500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 27782125500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 218087500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 32488977000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 32707064500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 218087500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 32488977000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 32707064500 # number of overall MSHR miss cycles -system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.965716 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.965716 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.235805 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.235805 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312999 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312999 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.235805 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.370700 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.368603 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.235805 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.370700 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.368603 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70625.725861 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70625.725861 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 75021.499828 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 75021.499828 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 124726.706443 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 124726.706443 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 75021.499828 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 112267.491162 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 111897.064962 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 75021.499828 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 112267.491162 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 111897.064962 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 1580123 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 787140 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2096 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2096 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 521167228000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 723971 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 155123 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 10581 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 881420 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 69011 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 69011 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 12328 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 711644 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 35236 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2337869 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2373105 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1466112 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55622080 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 57088192 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 259984 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 4267712 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 1052967 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.001991 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.044571 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1050871 99.80% 99.80% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2096 0.20% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1052967 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 889082500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 18490500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1170982500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 550183 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 257888 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 521167228000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 225650 # Transaction distribution -system.membus.trans_dist::WritebackDirty 66683 # Transaction distribution -system.membus.trans_dist::CleanEvict 191205 # Transaction distribution -system.membus.trans_dist::ReadExReq 66645 # Transaction distribution -system.membus.trans_dist::ReadExResp 66645 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 225650 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 842478 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 842478 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22974592 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22974592 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 292295 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 292295 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 292295 # Request fanout histogram -system.membus.reqLayer0.occupancy 925387500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 1555624500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.3 # Layer utilization (%) - ----------- End Simulation Statistics ---------- |