diff options
Diffstat (limited to 'tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt')
| -rw-r--r-- | tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt | 910 |
1 files changed, 458 insertions, 452 deletions
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt index f21f0115d..cfec5db38 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt @@ -1,70 +1,70 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.508216 # Number of seconds simulated -sim_ticks 508215534000 # Number of ticks simulated -final_tick 508215534000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.508441 # Number of seconds simulated +sim_ticks 508441445000 # Number of ticks simulated +final_tick 508441445000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 266071 # Simulator instruction rate (inst/s) -host_op_rate 266071 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 145588775 # Simulator tick rate (ticks/s) -host_mem_usage 258712 # Number of bytes of host memory used -host_seconds 3490.76 # Real time elapsed on the host +host_inst_rate 272638 # Simulator instruction rate (inst/s) +host_op_rate 272638 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 149248503 # Simulator tick rate (ticks/s) +host_mem_usage 263860 # Number of bytes of host memory used +host_seconds 3406.68 # Real time elapsed on the host sim_insts 928789150 # Number of instructions simulated sim_ops 928789150 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 508215534000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 185920 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 18520192 # Number of bytes read from this memory -system.physmem.bytes_read::total 18706112 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 185920 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 185920 # Number of instructions bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 508441445000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 185856 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18520896 # Number of bytes read from this memory +system.physmem.bytes_read::total 18706752 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 185856 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 185856 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4267712 # Number of bytes written to this memory system.physmem.bytes_written::total 4267712 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2905 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 289378 # Number of read requests responded to by this memory -system.physmem.num_reads::total 292283 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2904 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 289389 # Number of read requests responded to by this memory +system.physmem.num_reads::total 292293 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 365829 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 36441609 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 36807438 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 365829 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 365829 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 8397445 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 8397445 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 8397445 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 365829 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 36441609 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 45204883 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 292283 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 365541 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 36426802 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 36792343 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 365541 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 365541 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 8393714 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 8393714 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 8393714 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 365541 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 36426802 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 45186057 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 292293 # Number of read requests accepted system.physmem.writeReqs 66683 # Number of write requests accepted -system.physmem.readBursts 292283 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 292293 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 66683 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 18687040 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 19072 # Total number of bytes read from write queue -system.physmem.bytesWritten 4265984 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 18706112 # Total read bytes from the system interface side +system.physmem.bytesReadDRAM 18685888 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 20864 # Total number of bytes read from write queue +system.physmem.bytesWritten 4266496 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 18706752 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 4267712 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 298 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 326 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 18032 # Per bank write bursts -system.physmem.perBankRdBursts::1 18362 # Per bank write bursts -system.physmem.perBankRdBursts::2 18398 # Per bank write bursts -system.physmem.perBankRdBursts::3 18335 # Per bank write bursts -system.physmem.perBankRdBursts::4 18250 # Per bank write bursts -system.physmem.perBankRdBursts::5 18255 # Per bank write bursts -system.physmem.perBankRdBursts::6 18321 # Per bank write bursts -system.physmem.perBankRdBursts::7 18295 # Per bank write bursts -system.physmem.perBankRdBursts::8 18232 # Per bank write bursts -system.physmem.perBankRdBursts::9 18236 # Per bank write bursts -system.physmem.perBankRdBursts::10 18232 # Per bank write bursts -system.physmem.perBankRdBursts::11 18379 # Per bank write bursts -system.physmem.perBankRdBursts::12 18271 # Per bank write bursts -system.physmem.perBankRdBursts::13 18134 # Per bank write bursts -system.physmem.perBankRdBursts::14 18060 # Per bank write bursts -system.physmem.perBankRdBursts::15 18193 # Per bank write bursts +system.physmem.perBankRdBursts::0 18028 # Per bank write bursts +system.physmem.perBankRdBursts::1 18361 # Per bank write bursts +system.physmem.perBankRdBursts::2 18399 # Per bank write bursts +system.physmem.perBankRdBursts::3 18347 # Per bank write bursts +system.physmem.perBankRdBursts::4 18249 # Per bank write bursts +system.physmem.perBankRdBursts::5 18247 # Per bank write bursts +system.physmem.perBankRdBursts::6 18319 # Per bank write bursts +system.physmem.perBankRdBursts::7 18291 # Per bank write bursts +system.physmem.perBankRdBursts::8 18230 # Per bank write bursts +system.physmem.perBankRdBursts::9 18239 # Per bank write bursts +system.physmem.perBankRdBursts::10 18229 # Per bank write bursts +system.physmem.perBankRdBursts::11 18377 # Per bank write bursts +system.physmem.perBankRdBursts::12 18268 # Per bank write bursts +system.physmem.perBankRdBursts::13 18136 # Per bank write bursts +system.physmem.perBankRdBursts::14 18057 # Per bank write bursts +system.physmem.perBankRdBursts::15 18190 # Per bank write bursts system.physmem.perBankWrBursts::0 4125 # Per bank write bursts system.physmem.perBankWrBursts::1 4164 # Per bank write bursts system.physmem.perBankWrBursts::2 4223 # Per bank write bursts @@ -74,7 +74,7 @@ system.physmem.perBankWrBursts::5 4099 # Pe system.physmem.perBankWrBursts::6 4262 # Per bank write bursts system.physmem.perBankWrBursts::7 4226 # Per bank write bursts system.physmem.perBankWrBursts::8 4233 # Per bank write bursts -system.physmem.perBankWrBursts::9 4180 # Per bank write bursts +system.physmem.perBankWrBursts::9 4188 # Per bank write bursts system.physmem.perBankWrBursts::10 4150 # Per bank write bursts system.physmem.perBankWrBursts::11 4241 # Per bank write bursts system.physmem.perBankWrBursts::12 4098 # Per bank write bursts @@ -83,14 +83,14 @@ system.physmem.perBankWrBursts::14 4096 # Pe system.physmem.perBankWrBursts::15 4157 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 508215452500 # Total gap between requests +system.physmem.totGap 508441362500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 292283 # Read request sizes (log2) +system.physmem.readPktSize::6 292293 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -98,8 +98,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66683 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 291508 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 465 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 291491 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 464 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 12 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -145,25 +145,25 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 936 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 937 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4046 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4049 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4051 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4049 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4049 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 907 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 908 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4049 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4053 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4054 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4053 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4053 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4053 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4053 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4054 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4054 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4055 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4055 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4054 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4053 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4054 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4053 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4053 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see @@ -194,97 +194,97 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 103603 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 221.521925 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 143.541969 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 268.372247 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 37864 36.55% 36.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 43808 42.28% 78.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 9097 8.78% 87.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 745 0.72% 88.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1395 1.35% 89.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1153 1.11% 90.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 627 0.61% 91.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 610 0.59% 91.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8304 8.02% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 103603 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4049 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 69.361324 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 34.573478 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 739.455375 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 4041 99.80% 99.80% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 103424 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 221.899134 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 143.895688 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 268.440022 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 37597 36.35% 36.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 43798 42.35% 78.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 9078 8.78% 87.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 804 0.78% 88.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1585 1.53% 89.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1026 0.99% 90.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 543 0.53% 91.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 660 0.64% 91.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8333 8.06% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 103424 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4053 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 71.164816 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 34.696519 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 767.230213 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 4045 99.80% 99.80% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.83% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::8192-9215 1 0.02% 99.85% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14336-15359 4 0.10% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::15360-16383 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14336-15359 4 0.10% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::15360-16383 2 0.05% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::30720-31743 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4049 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4049 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.462336 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.441628 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.843264 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3113 76.88% 76.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 936 23.12% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4049 # Writes before turning the bus around for reads -system.physmem.totQLat 2518388500 # Total ticks spent queuing -system.physmem.totMemAccLat 7993107250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1459925000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8625.06 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 4053 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4053 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.448063 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.427763 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.835172 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3146 77.62% 77.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 906 22.35% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4053 # Writes before turning the bus around for reads +system.physmem.totQLat 2452616250 # Total ticks spent queuing +system.physmem.totMemAccLat 7926997500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1459835000 # Total ticks spent in databus transfers +system.physmem.avgQLat 8400.32 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27375.06 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 36.77 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 27150.32 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 36.75 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 8.39 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 36.81 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 8.40 # Average system write bandwidth in MiByte/s +system.physmem.avgRdBWSys 36.79 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 8.39 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.35 # Data bus utilization in percentage system.physmem.busUtilRead 0.29 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.07 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.41 # Average write queue length when enqueuing -system.physmem.readRowHits 203026 # Number of row buffer hits during reads -system.physmem.writeRowHits 52001 # Number of row buffer hits during writes -system.physmem.readRowHitRate 69.53 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 77.98 # Row buffer hit rate for writes -system.physmem.avgGap 1415776.01 # Average gap between requests -system.physmem.pageHitRate 71.10 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 390708360 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 213184125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1140250800 # Energy for read commands per rank (pJ) +system.physmem.avgWrQLen 24.39 # Average write queue length when enqueuing +system.physmem.readRowHits 203097 # Number of row buffer hits during reads +system.physmem.writeRowHits 52099 # Number of row buffer hits during writes +system.physmem.readRowHitRate 69.56 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.13 # Row buffer hit rate for writes +system.physmem.avgGap 1416365.89 # Average gap between requests +system.physmem.pageHitRate 71.15 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 390353040 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 212990250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1140196200 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 216438480 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 33193711200 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 103572972045 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 214071794250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 352799059260 # Total energy per rank (pJ) -system.physmem_0.averagePower 694.201008 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 355459552750 # Time in different power states -system.physmem_0.memoryStateTime::REF 16970200000 # Time in different power states +system.physmem_0.refreshEnergy 33208459440 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 103170345705 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 214560479250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 352899262365 # Total energy per rank (pJ) +system.physmem_0.averagePower 694.089734 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 356274409500 # Time in different power states +system.physmem_0.memoryStateTime::REF 16977740000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 135779058500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 135182501000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 392424480 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 214120500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1136545800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 215492400 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 33193711200 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 103467236760 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 214164544500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 352784075640 # Total energy per rank (pJ) -system.physmem_1.averagePower 694.171524 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 355611467750 # Time in different power states -system.physmem_1.memoryStateTime::REF 16970200000 # Time in different power states +system.physmem_1.actEnergy 391426560 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 213576000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1136460000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 215544240 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 33208459440 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 103438175310 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 214325517750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 352929159300 # Total energy per rank (pJ) +system.physmem_1.averagePower 694.148589 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 355878371250 # Time in different power states +system.physmem_1.memoryStateTime::REF 16977740000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 135627775750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 135579179250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 508215534000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 123851653 # Number of BP lookups +system.pwrStateResidencyTicks::UNDEFINED 508441445000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 123851654 # Number of BP lookups system.cpu.branchPred.condPredicted 79872946 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 686743 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 102066131 # Number of BTB lookups -system.cpu.branchPred.BTBHits 68190141 # Number of BTB hits +system.cpu.branchPred.BTBLookups 102066133 # Number of BTB lookups +system.cpu.branchPred.BTBHits 68190143 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 66.809764 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 18697400 # Number of times the RAS was used to get a target. +system.cpu.branchPred.usedRAS 18697398 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 11224 # Number of incorrect RAS predictions. system.cpu.branchPred.indirectLookups 14052177 # Number of indirect predictor lookups. system.cpu.branchPred.indirectHits 14048616 # Number of indirect target hits. @@ -299,18 +299,18 @@ system.cpu.dtb.read_hits 237539296 # DT system.cpu.dtb.read_misses 195211 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations system.cpu.dtb.read_accesses 237734507 # DTB read accesses -system.cpu.dtb.write_hits 98305020 # DTB write hits +system.cpu.dtb.write_hits 98305021 # DTB write hits system.cpu.dtb.write_misses 7170 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 98312190 # DTB write accesses -system.cpu.dtb.data_hits 335844316 # DTB hits +system.cpu.dtb.write_accesses 98312191 # DTB write accesses +system.cpu.dtb.data_hits 335844317 # DTB hits system.cpu.dtb.data_misses 202381 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 336046697 # DTB accesses -system.cpu.itb.fetch_hits 286584409 # ITB hits +system.cpu.dtb.data_accesses 336046698 # DTB accesses +system.cpu.itb.fetch_hits 286584411 # ITB hits system.cpu.itb.fetch_misses 119 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 286584528 # ITB accesses +system.cpu.itb.fetch_accesses 286584530 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -324,16 +324,16 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 37 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 508215534000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 1016431068 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 508441445000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 1016882890 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 928789150 # Number of instructions committed system.cpu.committedOps 928789150 # Number of ops (including micro ops) committed -system.cpu.discardedOps 319592 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 319599 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.094361 # CPI: cycles per instruction -system.cpu.ipc 0.913775 # IPC: instructions per cycle +system.cpu.cpi 1.094848 # CPI: cycles per instruction +system.cpu.ipc 0.913369 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 86206875 9.28% 9.28% # Class of committed instruction system.cpu.op_class_0::IntAlu 486529511 52.38% 61.66% # Class of committed instruction system.cpu.op_class_0::IntMult 7040 0.00% 61.67% # Class of committed instruction @@ -369,36 +369,36 @@ system.cpu.op_class_0::MemWrite 98308071 10.58% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 928789150 # Class of committed instruction -system.cpu.tickCycles 962815750 # Number of cycles that the object actually ticked -system.cpu.idleCycles 53615318 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 508215534000 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 962815783 # Number of cycles that the object actually ticked +system.cpu.idleCycles 54067107 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 508441445000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 776559 # number of replacements -system.cpu.dcache.tags.tagsinuse 4092.348104 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 320318733 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 4092.323693 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 320318732 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 780655 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 410.320478 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 905242500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4092.348104 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999108 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999108 # Average percentage of cache occupancy +system.cpu.dcache.tags.avg_refs 410.320477 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 911974500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4092.323693 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999102 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999102 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 213 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 955 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 212 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 956 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 1381 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1491 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 643115729 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 643115729 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 508215534000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 222154684 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 222154684 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 643115727 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 643115727 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 508441445000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 222154683 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 222154683 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 98164049 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 98164049 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 320318733 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 320318733 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 320318733 # number of overall hits -system.cpu.dcache.overall_hits::total 320318733 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 320318732 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 320318732 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 320318732 # number of overall hits +system.cpu.dcache.overall_hits::total 320318732 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 711653 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 711653 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 137151 # number of WriteReq misses @@ -407,22 +407,22 @@ system.cpu.dcache.demand_misses::cpu.data 848804 # n system.cpu.dcache.demand_misses::total 848804 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 848804 # number of overall misses system.cpu.dcache.overall_misses::total 848804 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 24412597000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 24412597000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10105115500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10105115500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 34517712500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 34517712500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 34517712500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 34517712500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 222866337 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 222866337 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 24607511500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 24607511500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10163393500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10163393500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 34770905000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 34770905000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 34770905000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 34770905000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 222866336 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 222866336 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 321167537 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 321167537 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 321167537 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 321167537 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 321167536 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 321167536 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 321167536 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 321167536 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003193 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.003193 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001395 # miss rate for WriteReq accesses @@ -431,22 +431,22 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002643 system.cpu.dcache.demand_miss_rate::total 0.002643 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002643 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002643 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34304.073755 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 34304.073755 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73678.759178 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 73678.759178 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 40666.293396 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 40666.293396 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 40666.293396 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 40666.293396 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34577.963558 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 34577.963558 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74103.677698 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 74103.677698 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 40964.586642 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 40964.586642 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 40964.586642 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 40964.586642 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 88481 # number of writebacks -system.cpu.dcache.writebacks::total 88481 # number of writebacks +system.cpu.dcache.writebacks::writebacks 88440 # number of writebacks +system.cpu.dcache.writebacks::total 88440 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 9 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 9 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68140 # number of WriteReq MSHR hits @@ -463,14 +463,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 780655 system.cpu.dcache.demand_mshr_misses::total 780655 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 780655 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 780655 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23700262500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 23700262500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5068010000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5068010000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28768272500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 28768272500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28768272500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 28768272500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23895183000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 23895183000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5097981500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5097981500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28993164500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 28993164500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28993164500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 28993164500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003193 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003193 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000702 # mshr miss rate for WriteReq accesses @@ -479,24 +479,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002431 system.cpu.dcache.demand_mshr_miss_rate::total 0.002431 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002431 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002431 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33303.537302 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33303.537302 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73437.712828 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73437.712828 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36851.454868 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 36851.454868 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36851.454868 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 36851.454868 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 508215534000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 10580 # number of replacements -system.cpu.icache.tags.tagsinuse 1690.197843 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 286572082 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 12326 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 23249.398183 # Average number of references to valid blocks. +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33577.439000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33577.439000 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73872.013157 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73872.013157 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37139.536031 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 37139.536031 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37139.536031 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 37139.536031 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 508441445000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 10578 # number of replacements +system.cpu.icache.tags.tagsinuse 1690.178313 # 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Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 105 # Occupied blocks per task id @@ -504,181 +504,181 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 2 system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1576 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.852539 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 573181144 # Number of tag accesses -system.cpu.icache.tags.data_accesses 573181144 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 508215534000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 286572082 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 286572082 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 286572082 # 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average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 28646.345421 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28773.346856 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 28773.346856 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 28773.346856 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 28773.346856 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 28773.346856 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 28773.346856 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # 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number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 340797500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 340797500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 340797500 # number of overall MSHR miss cycles +system.cpu.icache.writebacks::writebacks 10578 # number of writebacks +system.cpu.icache.writebacks::total 10578 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12325 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 12325 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 12325 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 12325 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 12325 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 12325 # 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mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000043 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000043 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27646.426543 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27646.426543 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27646.426543 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 27646.426543 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27646.426543 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 27646.426543 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 508215534000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 259960 # 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number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 289389 # number of overall misses +system.cpu.l2cache.overall_misses::total 292294 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4969595000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4969595000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 224911500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 224911500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 17694256000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 17694256000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 224911500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 22663851000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 22888762500 # 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number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 12327 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 12325 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 12325 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 711644 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::total 711644 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 12327 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 12325 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 780655 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 792982 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 12327 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 792980 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 12325 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 780655 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 792982 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 792980 # number of overall (read+write) accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.965716 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.965716 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.235743 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.235743 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312984 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312984 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.235743 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.370686 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.368588 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.235743 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.370686 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.368588 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74118.433491 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74118.433491 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76871.300757 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76871.300757 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78565.906264 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78565.906264 # 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miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.370700 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.368602 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.235700 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.370700 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.368602 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74568.159652 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74568.159652 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77422.203098 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77422.203098 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 79437.632439 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 79437.632439 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77422.203098 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78316.214507 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 78307.329264 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77422.203098 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78316.214507 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 78307.329264 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -691,120 +691,126 @@ system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1 system.cpu.l2cache.CleanEvict_mshr_misses::total 1 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19769961000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 19965832500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 195871500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19769961000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 19965832500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.965716 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.965716 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.235743 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.235743 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312984 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312984 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.235743 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.370686 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.368588 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.235743 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.370686 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.368588 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64118.433491 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64118.433491 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66874.741913 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66874.741913 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 68565.906264 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 68565.906264 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66874.741913 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67541.634126 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67535.003627 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66874.741913 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67541.634126 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67535.003627 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 1580121 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 787139 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.235700 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.235700 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312999 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312999 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.235700 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.370700 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.368602 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.235700 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.370700 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.368602 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64568.159652 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64568.159652 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67425.645439 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67425.645439 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69437.632439 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69437.632439 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67425.645439 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68316.214507 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68307.363476 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67425.645439 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68316.214507 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68307.363476 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 1580117 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 787137 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2087 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2087 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2095 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2095 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 508215534000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 723970 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 155164 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 10580 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 881355 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 508441445000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 723968 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 155123 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 10578 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 881417 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 69011 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 69011 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 12327 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 12325 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 711644 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 35233 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 35227 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2337869 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2373102 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1465984 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55624704 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 57090688 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 259960 # Total snoops (count) +system.cpu.toL2Bus.pkt_count::total 2373096 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1465728 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55622080 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 57087808 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 259981 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 4267712 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 1052942 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.001982 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.044476 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 1052961 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.001990 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.044561 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1050855 99.80% 99.80% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2087 0.20% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1050866 99.80% 99.80% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2095 0.20% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1052942 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 889121500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1052961 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 889076500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 18489000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 18486000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 1170982999 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 508215534000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 225638 # Transaction distribution +system.membus.snoop_filter.tot_requests 550179 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 257886 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 508441445000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 225648 # Transaction distribution system.membus.trans_dist::WritebackDirty 66683 # Transaction distribution -system.membus.trans_dist::CleanEvict 191190 # Transaction distribution +system.membus.trans_dist::CleanEvict 191203 # Transaction distribution system.membus.trans_dist::ReadExReq 66645 # Transaction distribution system.membus.trans_dist::ReadExResp 66645 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 225638 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 842439 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 842439 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22973824 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22973824 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 225648 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 842472 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 842472 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22974464 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22974464 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 550156 # Request fanout histogram +system.membus.snoop_fanout::samples 292293 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 550156 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 292293 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 550156 # Request fanout histogram -system.membus.reqLayer0.occupancy 925402000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 292293 # Request fanout histogram +system.membus.reqLayer0.occupancy 925378500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 1556718500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1556878500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- |