diff options
Diffstat (limited to 'tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt')
| -rw-r--r-- | tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt | 905 |
1 files changed, 462 insertions, 443 deletions
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt index efccfaef5..f751a40d2 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt @@ -1,69 +1,69 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.561049 # Number of seconds simulated -sim_ticks 561048999000 # Number of ticks simulated -final_tick 561048999000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.560940 # Number of seconds simulated +sim_ticks 560939897000 # Number of ticks simulated +final_tick 560939897000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 327042 # Simulator instruction rate (inst/s) -host_op_rate 327042 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 197554566 # Simulator tick rate (ticks/s) -host_mem_usage 305844 # Number of bytes of host memory used -host_seconds 2839.97 # Real time elapsed on the host +host_inst_rate 309766 # Simulator instruction rate (inst/s) +host_op_rate 309766 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 187082277 # Simulator tick rate (ticks/s) +host_mem_usage 305868 # Number of bytes of host memory used +host_seconds 2998.36 # Real time elapsed on the host sim_insts 928789150 # Number of instructions simulated sim_ops 928789150 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 186944 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 18470400 # Number of bytes read from this memory -system.physmem.bytes_read::total 18657344 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 186944 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 186944 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 186880 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18514240 # Number of bytes read from this memory +system.physmem.bytes_read::total 18701120 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 186880 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 186880 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4267712 # Number of bytes written to this memory system.physmem.bytes_written::total 4267712 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2921 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 288600 # Number of read requests responded to by this memory -system.physmem.num_reads::total 291521 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2920 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 289285 # Number of read requests responded to by this memory +system.physmem.num_reads::total 292205 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 333204 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 32921189 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 33254393 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 333204 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 333204 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 7606665 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 7606665 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 7606665 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 333204 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 32921189 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 40861059 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 291521 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 333155 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 33005746 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 33338902 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 333155 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 333155 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 7608145 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 7608145 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 7608145 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 333155 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 33005746 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 40947046 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 292205 # Number of read requests accepted system.physmem.writeReqs 66683 # Number of write requests accepted -system.physmem.readBursts 291521 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 292205 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 66683 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 18639104 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 18240 # Total number of bytes read from write queue -system.physmem.bytesWritten 4266496 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 18657344 # Total read bytes from the system interface side +system.physmem.bytesReadDRAM 18680832 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 20288 # Total number of bytes read from write queue +system.physmem.bytesWritten 4266304 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 18701120 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 4267712 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 285 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 317 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 17937 # Per bank write bursts -system.physmem.perBankRdBursts::1 18285 # Per bank write bursts -system.physmem.perBankRdBursts::2 18301 # Per bank write bursts -system.physmem.perBankRdBursts::3 18253 # Per bank write bursts -system.physmem.perBankRdBursts::4 18160 # Per bank write bursts -system.physmem.perBankRdBursts::5 18247 # Per bank write bursts -system.physmem.perBankRdBursts::6 18325 # Per bank write bursts -system.physmem.perBankRdBursts::7 18297 # Per bank write bursts -system.physmem.perBankRdBursts::8 18227 # Per bank write bursts -system.physmem.perBankRdBursts::9 18224 # Per bank write bursts -system.physmem.perBankRdBursts::10 18215 # Per bank write bursts -system.physmem.perBankRdBursts::11 18384 # Per bank write bursts -system.physmem.perBankRdBursts::12 18260 # Per bank write bursts -system.physmem.perBankRdBursts::13 18042 # Per bank write bursts -system.physmem.perBankRdBursts::14 17980 # Per bank write bursts -system.physmem.perBankRdBursts::15 18099 # Per bank write bursts +system.physmem.perBankRdBursts::0 18030 # Per bank write bursts +system.physmem.perBankRdBursts::1 18359 # Per bank write bursts +system.physmem.perBankRdBursts::2 18394 # Per bank write bursts +system.physmem.perBankRdBursts::3 18343 # Per bank write bursts +system.physmem.perBankRdBursts::4 18248 # Per bank write bursts +system.physmem.perBankRdBursts::5 18243 # Per bank write bursts +system.physmem.perBankRdBursts::6 18313 # Per bank write bursts +system.physmem.perBankRdBursts::7 18291 # Per bank write bursts +system.physmem.perBankRdBursts::8 18223 # Per bank write bursts +system.physmem.perBankRdBursts::9 18225 # Per bank write bursts +system.physmem.perBankRdBursts::10 18213 # Per bank write bursts +system.physmem.perBankRdBursts::11 18377 # Per bank write bursts +system.physmem.perBankRdBursts::12 18256 # Per bank write bursts +system.physmem.perBankRdBursts::13 18128 # Per bank write bursts +system.physmem.perBankRdBursts::14 18060 # Per bank write bursts +system.physmem.perBankRdBursts::15 18185 # Per bank write bursts system.physmem.perBankWrBursts::0 4125 # Per bank write bursts system.physmem.perBankWrBursts::1 4164 # Per bank write bursts system.physmem.perBankWrBursts::2 4223 # Per bank write bursts @@ -73,7 +73,7 @@ system.physmem.perBankWrBursts::5 4099 # Pe system.physmem.perBankWrBursts::6 4262 # Per bank write bursts system.physmem.perBankWrBursts::7 4226 # Per bank write bursts system.physmem.perBankWrBursts::8 4233 # Per bank write bursts -system.physmem.perBankWrBursts::9 4188 # Per bank write bursts +system.physmem.perBankWrBursts::9 4185 # Per bank write bursts system.physmem.perBankWrBursts::10 4150 # Per bank write bursts system.physmem.perBankWrBursts::11 4241 # Per bank write bursts system.physmem.perBankWrBursts::12 4098 # Per bank write bursts @@ -82,14 +82,14 @@ system.physmem.perBankWrBursts::14 4096 # Pe system.physmem.perBankWrBursts::15 4157 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 561048916000 # Total gap between requests +system.physmem.totGap 560939815000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 291521 # Read request sizes (log2) +system.physmem.readPktSize::6 292205 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -97,7 +97,7 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66683 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 290732 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 291384 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 475 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 29 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -144,24 +144,24 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1004 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1004 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4041 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4041 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4041 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4041 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4041 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4041 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4041 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4041 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4043 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4041 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4041 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4041 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4041 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4041 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 938 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 938 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4049 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4050 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4050 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4050 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4050 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4049 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4049 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4049 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4049 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4049 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4050 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4051 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4049 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4050 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4049 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4049 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -193,117 +193,119 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 105209 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 217.703657 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 140.847395 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 266.018983 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 39852 37.88% 37.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 43676 41.51% 79.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8737 8.30% 87.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 846 0.80% 88.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1608 1.53% 90.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1088 1.03% 91.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 546 0.52% 91.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 586 0.56% 92.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8270 7.86% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 105209 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4041 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 71.193764 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 36.202156 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 784.629260 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 4034 99.83% 99.83% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::12288-14335 1 0.02% 99.85% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14336-16383 5 0.12% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::32768-34815 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4041 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4041 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.496907 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.475096 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.865198 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3038 75.18% 75.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 1001 24.77% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 2 0.05% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4041 # Writes before turning the bus around for reads -system.physmem.totQLat 2859634000 # Total ticks spent queuing -system.physmem.totMemAccLat 8320309000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1456180000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9818.96 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 103977 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 220.682651 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 142.922946 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 267.989820 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 38271 36.81% 36.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 43979 42.30% 79.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8888 8.55% 87.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 756 0.73% 88.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1408 1.35% 89.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1167 1.12% 90.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 628 0.60% 91.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 577 0.55% 92.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8303 7.99% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 103977 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4049 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 70.413929 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 34.545155 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 755.096124 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 4041 99.80% 99.80% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.83% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::12288-13311 1 0.02% 99.85% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::13312-14335 2 0.05% 99.90% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::15360-16383 3 0.07% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::30720-31743 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 4049 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4049 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.463571 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.442765 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.845366 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3112 76.86% 76.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 934 23.07% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 3 0.07% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4049 # Writes before turning the bus around for reads +system.physmem.totQLat 2918754250 # Total ticks spent queuing +system.physmem.totMemAccLat 8391654250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1459440000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9999.57 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28568.96 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 33.22 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 7.60 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 33.25 # Average system read bandwidth in MiByte/s +system.physmem.avgMemAccLat 28749.57 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 33.30 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 7.61 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 33.34 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 7.61 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.32 # Data bus utilization in percentage system.physmem.busUtilRead 0.26 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.36 # Average write queue length when enqueuing -system.physmem.readRowHits 202235 # Number of row buffer hits during reads -system.physmem.writeRowHits 50448 # Number of row buffer hits during writes -system.physmem.readRowHitRate 69.44 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.65 # Row buffer hit rate for writes -system.physmem.avgGap 1566283.22 # Average gap between requests -system.physmem.pageHitRate 70.60 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 396718560 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 216463500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1137021600 # Energy for read commands per rank (pJ) +system.physmem.avgWrQLen 24.25 # Average write queue length when enqueuing +system.physmem.readRowHits 202534 # Number of row buffer hits during reads +system.physmem.writeRowHits 52030 # Number of row buffer hits during writes +system.physmem.readRowHitRate 69.39 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.03 # Row buffer hit rate for writes +system.physmem.avgGap 1562994.07 # Average gap between requests +system.physmem.pageHitRate 70.99 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 391812120 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 213786375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1140274200 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 216438480 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 36644799360 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 109036341675 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 240981860250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 388629643425 # Total energy per rank (pJ) -system.physmem_0.averagePower 692.687306 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 400213963500 # Time in different power states -system.physmem_0.memoryStateTime::REF 18734560000 # Time in different power states +system.physmem_0.refreshEnergy 36637679520 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 109227211875 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 240749028000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 388576230570 # Total energy per rank (pJ) +system.physmem_0.averagePower 692.726692 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 399826633250 # Time in different power states +system.physmem_0.memoryStateTime::REF 18730920000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 142097780250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 142379745750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 398601000 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 217490625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1134307200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 215544240 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 36644799360 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 109322809425 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 240730572750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 388664124600 # Total energy per rank (pJ) -system.physmem_1.averagePower 692.748765 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 399791677000 # Time in different power states -system.physmem_1.memoryStateTime::REF 18734560000 # Time in different power states +system.physmem_1.actEnergy 394193520 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 215085750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1136148000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 215524800 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 36637679520 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 109501586505 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 240508346250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 388608564345 # Total energy per rank (pJ) +system.physmem_1.averagePower 692.784339 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 399420466000 # Time in different power states +system.physmem_1.memoryStateTime::REF 18730920000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 142520871000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 142786637000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 125749073 # Number of BP lookups -system.cpu.branchPred.condPredicted 81144364 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 12157127 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 103970968 # Number of BTB lookups -system.cpu.branchPred.BTBHits 83513050 # Number of BTB hits +system.cpu.branchPred.lookups 125749081 # Number of BP lookups +system.cpu.branchPred.condPredicted 81144339 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 12157133 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 103971313 # Number of BTB lookups +system.cpu.branchPred.BTBHits 83513402 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 80.323432 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 18691036 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 9451 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 80.323504 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 18691072 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 9449 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 237538495 # DTB read hits +system.cpu.dtb.read_hits 237538494 # DTB read hits system.cpu.dtb.read_misses 198467 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 237736962 # DTB read accesses -system.cpu.dtb.write_hits 98305062 # DTB write hits -system.cpu.dtb.write_misses 7206 # DTB write misses +system.cpu.dtb.read_accesses 237736961 # DTB read accesses +system.cpu.dtb.write_hits 98305022 # DTB write hits +system.cpu.dtb.write_misses 7216 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 98312268 # DTB write accesses -system.cpu.dtb.data_hits 335843557 # DTB hits -system.cpu.dtb.data_misses 205673 # DTB misses +system.cpu.dtb.write_accesses 98312238 # DTB write accesses +system.cpu.dtb.data_hits 335843516 # DTB hits +system.cpu.dtb.data_misses 205683 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 336049230 # DTB accesses -system.cpu.itb.fetch_hits 316986664 # ITB hits +system.cpu.dtb.data_accesses 336049199 # DTB accesses +system.cpu.itb.fetch_hits 316987000 # ITB hits system.cpu.itb.fetch_misses 120 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 316986784 # ITB accesses +system.cpu.itb.fetch_accesses 316987120 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -317,67 +319,67 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 37 # Number of system calls -system.cpu.numCycles 1122097998 # number of cpu cycles simulated +system.cpu.numCycles 1121879794 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 928789150 # Number of instructions committed system.cpu.committedOps 928789150 # Number of ops (including micro ops) committed -system.cpu.discardedOps 30863568 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 30863449 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.208130 # CPI: cycles per instruction -system.cpu.ipc 0.827726 # IPC: instructions per cycle -system.cpu.tickCycles 1059712720 # Number of cycles that the object actually ticked -system.cpu.idleCycles 62385278 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.207895 # CPI: cycles per instruction +system.cpu.ipc 0.827887 # IPC: instructions per cycle +system.cpu.tickCycles 1059714780 # Number of cycles that the object actually ticked +system.cpu.idleCycles 62165014 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 776532 # number of replacements -system.cpu.dcache.tags.tagsinuse 4092.688853 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 322867255 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 4092.723334 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 322867251 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 780628 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 413.599378 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 907886250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4092.688853 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999192 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999192 # Average percentage of cache occupancy +system.cpu.dcache.tags.avg_refs 413.599373 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 899878500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4092.723334 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999200 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999200 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 204 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 203 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 952 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 1242 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1642 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 648213290 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 648213290 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 224703202 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 224703202 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 98164053 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 98164053 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 322867255 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 322867255 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 322867255 # number of overall hits -system.cpu.dcache.overall_hits::total 322867255 # number of overall hits +system.cpu.dcache.tags.tag_accesses 648213288 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 648213288 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 224703201 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 224703201 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 98164050 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 98164050 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 322867251 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 322867251 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 322867251 # number of overall hits +system.cpu.dcache.overall_hits::total 322867251 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 711929 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 711929 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 137147 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 137147 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 849076 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 849076 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 849076 # number of overall misses -system.cpu.dcache.overall_misses::total 849076 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 24858122500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 24858122500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10112031250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10112031250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 34970153750 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 34970153750 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 34970153750 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 34970153750 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 225415131 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 225415131 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_misses::cpu.data 137150 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 137150 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 849079 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 849079 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 849079 # number of overall misses +system.cpu.dcache.overall_misses::total 849079 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 24888612000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 24888612000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9943107500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9943107500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 34831719500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 34831719500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 34831719500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 34831719500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 225415130 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 225415130 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 323716331 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 323716331 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 323716331 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 323716331 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 323716330 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 323716330 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 323716330 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 323716330 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003158 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.003158 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001395 # miss rate for WriteReq accesses @@ -386,14 +388,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002623 system.cpu.dcache.demand_miss_rate::total 0.002623 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002623 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002623 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34916.575248 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 34916.575248 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73731.333897 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 73731.333897 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 41186.129098 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 41186.129098 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 41186.129098 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 41186.129098 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34959.401850 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 34959.401850 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72498.049581 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 72498.049581 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 41022.943095 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 41022.943095 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 41022.943095 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 41022.943095 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -402,16 +404,16 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 91489 # number of writebacks -system.cpu.dcache.writebacks::total 91489 # number of writebacks +system.cpu.dcache.writebacks::writebacks 88848 # number of writebacks +system.cpu.dcache.writebacks::total 88848 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 312 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 312 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68136 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 68136 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 68448 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 68448 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 68448 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 68448 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68139 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 68139 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 68451 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 68451 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 68451 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 68451 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711617 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 711617 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69011 # number of WriteReq MSHR misses @@ -420,14 +422,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 780628 system.cpu.dcache.demand_mshr_misses::total 780628 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 780628 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 780628 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23712269000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 23712269000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5006644750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5006644750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28718913750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 28718913750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28718913750 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 28718913750 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24170012500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 24170012500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4987370000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4987370000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29157382500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 29157382500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29157382500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 29157382500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003157 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003157 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000702 # mshr miss rate for WriteReq accesses @@ -436,24 +438,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002411 system.cpu.dcache.demand_mshr_miss_rate::total 0.002411 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002411 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002411 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33321.673035 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33321.673035 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72548.503137 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72548.503137 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36789.499928 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 36789.499928 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36789.499928 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 36789.499928 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33964.917224 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33964.917224 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72269.203460 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72269.203460 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37351.187121 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 37351.187121 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37351.187121 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 37351.187121 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 10608 # number of replacements -system.cpu.icache.tags.tagsinuse 1686.311703 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 316974313 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 12350 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 25665.936275 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 10610 # number of replacements +system.cpu.icache.tags.tagsinuse 1686.330189 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 316974647 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 12352 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 25661.807562 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1686.311703 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.823394 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.823394 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1686.330189 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.823403 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.823403 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1742 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 104 # Occupied blocks per task id @@ -461,44 +463,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 2 system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1572 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.850586 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 633985678 # Number of tag accesses -system.cpu.icache.tags.data_accesses 633985678 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 316974313 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 316974313 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 316974313 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 316974313 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 316974313 # number of overall hits -system.cpu.icache.overall_hits::total 316974313 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 12351 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 12351 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 12351 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 12351 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 12351 # number of overall misses -system.cpu.icache.overall_misses::total 12351 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 355440500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 355440500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 355440500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 355440500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 355440500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 355440500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 316986664 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 316986664 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 316986664 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 316986664 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 316986664 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 316986664 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 633986352 # Number of tag accesses +system.cpu.icache.tags.data_accesses 633986352 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 316974647 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 316974647 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 316974647 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 316974647 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 316974647 # number of overall hits +system.cpu.icache.overall_hits::total 316974647 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 12353 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 12353 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 12353 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 12353 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 12353 # number of overall misses +system.cpu.icache.overall_misses::total 12353 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 352286000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 352286000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 352286000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 352286000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 352286000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 352286000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 316987000 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 316987000 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 316987000 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 316987000 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 316987000 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 316987000 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000039 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000039 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000039 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000039 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000039 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000039 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28778.277063 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 28778.277063 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 28778.277063 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 28778.277063 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 28778.277063 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 28778.277063 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28518.254675 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 28518.254675 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 28518.254675 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 28518.254675 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 28518.254675 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 28518.254675 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -507,123 +509,129 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12351 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 12351 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 12351 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 12351 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 12351 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 12351 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 335642500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 335642500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 335642500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 335642500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 335642500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 335642500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12353 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 12353 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 12353 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 12353 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 12353 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 12353 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 339934000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 339934000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 339934000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 339934000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 339934000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 339934000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000039 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000039 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000039 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27175.329933 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27175.329933 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27175.329933 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 27175.329933 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27175.329933 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 27175.329933 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27518.335627 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27518.335627 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27518.335627 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 27518.335627 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27518.335627 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 27518.335627 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 258742 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32592.002895 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 523848 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 291478 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 1.797213 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 259426 # number of replacements +system.cpu.l2cache.tags.tagsinuse 32593.023927 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1218366 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 292162 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.170173 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 2882.733111 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 84.797304 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 29624.472480 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.087974 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002588 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.904067 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.994629 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 2589.520333 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 84.221668 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 29919.281926 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.079026 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002570 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.913064 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.994660 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32736 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 117 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 214 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 213 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 272 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2658 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29475 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999023 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 7436233 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 7436233 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 9429 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 489662 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 499091 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 91489 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 91489 # number of Writeback hits +system.cpu.l2cache.tags.tag_accesses 13002157 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 13002157 # Number of data accesses +system.cpu.l2cache.Writeback_hits::writebacks 88848 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 88848 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 2366 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 2366 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 9429 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 492028 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 501457 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 9429 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 492028 # number of overall hits -system.cpu.l2cache.overall_hits::total 501457 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 2922 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 221955 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 224877 # number of ReadReq misses +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 9432 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 9432 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 488977 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 488977 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 9432 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 491343 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 500775 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 9432 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 491343 # number of overall hits +system.cpu.l2cache.overall_hits::total 500775 # number of overall hits system.cpu.l2cache.ReadExReq_misses::cpu.data 66645 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 66645 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2922 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 288600 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 291522 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2922 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 288600 # number of overall misses -system.cpu.l2cache.overall_misses::total 291522 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 224288000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17859188000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 18083476000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4912763250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4912763250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 224288000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 22771951250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 22996239250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 224288000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 22771951250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 22996239250 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 12351 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 711617 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 723968 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 91489 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 91489 # 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number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 792979 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 12351 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 792981 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 12353 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 780628 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 792979 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.236580 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.311902 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.310617 # miss rate for ReadReq accesses +system.cpu.l2cache.overall_accesses::total 792981 # number of overall (read+write) accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.965716 # 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miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.236461 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.370580 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.368491 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.236461 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.370580 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.368491 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72908.440243 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72908.440243 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76128.038343 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76128.038343 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80705.693047 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80705.693047 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76128.038343 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78909.374838 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 78881.571563 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76128.038343 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78909.374838 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 78881.571563 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -634,103 +642,114 @@ system.cpu.l2cache.fast_writes 0 # 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number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 19351356750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 187662000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19163694750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 19351356750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.236580 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.311902 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.310617 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2921 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2921 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222640 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222640 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2921 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 289285 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 292206 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2921 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 289285 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 292206 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4192533000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4192533000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 193170000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 193170000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15741915500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15741915500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 193170000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19934448500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 20127618500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 193170000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19934448500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 20127618500 # number of overall MSHR miss cycles +system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.965716 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.965716 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.236580 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.369702 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.367629 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.236580 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.369702 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.367629 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64223.819302 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67961.136266 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67912.574430 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61210.604697 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61210.604697 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64223.819302 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66402.268711 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66380.433552 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64223.819302 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66402.268711 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66380.433552 # average overall mshr miss latency +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.236461 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.236461 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312865 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312865 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.236461 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.370580 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.368491 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.236461 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.370580 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.368491 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62908.440243 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62908.440243 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66131.461828 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66131.461828 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70705.693047 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70705.693047 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66131.461828 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68909.374838 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68881.605785 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66131.461828 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68909.374838 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68881.605785 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 723968 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 723967 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 91489 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 723969 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 155531 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 891037 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 69011 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 69011 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 24701 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1652745 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1677446 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 790400 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55815488 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 56605888 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 884468 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadCleanReq 12353 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 711617 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 35315 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2337788 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2373103 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 790528 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55646464 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 56436992 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 259426 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 1839549 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.141027 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.348049 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 884468 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1580123 85.90% 85.90% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 259426 14.10% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 884468 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 533723000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 19161500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 1839549 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 878909500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 18528000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1222147750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1170942000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.trans_dist::ReadReq 224876 # Transaction distribution -system.membus.trans_dist::ReadResp 224876 # Transaction distribution +system.membus.trans_dist::ReadResp 225560 # Transaction distribution system.membus.trans_dist::Writeback 66683 # Transaction distribution +system.membus.trans_dist::CleanEvict 191116 # Transaction distribution system.membus.trans_dist::ReadExReq 66645 # Transaction distribution system.membus.trans_dist::ReadExResp 66645 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 649725 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 649725 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22925056 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22925056 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 225560 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 842209 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 842209 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22968832 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22968832 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 358204 # Request fanout histogram +system.membus.snoop_fanout::samples 550004 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 358204 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 550004 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 358204 # Request fanout histogram -system.membus.reqLayer0.occupancy 732288500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 1552393250 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 550004 # Request fanout histogram +system.membus.reqLayer0.occupancy 918579000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 1556120750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- |